tc_3000_300.c revision 1.37
1 /* $NetBSD: tc_3000_300.c,v 1.37 2020/09/25 03:40:11 thorpej Exp $ */ 2 3 /* 4 * Copyright (c) 1994, 1995, 1996 Carnegie-Mellon University. 5 * All rights reserved. 6 * 7 * Author: Chris G. Demetriou 8 * 9 * Permission to use, copy, modify and distribute this software and 10 * its documentation is hereby granted, provided that both the copyright 11 * notice and this permission notice appear in all copies of the 12 * software, derivative works or modified versions, and any portions 13 * thereof, and that both notices appear in supporting documentation. 14 * 15 * CARNEGIE MELLON ALLOWS FREE USE OF THIS SOFTWARE IN ITS "AS IS" 16 * CONDITION. CARNEGIE MELLON DISCLAIMS ANY LIABILITY OF ANY KIND 17 * FOR ANY DAMAGES WHATSOEVER RESULTING FROM THE USE OF THIS SOFTWARE. 18 * 19 * Carnegie Mellon requests users of this software to return to 20 * 21 * Software Distribution Coordinator or Software.Distribution (at) CS.CMU.EDU 22 * School of Computer Science 23 * Carnegie Mellon University 24 * Pittsburgh PA 15213-3890 25 * 26 * any improvements or extensions that they make and grant Carnegie the 27 * rights to redistribute these changes. 28 */ 29 30 #include <sys/cdefs.h> /* RCS ID & Copyright macro defns */ 31 32 __KERNEL_RCSID(0, "$NetBSD: tc_3000_300.c,v 1.37 2020/09/25 03:40:11 thorpej Exp $"); 33 34 #include <sys/param.h> 35 #include <sys/systm.h> 36 #include <sys/device.h> 37 #include <sys/malloc.h> 38 #include <sys/cpu.h> 39 40 #include <machine/autoconf.h> 41 #include <machine/pte.h> 42 43 #include <dev/tc/tcvar.h> 44 #include <dev/tc/ioasicreg.h> 45 #include <alpha/tc/tc_conf.h> 46 #include <alpha/tc/tc_3000_300.h> 47 48 #include "wsdisplay.h" 49 #include "sfb.h" 50 51 #if NSFB > 0 52 extern int sfb_cnattach(tc_addr_t); 53 #endif 54 55 int tc_3000_300_intrnull(void *); 56 57 #define C(x) ((void *)(u_long)x) 58 #define KV(x) (ALPHA_PHYS_TO_K0SEG(x)) 59 60 /* 61 * We have to read and modify the IOASIC registers directly, because 62 * the TC option slot interrupt request and mask bits are stored there, 63 * and the ioasic code isn't initted when we need to frob some interrupt 64 * bits. 65 */ 66 #define DEC_3000_300_IOASIC_ADDR KV(0x1a0000000) 67 68 struct tc_slotdesc tc_3000_300_slots[] = { 69 { KV(0x100000000), C(TC_3000_300_DEV_OPT0), }, /* 0 - opt slot 0 */ 70 { KV(0x120000000), C(TC_3000_300_DEV_OPT1), }, /* 1 - opt slot 1 */ 71 { KV(0x140000000), C(TC_3000_300_DEV_BOGUS), }, /* 2 - unused */ 72 { KV(0x160000000), C(TC_3000_300_DEV_BOGUS), }, /* 3 - unused */ 73 { KV(0x180000000), C(TC_3000_300_DEV_BOGUS), }, /* 4 - TCDS ASIC */ 74 { KV(0x1a0000000), C(TC_3000_300_DEV_BOGUS), }, /* 5 - IOCTL ASIC */ 75 { KV(0x1c0000000), C(TC_3000_300_DEV_BOGUS), }, /* 6 - CXTurbo */ 76 }; 77 int tc_3000_300_nslots = 78 sizeof(tc_3000_300_slots) / sizeof(tc_3000_300_slots[0]); 79 80 struct tc_builtin tc_3000_300_builtins[] = { 81 { "PMAGB-BA", 6, 0x02000000, C(TC_3000_300_DEV_CXTURBO), }, 82 { "FLAMG-IO", 5, 0x00000000, C(TC_3000_300_DEV_IOASIC), }, 83 { "PMAZ-DS ", 4, 0x00000000, C(TC_3000_300_DEV_TCDS), }, 84 }; 85 int tc_3000_300_nbuiltins = 86 sizeof(tc_3000_300_builtins) / sizeof(tc_3000_300_builtins[0]); 87 88 struct tcintr { 89 int (*tci_func)(void *); 90 void *tci_arg; 91 struct evcnt tci_evcnt; 92 } tc_3000_300_intr[TC_3000_300_NCOOKIES]; 93 94 void 95 tc_3000_300_intr_setup(void) 96 { 97 volatile uint32_t *imskp; 98 char *cp; 99 u_long i; 100 101 /* 102 * Disable all interrupts that we can (can't disable builtins). 103 */ 104 imskp = (volatile uint32_t *)(DEC_3000_300_IOASIC_ADDR + IOASIC_IMSK); 105 *imskp &= ~(IOASIC_INTR_300_OPT0 | IOASIC_INTR_300_OPT1); 106 107 /* 108 * Set up interrupt handlers. 109 */ 110 for (i = 0; i < TC_3000_300_NCOOKIES; i++) { 111 static const size_t len = 12; 112 tc_3000_300_intr[i].tci_func = tc_3000_300_intrnull; 113 tc_3000_300_intr[i].tci_arg = (void *)i; 114 115 cp = malloc(len, M_DEVBUF, M_WAITOK); 116 snprintf(cp, len, "slot %lu", i); 117 evcnt_attach_dynamic(&tc_3000_300_intr[i].tci_evcnt, 118 EVCNT_TYPE_INTR, NULL, "tc", cp); 119 } 120 } 121 122 const struct evcnt * 123 tc_3000_300_intr_evcnt(device_t tcadev, void *cookie) 124 { 125 u_long dev = (u_long)cookie; 126 127 #ifdef DIAGNOSTIC 128 /* XXX bounds-check cookie. */ 129 #endif 130 131 return (&tc_3000_300_intr[dev].tci_evcnt); 132 } 133 134 void 135 tc_3000_300_intr_establish(device_t tcadev, void *cookie, tc_intrlevel_t level, int (*func)(void *), void *arg) 136 { 137 volatile uint32_t *imskp; 138 u_long dev = (u_long)cookie; 139 140 #ifdef DIAGNOSTIC 141 /* XXX bounds-check cookie. */ 142 #endif 143 144 if (tc_3000_300_intr[dev].tci_func != tc_3000_300_intrnull) 145 panic("tc_3000_300_intr_establish: cookie %lu twice", dev); 146 147 const int s = splhigh(); 148 149 /* All TC systems are uniprocessors. */ 150 KASSERT(CPU_IS_PRIMARY(curcpu())); 151 KASSERT(ncpu == 1); 152 curcpu()->ci_nintrhand++; 153 154 tc_3000_300_intr[dev].tci_func = func; 155 tc_3000_300_intr[dev].tci_arg = arg; 156 157 splx(s); 158 159 imskp = (volatile uint32_t *)(DEC_3000_300_IOASIC_ADDR + IOASIC_IMSK); 160 switch (dev) { 161 case TC_3000_300_DEV_OPT0: 162 *imskp |= IOASIC_INTR_300_OPT0; 163 break; 164 case TC_3000_300_DEV_OPT1: 165 *imskp |= IOASIC_INTR_300_OPT1; 166 break; 167 default: 168 /* interrupts for builtins always enabled */ 169 break; 170 } 171 } 172 173 void 174 tc_3000_300_intr_disestablish(device_t tcadev, void *cookie) 175 { 176 volatile uint32_t *imskp; 177 u_long dev = (u_long)cookie; 178 179 #ifdef DIAGNOSTIC 180 /* XXX bounds-check cookie. */ 181 #endif 182 183 if (tc_3000_300_intr[dev].tci_func == tc_3000_300_intrnull) 184 panic("tc_3000_300_intr_disestablish: cookie %lu bad intr", 185 dev); 186 187 imskp = (volatile uint32_t *)(DEC_3000_300_IOASIC_ADDR + IOASIC_IMSK); 188 switch (dev) { 189 case TC_3000_300_DEV_OPT0: 190 *imskp &= ~IOASIC_INTR_300_OPT0; 191 break; 192 case TC_3000_300_DEV_OPT1: 193 *imskp &= ~IOASIC_INTR_300_OPT1; 194 break; 195 default: 196 /* interrupts for builtins always enabled */ 197 break; 198 } 199 200 const int s = splhigh(); 201 202 curcpu()->ci_nintrhand--; 203 204 tc_3000_300_intr[dev].tci_func = tc_3000_300_intrnull; 205 tc_3000_300_intr[dev].tci_arg = (void *)dev; 206 207 splx(s); 208 } 209 210 int 211 tc_3000_300_intrnull(void *val) 212 { 213 214 panic("tc_3000_300_intrnull: uncaught TC intr for cookie %ld", 215 (u_long)val); 216 } 217 218 void 219 tc_3000_300_iointr(void *arg, unsigned long vec) 220 { 221 uint32_t tcir, ioasicir, ioasicimr; 222 int ifound; 223 224 KERNEL_LOCK(1, NULL); 225 226 #ifdef DIAGNOSTIC 227 int s; 228 if (vec != 0x800) 229 panic("INVALID ASSUMPTION: vec 0x%lx, not 0x800", vec); 230 s = splhigh(); 231 if (s != ALPHA_PSL_IPL_IO_HI) 232 panic("INVALID ASSUMPTION: IPL %d, not %d", s, 233 ALPHA_PSL_IPL_IO_HI); 234 splx(s); 235 #endif 236 237 do { 238 tc_syncbus(); 239 240 /* find out what interrupts/errors occurred */ 241 tcir = *(volatile uint32_t *)TC_3000_300_IR; 242 ioasicir = *(volatile uint32_t *) 243 (DEC_3000_300_IOASIC_ADDR + IOASIC_INTR); 244 ioasicimr = *(volatile uint32_t *) 245 (DEC_3000_300_IOASIC_ADDR + IOASIC_IMSK); 246 tc_mb(); 247 248 /* Ignore interrupts that aren't enabled out. */ 249 ioasicir &= ioasicimr; 250 251 /* clear the interrupts/errors we found. */ 252 *(volatile uint32_t *)TC_3000_300_IR = tcir; 253 /* XXX can't clear TC option slot interrupts here? */ 254 tc_wmb(); 255 256 ifound = 0; 257 258 #define INCRINTRCNT(slot) tc_3000_300_intr[slot].tci_evcnt.ev_count++ 259 260 #define CHECKINTR(slot, flag) \ 261 if (flag) { \ 262 ifound = 1; \ 263 INCRINTRCNT(slot); \ 264 (*tc_3000_300_intr[slot].tci_func) \ 265 (tc_3000_300_intr[slot].tci_arg); \ 266 } 267 /* Do them in order of priority; highest slot # first. */ 268 CHECKINTR(TC_3000_300_DEV_CXTURBO, 269 tcir & TC_3000_300_IR_CXTURBO); 270 CHECKINTR(TC_3000_300_DEV_IOASIC, 271 (tcir & TC_3000_300_IR_IOASIC) && 272 (ioasicir & ~(IOASIC_INTR_300_OPT1|IOASIC_INTR_300_OPT0))); 273 CHECKINTR(TC_3000_300_DEV_TCDS, tcir & TC_3000_300_IR_TCDS); 274 CHECKINTR(TC_3000_300_DEV_OPT1, 275 ioasicir & IOASIC_INTR_300_OPT1); 276 CHECKINTR(TC_3000_300_DEV_OPT0, 277 ioasicir & IOASIC_INTR_300_OPT0); 278 #undef CHECKINTR 279 280 #ifdef DIAGNOSTIC 281 #define PRINTINTR(msg, bits) \ 282 if (tcir & bits) \ 283 printf(msg); 284 PRINTINTR("BCache tag parity error\n", 285 TC_3000_300_IR_BCTAGPARITY); 286 PRINTINTR("TC overrun error\n", TC_3000_300_IR_TCOVERRUN); 287 PRINTINTR("TC I/O timeout\n", TC_3000_300_IR_TCTIMEOUT); 288 PRINTINTR("Bcache parity error\n", 289 TC_3000_300_IR_BCACHEPARITY); 290 PRINTINTR("Memory parity error\n", TC_3000_300_IR_MEMPARITY); 291 #undef PRINTINTR 292 #endif 293 } while (ifound); 294 295 KERNEL_UNLOCK_ONE(NULL); 296 } 297 298 #if NWSDISPLAY > 0 299 /* 300 * tc_3000_300_fb_cnattach -- 301 * Attempt to map the CTB output device to a slot and attach the 302 * framebuffer as the output side of the console. 303 */ 304 int 305 tc_3000_300_fb_cnattach(uint64_t turbo_slot) 306 { 307 uint32_t output_slot; 308 309 output_slot = turbo_slot & 0xffffffff; 310 311 if (output_slot >= tc_3000_300_nslots) { 312 return EINVAL; 313 } 314 315 if (output_slot == 0) { 316 #if NSFB > 0 317 sfb_cnattach(KV(0x1c0000000) + 0x02000000); 318 return 0; 319 #else 320 return ENXIO; 321 #endif 322 } 323 324 return tc_fb_cnattach(tc_3000_300_slots[output_slot-1].tcs_addr); 325 } 326 #endif /* NWSDISPLAY */ 327
Indexes created Thu Oct 02 14:10:14 GMT 2025