tc_3000_300.c revision 1.7
1 /* $NetBSD: tc_3000_300.c,v 1.7 1996/05/01 23:19:50 cgd Exp $ */ 2 3 /* 4 * Copyright (c) 1994, 1995, 1996 Carnegie-Mellon University. 5 * All rights reserved. 6 * 7 * Author: Chris G. Demetriou 8 * 9 * Permission to use, copy, modify and distribute this software and 10 * its documentation is hereby granted, provided that both the copyright 11 * notice and this permission notice appear in all copies of the 12 * software, derivative works or modified versions, and any portions 13 * thereof, and that both notices appear in supporting documentation. 14 * 15 * CARNEGIE MELLON ALLOWS FREE USE OF THIS SOFTWARE IN ITS "AS IS" 16 * CONDITION. CARNEGIE MELLON DISCLAIMS ANY LIABILITY OF ANY KIND 17 * FOR ANY DAMAGES WHATSOEVER RESULTING FROM THE USE OF THIS SOFTWARE. 18 * 19 * Carnegie Mellon requests users of this software to return to 20 * 21 * Software Distribution Coordinator or Software.Distribution (at) CS.CMU.EDU 22 * School of Computer Science 23 * Carnegie Mellon University 24 * Pittsburgh PA 15213-3890 25 * 26 * any improvements or extensions that they make and grant Carnegie the 27 * rights to redistribute these changes. 28 */ 29 30 #include <sys/param.h> 31 #include <sys/device.h> 32 33 #include <machine/autoconf.h> 34 #include <machine/pte.h> 35 36 #include <dev/tc/tcvar.h> 37 #include <alpha/tc/tc_conf.h> 38 #include <alpha/tc/tc_3000_300.h> 39 #include <alpha/tc/ioasicreg.h> 40 41 void tc_3000_300_intr_setup __P((void)); 42 void tc_3000_300_intr_establish __P((struct device *, void *, 43 tc_intrlevel_t, int (*)(void *), void *)); 44 void tc_3000_300_intr_disestablish __P((struct device *, void *)); 45 void tc_3000_300_iointr __P((void *, int)); 46 47 int tc_3000_300_intrnull __P((void *)); 48 49 #define C(x) ((void *)(u_long)x) 50 #define KV(x) (phystok0seg(x)) 51 52 /* 53 * We have to read and modify the IOASIC registers directly, because 54 * the TC option slot interrupt request and mask bits are stored there, 55 * and the ioasic code isn't initted when we need to frob some interrupt 56 * bits. 57 */ 58 #define DEC_3000_300_IOASIC_ADDR KV(0x1a0000000) 59 60 struct tc_slotdesc tc_3000_300_slots[] = { 61 { KV(0x100000000), C(TC_3000_300_DEV_OPT0), }, /* 0 - opt slot 0 */ 62 { KV(0x120000000), C(TC_3000_300_DEV_OPT1), }, /* 1 - opt slot 1 */ 63 { KV(0x180000000), C(TC_3000_300_DEV_BOGUS), }, /* 2 - TCDS ASIC */ 64 { KV(0x1a0000000), C(TC_3000_300_DEV_BOGUS), }, /* 3 - IOCTL ASIC */ 65 { KV(0x1c0000000), C(TC_3000_300_DEV_CXTURBO), }, /* 4 - CXTurbo */ 66 }; 67 int tc_3000_300_nslots = 68 sizeof(tc_3000_300_slots) / sizeof(tc_3000_300_slots[0]); 69 70 struct tc_builtin tc_3000_300_builtins[] = { 71 { "PMAGB-BA", 4, 0x02000000, C(TC_3000_300_DEV_CXTURBO), }, 72 { "FLAMG-IO", 3, 0x00000000, C(TC_3000_300_DEV_IOASIC), }, 73 { "PMAZ-DS ", 2, 0x00000000, C(TC_3000_300_DEV_TCDS), }, 74 }; 75 int tc_3000_300_nbuiltins = 76 sizeof(tc_3000_300_builtins) / sizeof(tc_3000_300_builtins[0]); 77 78 struct tcintr { 79 int (*tci_func) __P((void *)); 80 void *tci_arg; 81 } tc_3000_300_intr[TC_3000_300_NCOOKIES]; 82 83 void 84 tc_3000_300_intr_setup() 85 { 86 volatile u_int32_t *imskp; 87 u_long i; 88 89 /* 90 * Disable all interrupts that we can (can't disable builtins). 91 */ 92 imskp = (volatile u_int32_t *)IOASIC_REG_IMSK(DEC_3000_300_IOASIC_ADDR); 93 *imskp &= ~(IOASIC_INTR_300_OPT0 | IOASIC_INTR_300_OPT1); 94 95 /* 96 * Set up interrupt handlers. 97 */ 98 for (i = 0; i < TC_3000_300_NCOOKIES; i++) { 99 tc_3000_300_intr[i].tci_func = tc_3000_300_intrnull; 100 tc_3000_300_intr[i].tci_arg = (void *)i; 101 } 102 } 103 104 void 105 tc_3000_300_intr_establish(tcadev, cookie, level, func, arg) 106 struct device *tcadev; 107 void *cookie, *arg; 108 tc_intrlevel_t level; 109 int (*func) __P((void *)); 110 { 111 volatile u_int32_t *imskp; 112 u_long dev = (u_long)cookie; 113 114 #ifdef DIAGNOSTIC 115 /* XXX bounds-check cookie. */ 116 #endif 117 118 if (tc_3000_300_intr[dev].tci_func != tc_3000_300_intrnull) 119 panic("tc_3000_300_intr_establish: cookie %d twice", dev); 120 121 tc_3000_300_intr[dev].tci_func = func; 122 tc_3000_300_intr[dev].tci_arg = arg; 123 124 imskp = (volatile u_int32_t *)IOASIC_REG_IMSK(DEC_3000_300_IOASIC_ADDR); 125 switch (dev) { 126 case TC_3000_300_DEV_OPT0: 127 *imskp |= IOASIC_INTR_300_OPT0; 128 break; 129 case TC_3000_300_DEV_OPT1: 130 *imskp |= IOASIC_INTR_300_OPT1; 131 break; 132 default: 133 /* interrupts for builtins always enabled */ 134 break; 135 } 136 } 137 138 void 139 tc_3000_300_intr_disestablish(tcadev, cookie) 140 struct device *tcadev; 141 void *cookie; 142 { 143 volatile u_int32_t *imskp; 144 u_long dev = (u_long)cookie; 145 146 #ifdef DIAGNOSTIC 147 /* XXX bounds-check cookie. */ 148 #endif 149 150 if (tc_3000_300_intr[dev].tci_func == tc_3000_300_intrnull) 151 panic("tc_3000_300_intr_disestablish: cookie %d bad intr", 152 dev); 153 154 imskp = (volatile u_int32_t *)IOASIC_REG_IMSK(DEC_3000_300_IOASIC_ADDR); 155 switch (dev) { 156 case TC_3000_300_DEV_OPT0: 157 *imskp &= ~IOASIC_INTR_300_OPT0; 158 break; 159 case TC_3000_300_DEV_OPT1: 160 *imskp &= ~IOASIC_INTR_300_OPT1; 161 break; 162 default: 163 /* interrupts for builtins always enabled */ 164 break; 165 } 166 167 tc_3000_300_intr[dev].tci_func = tc_3000_300_intrnull; 168 tc_3000_300_intr[dev].tci_arg = (void *)dev; 169 } 170 171 int 172 tc_3000_300_intrnull(val) 173 void *val; 174 { 175 176 panic("tc_3000_300_intrnull: uncaught TC intr for cookie %ld\n", 177 (u_long)val); 178 } 179 180 void 181 tc_3000_300_iointr(framep, vec) 182 void *framep; 183 int vec; 184 { 185 u_int32_t tcir, ioasicir, ioasicimr; 186 int opt0intr, opt1intr, ifound; 187 188 #ifdef DIAGNOSTIC 189 int s; 190 if (vec != 0x800) 191 panic("INVALID ASSUMPTION: vec %x, not 0x800", vec); 192 s = splhigh(); 193 if (s != PSL_IPL_IO) 194 panic("INVALID ASSUMPTION: IPL %d, not %d", s, PSL_IPL_IO); 195 splx(s); 196 #endif 197 198 do { 199 tc_syncbus(); 200 201 /* find out what interrupts/errors occurred */ 202 tcir = *(volatile u_int32_t *)TC_3000_300_IR; 203 ioasicir = *(volatile u_int32_t *) 204 IOASIC_REG_INTR(DEC_3000_300_IOASIC_ADDR); 205 ioasicimr = *(volatile u_int32_t *) 206 IOASIC_REG_IMSK(DEC_3000_300_IOASIC_ADDR); 207 tc_mb(); 208 209 /* Ignore interrupts that aren't enabled out. */ 210 ioasicir &= ioasicimr; 211 212 /* clear the interrupts/errors we found. */ 213 *(volatile u_int32_t *)TC_3000_300_IR = tcir; 214 /* XXX can't clear TC option slot interrupts here? */ 215 tc_wmb(); 216 217 ifound = 0; 218 #define CHECKINTR(slot, flag) \ 219 if (flag) { \ 220 ifound = 1; \ 221 (*tc_3000_300_intr[slot].tci_func) \ 222 (tc_3000_300_intr[slot].tci_arg); \ 223 } 224 /* Do them in order of priority; highest slot # first. */ 225 CHECKINTR(TC_3000_300_DEV_CXTURBO, 226 tcir & TC_3000_300_IR_CXTURBO); 227 CHECKINTR(TC_3000_300_DEV_IOASIC, tcir & TC_3000_300_IR_IOASIC); 228 CHECKINTR(TC_3000_300_DEV_TCDS, tcir & TC_3000_300_IR_TCDS); 229 CHECKINTR(TC_3000_300_DEV_OPT1, 230 ioasicir & IOASIC_INTR_300_OPT1); 231 CHECKINTR(TC_3000_300_DEV_OPT0, 232 ioasicir & IOASIC_INTR_300_OPT0); 233 #undef CHECKINTR 234 235 #ifdef DIAGNOSTIC 236 #define PRINTINTR(msg, bits) \ 237 if (tcir & bits) \ 238 printf(msg); 239 PRINTINTR("BCache tag parity error\n", 240 TC_3000_300_IR_BCTAGPARITY); 241 PRINTINTR("TC overrun error\n", TC_3000_300_IR_TCOVERRUN); 242 PRINTINTR("TC I/O timeout\n", TC_3000_300_IR_TCTIMEOUT); 243 PRINTINTR("Bcache parity error\n", 244 TC_3000_300_IR_BCACHEPARITY); 245 PRINTINTR("Memory parity error\n", TC_3000_300_IR_MEMPARITY); 246 #undef PRINTINTR 247 #endif 248 } while (ifound); 249 } 250
Indexes created Thu Oct 02 14:10:14 GMT 2025