tc_3000_300.c revision 1.8
1 /* $NetBSD: tc_3000_300.c,v 1.8 1996/06/05 00:30:53 cgd Exp $ */ 2 3 /* 4 * Copyright (c) 1994, 1995, 1996 Carnegie-Mellon University. 5 * All rights reserved. 6 * 7 * Author: Chris G. Demetriou 8 * 9 * Permission to use, copy, modify and distribute this software and 10 * its documentation is hereby granted, provided that both the copyright 11 * notice and this permission notice appear in all copies of the 12 * software, derivative works or modified versions, and any portions 13 * thereof, and that both notices appear in supporting documentation. 14 * 15 * CARNEGIE MELLON ALLOWS FREE USE OF THIS SOFTWARE IN ITS "AS IS" 16 * CONDITION. CARNEGIE MELLON DISCLAIMS ANY LIABILITY OF ANY KIND 17 * FOR ANY DAMAGES WHATSOEVER RESULTING FROM THE USE OF THIS SOFTWARE. 18 * 19 * Carnegie Mellon requests users of this software to return to 20 * 21 * Software Distribution Coordinator or Software.Distribution (at) CS.CMU.EDU 22 * School of Computer Science 23 * Carnegie Mellon University 24 * Pittsburgh PA 15213-3890 25 * 26 * any improvements or extensions that they make and grant Carnegie the 27 * rights to redistribute these changes. 28 */ 29 30 #include <sys/param.h> 31 #include <sys/device.h> 32 33 #include <machine/autoconf.h> 34 #include <machine/pte.h> 35 #ifndef EVCNT_COUNTERS 36 #include <machine/intrcnt.h> 37 #endif 38 39 #include <dev/tc/tcvar.h> 40 #include <alpha/tc/tc_conf.h> 41 #include <alpha/tc/tc_3000_300.h> 42 #include <alpha/tc/ioasicreg.h> 43 44 void tc_3000_300_intr_setup __P((void)); 45 void tc_3000_300_intr_establish __P((struct device *, void *, 46 tc_intrlevel_t, int (*)(void *), void *)); 47 void tc_3000_300_intr_disestablish __P((struct device *, void *)); 48 void tc_3000_300_iointr __P((void *, int)); 49 50 int tc_3000_300_intrnull __P((void *)); 51 52 #define C(x) ((void *)(u_long)x) 53 #define KV(x) (phystok0seg(x)) 54 55 /* 56 * We have to read and modify the IOASIC registers directly, because 57 * the TC option slot interrupt request and mask bits are stored there, 58 * and the ioasic code isn't initted when we need to frob some interrupt 59 * bits. 60 */ 61 #define DEC_3000_300_IOASIC_ADDR KV(0x1a0000000) 62 63 struct tc_slotdesc tc_3000_300_slots[] = { 64 { KV(0x100000000), C(TC_3000_300_DEV_OPT0), }, /* 0 - opt slot 0 */ 65 { KV(0x120000000), C(TC_3000_300_DEV_OPT1), }, /* 1 - opt slot 1 */ 66 { KV(0x180000000), C(TC_3000_300_DEV_BOGUS), }, /* 2 - TCDS ASIC */ 67 { KV(0x1a0000000), C(TC_3000_300_DEV_BOGUS), }, /* 3 - IOCTL ASIC */ 68 { KV(0x1c0000000), C(TC_3000_300_DEV_CXTURBO), }, /* 4 - CXTurbo */ 69 }; 70 int tc_3000_300_nslots = 71 sizeof(tc_3000_300_slots) / sizeof(tc_3000_300_slots[0]); 72 73 struct tc_builtin tc_3000_300_builtins[] = { 74 { "PMAGB-BA", 4, 0x02000000, C(TC_3000_300_DEV_CXTURBO), }, 75 { "FLAMG-IO", 3, 0x00000000, C(TC_3000_300_DEV_IOASIC), }, 76 { "PMAZ-DS ", 2, 0x00000000, C(TC_3000_300_DEV_TCDS), }, 77 }; 78 int tc_3000_300_nbuiltins = 79 sizeof(tc_3000_300_builtins) / sizeof(tc_3000_300_builtins[0]); 80 81 struct tcintr { 82 int (*tci_func) __P((void *)); 83 void *tci_arg; 84 } tc_3000_300_intr[TC_3000_300_NCOOKIES]; 85 86 void 87 tc_3000_300_intr_setup() 88 { 89 volatile u_int32_t *imskp; 90 u_long i; 91 92 /* 93 * Disable all interrupts that we can (can't disable builtins). 94 */ 95 imskp = (volatile u_int32_t *)IOASIC_REG_IMSK(DEC_3000_300_IOASIC_ADDR); 96 *imskp &= ~(IOASIC_INTR_300_OPT0 | IOASIC_INTR_300_OPT1); 97 98 /* 99 * Set up interrupt handlers. 100 */ 101 for (i = 0; i < TC_3000_300_NCOOKIES; i++) { 102 tc_3000_300_intr[i].tci_func = tc_3000_300_intrnull; 103 tc_3000_300_intr[i].tci_arg = (void *)i; 104 } 105 } 106 107 void 108 tc_3000_300_intr_establish(tcadev, cookie, level, func, arg) 109 struct device *tcadev; 110 void *cookie, *arg; 111 tc_intrlevel_t level; 112 int (*func) __P((void *)); 113 { 114 volatile u_int32_t *imskp; 115 u_long dev = (u_long)cookie; 116 117 #ifdef DIAGNOSTIC 118 /* XXX bounds-check cookie. */ 119 #endif 120 121 if (tc_3000_300_intr[dev].tci_func != tc_3000_300_intrnull) 122 panic("tc_3000_300_intr_establish: cookie %d twice", dev); 123 124 tc_3000_300_intr[dev].tci_func = func; 125 tc_3000_300_intr[dev].tci_arg = arg; 126 127 imskp = (volatile u_int32_t *)IOASIC_REG_IMSK(DEC_3000_300_IOASIC_ADDR); 128 switch (dev) { 129 case TC_3000_300_DEV_OPT0: 130 *imskp |= IOASIC_INTR_300_OPT0; 131 break; 132 case TC_3000_300_DEV_OPT1: 133 *imskp |= IOASIC_INTR_300_OPT1; 134 break; 135 default: 136 /* interrupts for builtins always enabled */ 137 break; 138 } 139 } 140 141 void 142 tc_3000_300_intr_disestablish(tcadev, cookie) 143 struct device *tcadev; 144 void *cookie; 145 { 146 volatile u_int32_t *imskp; 147 u_long dev = (u_long)cookie; 148 149 #ifdef DIAGNOSTIC 150 /* XXX bounds-check cookie. */ 151 #endif 152 153 if (tc_3000_300_intr[dev].tci_func == tc_3000_300_intrnull) 154 panic("tc_3000_300_intr_disestablish: cookie %d bad intr", 155 dev); 156 157 imskp = (volatile u_int32_t *)IOASIC_REG_IMSK(DEC_3000_300_IOASIC_ADDR); 158 switch (dev) { 159 case TC_3000_300_DEV_OPT0: 160 *imskp &= ~IOASIC_INTR_300_OPT0; 161 break; 162 case TC_3000_300_DEV_OPT1: 163 *imskp &= ~IOASIC_INTR_300_OPT1; 164 break; 165 default: 166 /* interrupts for builtins always enabled */ 167 break; 168 } 169 170 tc_3000_300_intr[dev].tci_func = tc_3000_300_intrnull; 171 tc_3000_300_intr[dev].tci_arg = (void *)dev; 172 } 173 174 int 175 tc_3000_300_intrnull(val) 176 void *val; 177 { 178 179 panic("tc_3000_300_intrnull: uncaught TC intr for cookie %ld\n", 180 (u_long)val); 181 } 182 183 void 184 tc_3000_300_iointr(framep, vec) 185 void *framep; 186 int vec; 187 { 188 u_int32_t tcir, ioasicir, ioasicimr; 189 int opt0intr, opt1intr, ifound; 190 191 #ifdef DIAGNOSTIC 192 int s; 193 if (vec != 0x800) 194 panic("INVALID ASSUMPTION: vec %x, not 0x800", vec); 195 s = splhigh(); 196 if (s != PSL_IPL_IO) 197 panic("INVALID ASSUMPTION: IPL %d, not %d", s, PSL_IPL_IO); 198 splx(s); 199 #endif 200 201 do { 202 tc_syncbus(); 203 204 /* find out what interrupts/errors occurred */ 205 tcir = *(volatile u_int32_t *)TC_3000_300_IR; 206 ioasicir = *(volatile u_int32_t *) 207 IOASIC_REG_INTR(DEC_3000_300_IOASIC_ADDR); 208 ioasicimr = *(volatile u_int32_t *) 209 IOASIC_REG_IMSK(DEC_3000_300_IOASIC_ADDR); 210 tc_mb(); 211 212 /* Ignore interrupts that aren't enabled out. */ 213 ioasicir &= ioasicimr; 214 215 /* clear the interrupts/errors we found. */ 216 *(volatile u_int32_t *)TC_3000_300_IR = tcir; 217 /* XXX can't clear TC option slot interrupts here? */ 218 tc_wmb(); 219 220 ifound = 0; 221 222 #ifdef EVCNT_COUNTERS 223 /* No interrupt counting via evcnt counters */ 224 XXX BREAK HERE XXX 225 #else /* !EVCNT_COUNTERS */ 226 #define INCRINTRCNT(slot) intrcnt[INTRCNT_KN16 + slot]++ 227 #endif /* EVCNT_COUNTERS */ 228 229 #define CHECKINTR(slot, flag) \ 230 if (flag) { \ 231 ifound = 1; \ 232 INCRINTRCNT(slot); \ 233 (*tc_3000_300_intr[slot].tci_func) \ 234 (tc_3000_300_intr[slot].tci_arg); \ 235 } 236 /* Do them in order of priority; highest slot # first. */ 237 CHECKINTR(TC_3000_300_DEV_CXTURBO, 238 tcir & TC_3000_300_IR_CXTURBO); 239 CHECKINTR(TC_3000_300_DEV_IOASIC, 240 (tcir & TC_3000_300_IR_IOASIC) && 241 (ioasicir & ~(IOASIC_INTR_300_OPT1|IOASIC_INTR_300_OPT0))); 242 CHECKINTR(TC_3000_300_DEV_TCDS, tcir & TC_3000_300_IR_TCDS); 243 CHECKINTR(TC_3000_300_DEV_OPT1, 244 ioasicir & IOASIC_INTR_300_OPT1); 245 CHECKINTR(TC_3000_300_DEV_OPT0, 246 ioasicir & IOASIC_INTR_300_OPT0); 247 #undef CHECKINTR 248 249 #ifdef DIAGNOSTIC 250 #define PRINTINTR(msg, bits) \ 251 if (tcir & bits) \ 252 printf(msg); 253 PRINTINTR("BCache tag parity error\n", 254 TC_3000_300_IR_BCTAGPARITY); 255 PRINTINTR("TC overrun error\n", TC_3000_300_IR_TCOVERRUN); 256 PRINTINTR("TC I/O timeout\n", TC_3000_300_IR_TCTIMEOUT); 257 PRINTINTR("Bcache parity error\n", 258 TC_3000_300_IR_BCACHEPARITY); 259 PRINTINTR("Memory parity error\n", TC_3000_300_IR_MEMPARITY); 260 #undef PRINTINTR 261 #endif 262 } while (ifound); 263 } 264
Indexes created Thu Oct 02 14:10:14 GMT 2025