tc_3000_300.c revision 1.9
1 /* $NetBSD: tc_3000_300.c,v 1.9 1996/07/09 00:55:25 cgd Exp $ */ 2 3 /* 4 * Copyright (c) 1994, 1995, 1996 Carnegie-Mellon University. 5 * All rights reserved. 6 * 7 * Author: Chris G. Demetriou 8 * 9 * Permission to use, copy, modify and distribute this software and 10 * its documentation is hereby granted, provided that both the copyright 11 * notice and this permission notice appear in all copies of the 12 * software, derivative works or modified versions, and any portions 13 * thereof, and that both notices appear in supporting documentation. 14 * 15 * CARNEGIE MELLON ALLOWS FREE USE OF THIS SOFTWARE IN ITS "AS IS" 16 * CONDITION. CARNEGIE MELLON DISCLAIMS ANY LIABILITY OF ANY KIND 17 * FOR ANY DAMAGES WHATSOEVER RESULTING FROM THE USE OF THIS SOFTWARE. 18 * 19 * Carnegie Mellon requests users of this software to return to 20 * 21 * Software Distribution Coordinator or Software.Distribution (at) CS.CMU.EDU 22 * School of Computer Science 23 * Carnegie Mellon University 24 * Pittsburgh PA 15213-3890 25 * 26 * any improvements or extensions that they make and grant Carnegie the 27 * rights to redistribute these changes. 28 */ 29 30 #include <sys/param.h> 31 #include <sys/systm.h> 32 #include <sys/device.h> 33 34 #include <machine/autoconf.h> 35 #include <machine/pte.h> 36 #ifndef EVCNT_COUNTERS 37 #include <machine/intrcnt.h> 38 #endif 39 40 #include <dev/tc/tcvar.h> 41 #include <alpha/tc/tc_conf.h> 42 #include <alpha/tc/tc_3000_300.h> 43 #include <alpha/tc/ioasicreg.h> 44 45 void tc_3000_300_intr_setup __P((void)); 46 void tc_3000_300_intr_establish __P((struct device *, void *, 47 tc_intrlevel_t, int (*)(void *), void *)); 48 void tc_3000_300_intr_disestablish __P((struct device *, void *)); 49 void tc_3000_300_iointr __P((void *, int)); 50 51 int tc_3000_300_intrnull __P((void *)); 52 53 #define C(x) ((void *)(u_long)x) 54 #define KV(x) (ALPHA_PHYS_TO_K0SEG(x)) 55 56 /* 57 * We have to read and modify the IOASIC registers directly, because 58 * the TC option slot interrupt request and mask bits are stored there, 59 * and the ioasic code isn't initted when we need to frob some interrupt 60 * bits. 61 */ 62 #define DEC_3000_300_IOASIC_ADDR KV(0x1a0000000) 63 64 struct tc_slotdesc tc_3000_300_slots[] = { 65 { KV(0x100000000), C(TC_3000_300_DEV_OPT0), }, /* 0 - opt slot 0 */ 66 { KV(0x120000000), C(TC_3000_300_DEV_OPT1), }, /* 1 - opt slot 1 */ 67 { KV(0x180000000), C(TC_3000_300_DEV_BOGUS), }, /* 2 - TCDS ASIC */ 68 { KV(0x1a0000000), C(TC_3000_300_DEV_BOGUS), }, /* 3 - IOCTL ASIC */ 69 { KV(0x1c0000000), C(TC_3000_300_DEV_CXTURBO), }, /* 4 - CXTurbo */ 70 }; 71 int tc_3000_300_nslots = 72 sizeof(tc_3000_300_slots) / sizeof(tc_3000_300_slots[0]); 73 74 struct tc_builtin tc_3000_300_builtins[] = { 75 { "PMAGB-BA", 4, 0x02000000, C(TC_3000_300_DEV_CXTURBO), }, 76 { "FLAMG-IO", 3, 0x00000000, C(TC_3000_300_DEV_IOASIC), }, 77 { "PMAZ-DS ", 2, 0x00000000, C(TC_3000_300_DEV_TCDS), }, 78 }; 79 int tc_3000_300_nbuiltins = 80 sizeof(tc_3000_300_builtins) / sizeof(tc_3000_300_builtins[0]); 81 82 struct tcintr { 83 int (*tci_func) __P((void *)); 84 void *tci_arg; 85 } tc_3000_300_intr[TC_3000_300_NCOOKIES]; 86 87 void 88 tc_3000_300_intr_setup() 89 { 90 volatile u_int32_t *imskp; 91 u_long i; 92 93 /* 94 * Disable all interrupts that we can (can't disable builtins). 95 */ 96 imskp = (volatile u_int32_t *)IOASIC_REG_IMSK(DEC_3000_300_IOASIC_ADDR); 97 *imskp &= ~(IOASIC_INTR_300_OPT0 | IOASIC_INTR_300_OPT1); 98 99 /* 100 * Set up interrupt handlers. 101 */ 102 for (i = 0; i < TC_3000_300_NCOOKIES; i++) { 103 tc_3000_300_intr[i].tci_func = tc_3000_300_intrnull; 104 tc_3000_300_intr[i].tci_arg = (void *)i; 105 } 106 } 107 108 void 109 tc_3000_300_intr_establish(tcadev, cookie, level, func, arg) 110 struct device *tcadev; 111 void *cookie, *arg; 112 tc_intrlevel_t level; 113 int (*func) __P((void *)); 114 { 115 volatile u_int32_t *imskp; 116 u_long dev = (u_long)cookie; 117 118 #ifdef DIAGNOSTIC 119 /* XXX bounds-check cookie. */ 120 #endif 121 122 if (tc_3000_300_intr[dev].tci_func != tc_3000_300_intrnull) 123 panic("tc_3000_300_intr_establish: cookie %d twice", dev); 124 125 tc_3000_300_intr[dev].tci_func = func; 126 tc_3000_300_intr[dev].tci_arg = arg; 127 128 imskp = (volatile u_int32_t *)IOASIC_REG_IMSK(DEC_3000_300_IOASIC_ADDR); 129 switch (dev) { 130 case TC_3000_300_DEV_OPT0: 131 *imskp |= IOASIC_INTR_300_OPT0; 132 break; 133 case TC_3000_300_DEV_OPT1: 134 *imskp |= IOASIC_INTR_300_OPT1; 135 break; 136 default: 137 /* interrupts for builtins always enabled */ 138 break; 139 } 140 } 141 142 void 143 tc_3000_300_intr_disestablish(tcadev, cookie) 144 struct device *tcadev; 145 void *cookie; 146 { 147 volatile u_int32_t *imskp; 148 u_long dev = (u_long)cookie; 149 150 #ifdef DIAGNOSTIC 151 /* XXX bounds-check cookie. */ 152 #endif 153 154 if (tc_3000_300_intr[dev].tci_func == tc_3000_300_intrnull) 155 panic("tc_3000_300_intr_disestablish: cookie %d bad intr", 156 dev); 157 158 imskp = (volatile u_int32_t *)IOASIC_REG_IMSK(DEC_3000_300_IOASIC_ADDR); 159 switch (dev) { 160 case TC_3000_300_DEV_OPT0: 161 *imskp &= ~IOASIC_INTR_300_OPT0; 162 break; 163 case TC_3000_300_DEV_OPT1: 164 *imskp &= ~IOASIC_INTR_300_OPT1; 165 break; 166 default: 167 /* interrupts for builtins always enabled */ 168 break; 169 } 170 171 tc_3000_300_intr[dev].tci_func = tc_3000_300_intrnull; 172 tc_3000_300_intr[dev].tci_arg = (void *)dev; 173 } 174 175 int 176 tc_3000_300_intrnull(val) 177 void *val; 178 { 179 180 panic("tc_3000_300_intrnull: uncaught TC intr for cookie %ld\n", 181 (u_long)val); 182 } 183 184 void 185 tc_3000_300_iointr(framep, vec) 186 void *framep; 187 int vec; 188 { 189 u_int32_t tcir, ioasicir, ioasicimr; 190 int ifound; 191 192 #ifdef DIAGNOSTIC 193 int s; 194 if (vec != 0x800) 195 panic("INVALID ASSUMPTION: vec %x, not 0x800", vec); 196 s = splhigh(); 197 if (s != ALPHA_PSL_IPL_IO) 198 panic("INVALID ASSUMPTION: IPL %d, not %d", s, 199 ALPHA_PSL_IPL_IO); 200 splx(s); 201 #endif 202 203 do { 204 tc_syncbus(); 205 206 /* find out what interrupts/errors occurred */ 207 tcir = *(volatile u_int32_t *)TC_3000_300_IR; 208 ioasicir = *(volatile u_int32_t *) 209 IOASIC_REG_INTR(DEC_3000_300_IOASIC_ADDR); 210 ioasicimr = *(volatile u_int32_t *) 211 IOASIC_REG_IMSK(DEC_3000_300_IOASIC_ADDR); 212 tc_mb(); 213 214 /* Ignore interrupts that aren't enabled out. */ 215 ioasicir &= ioasicimr; 216 217 /* clear the interrupts/errors we found. */ 218 *(volatile u_int32_t *)TC_3000_300_IR = tcir; 219 /* XXX can't clear TC option slot interrupts here? */ 220 tc_wmb(); 221 222 ifound = 0; 223 224 #ifdef EVCNT_COUNTERS 225 /* No interrupt counting via evcnt counters */ 226 XXX BREAK HERE XXX 227 #else /* !EVCNT_COUNTERS */ 228 #define INCRINTRCNT(slot) intrcnt[INTRCNT_KN16 + slot]++ 229 #endif /* EVCNT_COUNTERS */ 230 231 #define CHECKINTR(slot, flag) \ 232 if (flag) { \ 233 ifound = 1; \ 234 INCRINTRCNT(slot); \ 235 (*tc_3000_300_intr[slot].tci_func) \ 236 (tc_3000_300_intr[slot].tci_arg); \ 237 } 238 /* Do them in order of priority; highest slot # first. */ 239 CHECKINTR(TC_3000_300_DEV_CXTURBO, 240 tcir & TC_3000_300_IR_CXTURBO); 241 CHECKINTR(TC_3000_300_DEV_IOASIC, 242 (tcir & TC_3000_300_IR_IOASIC) && 243 (ioasicir & ~(IOASIC_INTR_300_OPT1|IOASIC_INTR_300_OPT0))); 244 CHECKINTR(TC_3000_300_DEV_TCDS, tcir & TC_3000_300_IR_TCDS); 245 CHECKINTR(TC_3000_300_DEV_OPT1, 246 ioasicir & IOASIC_INTR_300_OPT1); 247 CHECKINTR(TC_3000_300_DEV_OPT0, 248 ioasicir & IOASIC_INTR_300_OPT0); 249 #undef CHECKINTR 250 251 #ifdef DIAGNOSTIC 252 #define PRINTINTR(msg, bits) \ 253 if (tcir & bits) \ 254 printf(msg); 255 PRINTINTR("BCache tag parity error\n", 256 TC_3000_300_IR_BCTAGPARITY); 257 PRINTINTR("TC overrun error\n", TC_3000_300_IR_TCOVERRUN); 258 PRINTINTR("TC I/O timeout\n", TC_3000_300_IR_TCTIMEOUT); 259 PRINTINTR("Bcache parity error\n", 260 TC_3000_300_IR_BCACHEPARITY); 261 PRINTINTR("Memory parity error\n", TC_3000_300_IR_MEMPARITY); 262 #undef PRINTINTR 263 #endif 264 } while (ifound); 265 } 266
Indexes created Thu Oct 02 14:10:14 GMT 2025