tc_3000_500.c revision 1.1 1 1.1 cgd /* $NetBSD: tc_3000_500.c,v 1.1 1995/02/13 23:09:08 cgd Exp $ */
2 1.1 cgd
3 1.1 cgd /*
4 1.1 cgd * Copyright (c) 1994, 1995 Carnegie-Mellon University.
5 1.1 cgd * All rights reserved.
6 1.1 cgd *
7 1.1 cgd * Author: Chris G. Demetriou
8 1.1 cgd *
9 1.1 cgd * Permission to use, copy, modify and distribute this software and
10 1.1 cgd * its documentation is hereby granted, provided that both the copyright
11 1.1 cgd * notice and this permission notice appear in all copies of the
12 1.1 cgd * software, derivative works or modified versions, and any portions
13 1.1 cgd * thereof, and that both notices appear in supporting documentation.
14 1.1 cgd *
15 1.1 cgd * CARNEGIE MELLON ALLOWS FREE USE OF THIS SOFTWARE IN ITS "AS IS"
16 1.1 cgd * CONDITION. CARNEGIE MELLON DISCLAIMS ANY LIABILITY OF ANY KIND
17 1.1 cgd * FOR ANY DAMAGES WHATSOEVER RESULTING FROM THE USE OF THIS SOFTWARE.
18 1.1 cgd *
19 1.1 cgd * Carnegie Mellon requests users of this software to return to
20 1.1 cgd *
21 1.1 cgd * Software Distribution Coordinator or Software.Distribution (at) CS.CMU.EDU
22 1.1 cgd * School of Computer Science
23 1.1 cgd * Carnegie Mellon University
24 1.1 cgd * Pittsburgh PA 15213-3890
25 1.1 cgd *
26 1.1 cgd * any improvements or extensions that they make and grant Carnegie the
27 1.1 cgd * rights to redistribute these changes.
28 1.1 cgd */
29 1.1 cgd
30 1.1 cgd #include <sys/param.h>
31 1.1 cgd #include <sys/device.h>
32 1.1 cgd
33 1.1 cgd #include <machine/autoconf.h>
34 1.1 cgd #include <machine/pte.h>
35 1.1 cgd
36 1.1 cgd #include <alpha/tc/tc.h>
37 1.1 cgd #include <alpha/tc/tc_3000_500.h>
38 1.1 cgd
39 1.1 cgd /* XXX ESTABLISH, DISESTABLISH */
40 1.1 cgd void tc_3000_500_intr_setup __P((void));
41 1.1 cgd void tc_3000_500_intr_establish
42 1.1 cgd __P((struct confargs *, intr_handler_t, void *));
43 1.1 cgd void tc_3000_500_intr_disestablish __P((struct confargs *));
44 1.1 cgd void tc_3000_500_iointr __P((void *, int));
45 1.1 cgd int tc_3000_500_getdev __P((struct confargs *));
46 1.1 cgd
47 1.1 cgd #define KV(x) ((caddr_t)phystok0seg(x))
48 1.1 cgd #define TC_3000_500_NSLOTS 8
49 1.1 cgd #define TC_3000_500_MAXDEVS 9
50 1.1 cgd
51 1.1 cgd static struct tc_slot_desc dec_3000_500_slots[TC_3000_500_NSLOTS] = {
52 1.1 cgd { KV(0x100000000), }, /* slot 0 - TC option slot 0 */
53 1.1 cgd { KV(0x120000000), }, /* slot 1 - TC option slot 1 */
54 1.1 cgd { KV(0x140000000), }, /* slot 2 - TC option slot 2 */
55 1.1 cgd { KV(0x160000000), }, /* slot 3 - TC option slot 3 */
56 1.1 cgd { KV(0x180000000), }, /* slot 4 - TC option slot 4 */
57 1.1 cgd { KV(0x1a0000000), }, /* slot 5 - TC option slot 5 */
58 1.1 cgd { KV(0x1c0000000), }, /* slot 6 - TCDS ASIC on cpu board */
59 1.1 cgd { KV(0x1e0000000), }, /* slot 7 - IOCTL ASIC on cpu board */
60 1.1 cgd };
61 1.1 cgd
62 1.1 cgd static struct confargs dec_3000_500_devs[TC_3000_500_MAXDEVS] = {
63 1.1 cgd { "IOCTL ", 7, 0x00000000, },
64 1.1 cgd { "PMAGB-BA", 7, 0x02000000, },
65 1.1 cgd { "PMAZ-DS ", 6, 0x00000000, },
66 1.1 cgd { NULL, 5, 0x0, },
67 1.1 cgd { NULL, 4, 0x0, },
68 1.1 cgd { NULL, 3, 0x0, },
69 1.1 cgd { NULL, 2, 0x0, },
70 1.1 cgd { NULL, 1, 0x0, },
71 1.1 cgd { NULL, 0, 0x0, },
72 1.1 cgd };
73 1.1 cgd
74 1.1 cgd /* Indices into the struct confargs array. */
75 1.1 cgd #define TC_3000_500_DEV_IOCTL 0
76 1.1 cgd #define TC_3000_500_DEV_CXTURBO 1
77 1.1 cgd #define TC_3000_500_DEV_TCDS 2
78 1.1 cgd #define TC_3000_500_DEV_OPT5 3
79 1.1 cgd #define TC_3000_500_DEV_OPT4 4
80 1.1 cgd #define TC_3000_500_DEV_OPT3 5
81 1.1 cgd #define TC_3000_500_DEV_OPT2 6
82 1.1 cgd #define TC_3000_500_DEV_OPT1 7
83 1.1 cgd #define TC_3000_500_DEV_OPT0 8
84 1.1 cgd
85 1.1 cgd struct tc_cpu_desc dec_3000_500_cpu = {
86 1.1 cgd dec_3000_500_slots, TC_3000_500_NSLOTS,
87 1.1 cgd dec_3000_500_devs, TC_3000_500_MAXDEVS,
88 1.1 cgd tc_3000_500_intr_setup,
89 1.1 cgd tc_3000_500_intr_establish,
90 1.1 cgd tc_3000_500_intr_disestablish,
91 1.1 cgd tc_3000_500_iointr,
92 1.1 cgd };
93 1.1 cgd
94 1.1 cgd intr_handler_t tc_3000_500_intrhand[TC_3000_500_MAXDEVS];
95 1.1 cgd void *tc_3000_500_intrval[TC_3000_500_MAXDEVS];
96 1.1 cgd
97 1.1 cgd void
98 1.1 cgd tc_3000_500_intr_setup()
99 1.1 cgd {
100 1.1 cgd int i;
101 1.1 cgd
102 1.1 cgd /* Set up interrupt handlers. */
103 1.1 cgd for (i = 0; i < TC_3000_500_MAXDEVS; i++) {
104 1.1 cgd tc_3000_500_intrhand[i] = tc_intrnull;
105 1.1 cgd tc_3000_500_intrval[i] = (void *)(long)i;
106 1.1 cgd }
107 1.1 cgd
108 1.1 cgd /*
109 1.1 cgd * XXX
110 1.1 cgd * The System Programmer's Manual (3-15) says IMR entries for option
111 1.1 cgd * slots are initialized to 0. I think this is wrong, and that they
112 1.1 cgd * are initialized to 1, i.e. the option slots are disabled. Enable
113 1.1 cgd * them.
114 1.1 cgd *
115 1.1 cgd * XXX
116 1.1 cgd * The MACH code appears to enable them by setting them to 1. !?!?!
117 1.1 cgd */
118 1.1 cgd *(volatile u_int32_t *)TC_3000_500_IMR_WRITE = 0;
119 1.1 cgd MB();
120 1.1 cgd }
121 1.1 cgd
122 1.1 cgd void
123 1.1 cgd tc_3000_500_intr_establish(ca, handler, val)
124 1.1 cgd struct confargs *ca;
125 1.1 cgd int (*handler) __P((void *));
126 1.1 cgd void *val;
127 1.1 cgd {
128 1.1 cgd int dev = tc_3000_500_getdev(ca);
129 1.1 cgd
130 1.1 cgd #ifdef DIAGNOSTIC
131 1.1 cgd if (dev == -1)
132 1.1 cgd panic("tc_3000_500_intr_establish: dev == -1");
133 1.1 cgd #endif
134 1.1 cgd
135 1.1 cgd if (tc_3000_500_intrhand[dev] != tc_intrnull)
136 1.1 cgd panic("tc_3000_500_intr_establish: dev %d twice", dev);
137 1.1 cgd
138 1.1 cgd tc_3000_500_intrhand[dev] = handler;
139 1.1 cgd tc_3000_500_intrval[dev] = val;
140 1.1 cgd
141 1.1 cgd /* XXX ENABLE INTERRUPT MASK FOR DEV */
142 1.1 cgd }
143 1.1 cgd
144 1.1 cgd void
145 1.1 cgd tc_3000_500_intr_disestablish(ca)
146 1.1 cgd struct confargs *ca;
147 1.1 cgd {
148 1.1 cgd int dev = tc_3000_500_getdev(ca);
149 1.1 cgd
150 1.1 cgd #ifdef DIAGNOSTIC
151 1.1 cgd if (dev == -1)
152 1.1 cgd panic("tc_3000_500_intr_disestablish: somebody goofed");
153 1.1 cgd #endif
154 1.1 cgd
155 1.1 cgd if (tc_3000_500_intrhand[dev] == tc_intrnull)
156 1.1 cgd panic("tc_3000_500_intr_disestablish: dev %d missing intr",
157 1.1 cgd dev);
158 1.1 cgd
159 1.1 cgd tc_3000_500_intrhand[dev] = tc_intrnull;
160 1.1 cgd tc_3000_500_intrval[dev] = (void *)(long)dev;
161 1.1 cgd
162 1.1 cgd /* XXX DISABLE INTERRUPT MASK FOR DEV */
163 1.1 cgd }
164 1.1 cgd
165 1.1 cgd void
166 1.1 cgd tc_3000_500_iointr(framep, vec)
167 1.1 cgd void *framep;
168 1.1 cgd int vec;
169 1.1 cgd {
170 1.1 cgd u_int32_t ir;
171 1.1 cgd int ifound;
172 1.1 cgd
173 1.1 cgd #ifdef DIAGNOSTIC
174 1.1 cgd int s;
175 1.1 cgd if (vec != 0x800)
176 1.1 cgd panic("INVALID ASSUMPTION: vec %x, not 0x800", vec);
177 1.1 cgd s = splhigh();
178 1.1 cgd if (s != PSL_IPL_IO)
179 1.1 cgd panic("INVALID ASSUMPTION: IPL %d, not %d", s, PSL_IPL_IO);
180 1.1 cgd splx(s);
181 1.1 cgd #endif
182 1.1 cgd
183 1.1 cgd do {
184 1.1 cgd MAGIC_READ;
185 1.1 cgd MB();
186 1.1 cgd ir = *(volatile u_int32_t *)TC_3000_500_IR_CLEAR;
187 1.1 cgd MB();
188 1.1 cgd
189 1.1 cgd ifound = 0;
190 1.1 cgd #define CHECKINTR(slot, bits) \
191 1.1 cgd if (ir & bits) { \
192 1.1 cgd ifound = 1; \
193 1.1 cgd (*tc_3000_500_intrhand[slot]) \
194 1.1 cgd (tc_3000_500_intrval[slot]); \
195 1.1 cgd }
196 1.1 cgd /* Do them in order of priority; highest slot # first. */
197 1.1 cgd CHECKINTR(TC_3000_500_DEV_CXTURBO, TC_3000_500_IR_CXTURBO);
198 1.1 cgd CHECKINTR(TC_3000_500_DEV_IOCTL, TC_3000_500_IR_IOCTL);
199 1.1 cgd CHECKINTR(TC_3000_500_DEV_TCDS, TC_3000_500_IR_TCDS);
200 1.1 cgd CHECKINTR(TC_3000_500_DEV_OPT5, TC_3000_500_IR_OPT5);
201 1.1 cgd CHECKINTR(TC_3000_500_DEV_OPT4, TC_3000_500_IR_OPT4);
202 1.1 cgd CHECKINTR(TC_3000_500_DEV_OPT3, TC_3000_500_IR_OPT3);
203 1.1 cgd CHECKINTR(TC_3000_500_DEV_OPT2, TC_3000_500_IR_OPT2);
204 1.1 cgd CHECKINTR(TC_3000_500_DEV_OPT1, TC_3000_500_IR_OPT1);
205 1.1 cgd CHECKINTR(TC_3000_500_DEV_OPT0, TC_3000_500_IR_OPT0);
206 1.1 cgd #undef CHECKINTR
207 1.1 cgd
208 1.1 cgd #ifdef DIAGNOSTIC
209 1.1 cgd #define PRINTINTR(msg, bits) \
210 1.1 cgd if (ir & bits) \
211 1.1 cgd printf(msg);
212 1.1 cgd PRINTINTR("Second error occurred\n", TC_3000_500_IR_ERR2);
213 1.1 cgd PRINTINTR("DMA buffer error\n", TC_3000_500_IR_DMABE);
214 1.1 cgd PRINTINTR("DMA cross 2K boundary\n", TC_3000_500_IR_DMA2K);
215 1.1 cgd PRINTINTR("TC reset in progress\n", TC_3000_500_IR_TCRESET);
216 1.1 cgd PRINTINTR("TC parity error\n", TC_3000_500_IR_TCPAR);
217 1.1 cgd PRINTINTR("DMA tag error\n", TC_3000_500_IR_DMATAG);
218 1.1 cgd PRINTINTR("Single-bit error\n", TC_3000_500_IR_DMASBE);
219 1.1 cgd PRINTINTR("Double-bit error\n", TC_3000_500_IR_DMADBE);
220 1.1 cgd PRINTINTR("TC I/O timeout\n", TC_3000_500_IR_TCTIMEOUT);
221 1.1 cgd PRINTINTR("DMA block too long\n", TC_3000_500_IR_DMABLOCK);
222 1.1 cgd PRINTINTR("Invalid I/O address\n", TC_3000_500_IR_IOADDR);
223 1.1 cgd PRINTINTR("DMA scatter/gather invalid\n", TC_3000_500_IR_DMASG);
224 1.1 cgd PRINTINTR("Scatter/gather parity error\n",
225 1.1 cgd TC_3000_500_IR_SGPAR);
226 1.1 cgd #undef PRINTINTR
227 1.1 cgd #endif
228 1.1 cgd } while (ifound);
229 1.1 cgd }
230 1.1 cgd
231 1.1 cgd int
232 1.1 cgd tc_3000_500_getdev(ca)
233 1.1 cgd struct confargs *ca;
234 1.1 cgd {
235 1.1 cgd int i;
236 1.1 cgd
237 1.1 cgd for (i = 0; i < TC_3000_500_MAXDEVS; i++)
238 1.1 cgd if (ca->ca_slot == dec_3000_500_devs[i].ca_slot &&
239 1.1 cgd ca->ca_offset == dec_3000_500_devs[i].ca_offset &&
240 1.1 cgd !strncmp(ca->ca_name, dec_3000_500_devs[i].ca_name))
241 1.1 cgd return (i);
242 1.1 cgd
243 1.1 cgd return (-1);
244 1.1 cgd }
245 1.1 cgd
246 1.1 cgd /*
247 1.1 cgd * tc_3000_500_ioslot --
248 1.1 cgd * Set the PBS bits for devices on the TC.
249 1.1 cgd */
250 1.1 cgd void
251 1.1 cgd tc_3000_500_ioslot(slot, flags, set)
252 1.1 cgd u_int32_t slot, flags;
253 1.1 cgd int set;
254 1.1 cgd {
255 1.1 cgd volatile u_int32_t *iosp;
256 1.1 cgd u_int32_t ios;
257 1.1 cgd int s;
258 1.1 cgd
259 1.1 cgd iosp = (volatile u_int32_t *)TC_3000_500_IOSLOT;
260 1.1 cgd ios = *iosp;
261 1.1 cgd flags <<= (slot * 3);
262 1.1 cgd if (set)
263 1.1 cgd ios |= flags;
264 1.1 cgd else
265 1.1 cgd ios &= ~flags;
266 1.1 cgd s = splhigh();
267 1.1 cgd *iosp = ios;
268 1.1 cgd MB();
269 1.1 cgd splx(s);
270 1.1 cgd }
271