tc_3000_500.c revision 1.13 1 1.13 cgd /* $NetBSD: tc_3000_500.c,v 1.13 1997/04/06 22:32:02 cgd Exp $ */
2 1.1 cgd
3 1.1 cgd /*
4 1.7 cgd * Copyright (c) 1994, 1995, 1996 Carnegie-Mellon University.
5 1.1 cgd * All rights reserved.
6 1.1 cgd *
7 1.1 cgd * Author: Chris G. Demetriou
8 1.1 cgd *
9 1.1 cgd * Permission to use, copy, modify and distribute this software and
10 1.1 cgd * its documentation is hereby granted, provided that both the copyright
11 1.1 cgd * notice and this permission notice appear in all copies of the
12 1.1 cgd * software, derivative works or modified versions, and any portions
13 1.1 cgd * thereof, and that both notices appear in supporting documentation.
14 1.1 cgd *
15 1.1 cgd * CARNEGIE MELLON ALLOWS FREE USE OF THIS SOFTWARE IN ITS "AS IS"
16 1.1 cgd * CONDITION. CARNEGIE MELLON DISCLAIMS ANY LIABILITY OF ANY KIND
17 1.1 cgd * FOR ANY DAMAGES WHATSOEVER RESULTING FROM THE USE OF THIS SOFTWARE.
18 1.1 cgd *
19 1.1 cgd * Carnegie Mellon requests users of this software to return to
20 1.1 cgd *
21 1.1 cgd * Software Distribution Coordinator or Software.Distribution (at) CS.CMU.EDU
22 1.1 cgd * School of Computer Science
23 1.1 cgd * Carnegie Mellon University
24 1.1 cgd * Pittsburgh PA 15213-3890
25 1.1 cgd *
26 1.1 cgd * any improvements or extensions that they make and grant Carnegie the
27 1.1 cgd * rights to redistribute these changes.
28 1.1 cgd */
29 1.13 cgd
30 1.13 cgd #include <machine/options.h> /* Pull in config options headers */
31 1.1 cgd
32 1.1 cgd #include <sys/param.h>
33 1.8 cgd #include <sys/systm.h>
34 1.1 cgd #include <sys/device.h>
35 1.1 cgd
36 1.1 cgd #include <machine/autoconf.h>
37 1.1 cgd #include <machine/pte.h>
38 1.6 cgd #ifndef EVCNT_COUNTERS
39 1.6 cgd #include <machine/intrcnt.h>
40 1.6 cgd #endif
41 1.1 cgd
42 1.3 cgd #include <dev/tc/tcvar.h>
43 1.3 cgd #include <alpha/tc/tc_conf.h>
44 1.1 cgd #include <alpha/tc/tc_3000_500.h>
45 1.1 cgd
46 1.1 cgd void tc_3000_500_intr_setup __P((void));
47 1.3 cgd void tc_3000_500_intr_establish __P((struct device *, void *,
48 1.3 cgd tc_intrlevel_t, int (*)(void *), void *));
49 1.3 cgd void tc_3000_500_intr_disestablish __P((struct device *, void *));
50 1.9 cgd void tc_3000_500_iointr __P((void *, unsigned long));
51 1.1 cgd
52 1.3 cgd int tc_3000_500_intrnull __P((void *));
53 1.3 cgd
54 1.3 cgd #define C(x) ((void *)(u_long)x)
55 1.8 cgd #define KV(x) (ALPHA_PHYS_TO_K0SEG(x))
56 1.3 cgd
57 1.3 cgd struct tc_slotdesc tc_3000_500_slots[] = {
58 1.3 cgd { KV(0x100000000), C(TC_3000_500_DEV_OPT0), }, /* 0 - opt slot 0 */
59 1.3 cgd { KV(0x120000000), C(TC_3000_500_DEV_OPT1), }, /* 1 - opt slot 1 */
60 1.3 cgd { KV(0x140000000), C(TC_3000_500_DEV_OPT2), }, /* 2 - opt slot 2 */
61 1.3 cgd { KV(0x160000000), C(TC_3000_500_DEV_OPT3), }, /* 3 - opt slot 3 */
62 1.3 cgd { KV(0x180000000), C(TC_3000_500_DEV_OPT4), }, /* 4 - opt slot 4 */
63 1.3 cgd { KV(0x1a0000000), C(TC_3000_500_DEV_OPT5), }, /* 5 - opt slot 5 */
64 1.3 cgd { KV(0x1c0000000), C(TC_3000_500_DEV_BOGUS), }, /* 6 - TCDS ASIC */
65 1.3 cgd { KV(0x1e0000000), C(TC_3000_500_DEV_BOGUS), }, /* 7 - IOCTL ASIC */
66 1.1 cgd };
67 1.3 cgd int tc_3000_500_nslots =
68 1.3 cgd sizeof(tc_3000_500_slots) / sizeof(tc_3000_500_slots[0]);
69 1.1 cgd
70 1.12 cgd struct tc_builtin tc_3000_500_graphics_builtins[] = {
71 1.3 cgd { "FLAMG-IO", 7, 0x00000000, C(TC_3000_500_DEV_IOASIC), },
72 1.3 cgd { "PMAGB-BA", 7, 0x02000000, C(TC_3000_500_DEV_CXTURBO), },
73 1.3 cgd { "PMAZ-DS ", 6, 0x00000000, C(TC_3000_500_DEV_TCDS), },
74 1.1 cgd };
75 1.12 cgd int tc_3000_500_graphics_nbuiltins = sizeof(tc_3000_500_graphics_builtins) /
76 1.12 cgd sizeof(tc_3000_500_graphics_builtins[0]);
77 1.12 cgd
78 1.12 cgd struct tc_builtin tc_3000_500_nographics_builtins[] = {
79 1.12 cgd { "FLAMG-IO", 7, 0x00000000, C(TC_3000_500_DEV_IOASIC), },
80 1.12 cgd { "PMAZ-DS ", 6, 0x00000000, C(TC_3000_500_DEV_TCDS), },
81 1.12 cgd };
82 1.12 cgd int tc_3000_500_nographics_nbuiltins = sizeof(tc_3000_500_nographics_builtins) /
83 1.12 cgd sizeof(tc_3000_500_nographics_builtins[0]);
84 1.1 cgd
85 1.3 cgd u_int32_t tc_3000_500_intrbits[TC_3000_500_NCOOKIES] = {
86 1.3 cgd TC_3000_500_IR_OPT0,
87 1.3 cgd TC_3000_500_IR_OPT1,
88 1.3 cgd TC_3000_500_IR_OPT2,
89 1.3 cgd TC_3000_500_IR_OPT3,
90 1.3 cgd TC_3000_500_IR_OPT4,
91 1.3 cgd TC_3000_500_IR_OPT5,
92 1.3 cgd TC_3000_500_IR_TCDS,
93 1.3 cgd TC_3000_500_IR_IOASIC,
94 1.3 cgd TC_3000_500_IR_CXTURBO,
95 1.1 cgd };
96 1.1 cgd
97 1.3 cgd struct tcintr {
98 1.3 cgd int (*tci_func) __P((void *));
99 1.3 cgd void *tci_arg;
100 1.3 cgd } tc_3000_500_intr[TC_3000_500_NCOOKIES];
101 1.1 cgd
102 1.5 cgd u_int32_t tc_3000_500_imask; /* intrs we want to ignore; mirrors IMR. */
103 1.5 cgd
104 1.1 cgd void
105 1.1 cgd tc_3000_500_intr_setup()
106 1.1 cgd {
107 1.3 cgd u_long i;
108 1.1 cgd
109 1.3 cgd /*
110 1.4 cgd * Disable all slot interrupts. Note that this cannot
111 1.4 cgd * actually disable CXTurbo, TCDS, and IOASIC interrupts.
112 1.3 cgd */
113 1.5 cgd tc_3000_500_imask = *(volatile u_int32_t *)TC_3000_500_IMR_READ;
114 1.3 cgd for (i = 0; i < TC_3000_500_NCOOKIES; i++)
115 1.5 cgd tc_3000_500_imask |= tc_3000_500_intrbits[i];
116 1.5 cgd *(volatile u_int32_t *)TC_3000_500_IMR_WRITE = tc_3000_500_imask;
117 1.3 cgd tc_mb();
118 1.1 cgd
119 1.3 cgd /*
120 1.3 cgd * Set up interrupt handlers.
121 1.1 cgd */
122 1.3 cgd for (i = 0; i < TC_3000_500_NCOOKIES; i++) {
123 1.3 cgd tc_3000_500_intr[i].tci_func = tc_3000_500_intrnull;
124 1.3 cgd tc_3000_500_intr[i].tci_arg = (void *)i;
125 1.3 cgd }
126 1.1 cgd }
127 1.1 cgd
128 1.1 cgd void
129 1.3 cgd tc_3000_500_intr_establish(tcadev, cookie, level, func, arg)
130 1.3 cgd struct device *tcadev;
131 1.3 cgd void *cookie, *arg;
132 1.3 cgd tc_intrlevel_t level;
133 1.3 cgd int (*func) __P((void *));
134 1.1 cgd {
135 1.3 cgd u_long dev = (u_long)cookie;
136 1.1 cgd
137 1.1 cgd #ifdef DIAGNOSTIC
138 1.3 cgd /* XXX bounds-check cookie. */
139 1.1 cgd #endif
140 1.1 cgd
141 1.3 cgd if (tc_3000_500_intr[dev].tci_func != tc_3000_500_intrnull)
142 1.3 cgd panic("tc_3000_500_intr_establish: cookie %d twice", dev);
143 1.1 cgd
144 1.3 cgd tc_3000_500_intr[dev].tci_func = func;
145 1.3 cgd tc_3000_500_intr[dev].tci_arg = arg;
146 1.1 cgd
147 1.5 cgd tc_3000_500_imask &= ~tc_3000_500_intrbits[dev];
148 1.5 cgd *(volatile u_int32_t *)TC_3000_500_IMR_WRITE = tc_3000_500_imask;
149 1.3 cgd tc_mb();
150 1.1 cgd }
151 1.1 cgd
152 1.1 cgd void
153 1.3 cgd tc_3000_500_intr_disestablish(tcadev, cookie)
154 1.3 cgd struct device *tcadev;
155 1.3 cgd void *cookie;
156 1.1 cgd {
157 1.3 cgd u_long dev = (u_long)cookie;
158 1.1 cgd
159 1.1 cgd #ifdef DIAGNOSTIC
160 1.3 cgd /* XXX bounds-check cookie. */
161 1.1 cgd #endif
162 1.1 cgd
163 1.3 cgd if (tc_3000_500_intr[dev].tci_func == tc_3000_500_intrnull)
164 1.3 cgd panic("tc_3000_500_intr_disestablish: cookie %d bad intr",
165 1.1 cgd dev);
166 1.1 cgd
167 1.5 cgd tc_3000_500_imask |= tc_3000_500_intrbits[dev];
168 1.5 cgd *(volatile u_int32_t *)TC_3000_500_IMR_WRITE = tc_3000_500_imask;
169 1.3 cgd tc_mb();
170 1.3 cgd
171 1.3 cgd tc_3000_500_intr[dev].tci_func = tc_3000_500_intrnull;
172 1.3 cgd tc_3000_500_intr[dev].tci_arg = (void *)dev;
173 1.3 cgd }
174 1.3 cgd
175 1.3 cgd int
176 1.3 cgd tc_3000_500_intrnull(val)
177 1.3 cgd void *val;
178 1.3 cgd {
179 1.1 cgd
180 1.3 cgd panic("tc_3000_500_intrnull: uncaught TC intr for cookie %ld\n",
181 1.3 cgd (u_long)val);
182 1.1 cgd }
183 1.1 cgd
184 1.1 cgd void
185 1.1 cgd tc_3000_500_iointr(framep, vec)
186 1.1 cgd void *framep;
187 1.9 cgd unsigned long vec;
188 1.1 cgd {
189 1.5 cgd u_int32_t ir;
190 1.1 cgd int ifound;
191 1.1 cgd
192 1.1 cgd #ifdef DIAGNOSTIC
193 1.1 cgd int s;
194 1.1 cgd if (vec != 0x800)
195 1.9 cgd panic("INVALID ASSUMPTION: vec 0x%lx, not 0x800", vec);
196 1.1 cgd s = splhigh();
197 1.8 cgd if (s != ALPHA_PSL_IPL_IO)
198 1.8 cgd panic("INVALID ASSUMPTION: IPL %d, not %d", s,
199 1.8 cgd ALPHA_PSL_IPL_IO);
200 1.1 cgd splx(s);
201 1.1 cgd #endif
202 1.1 cgd
203 1.1 cgd do {
204 1.3 cgd tc_syncbus();
205 1.5 cgd ir = *(volatile u_int32_t *)TC_3000_500_IR_CLEAR;
206 1.4 cgd
207 1.4 cgd /* Ignore interrupts that we haven't enabled. */
208 1.5 cgd ir &= ~(tc_3000_500_imask & 0x1ff);
209 1.1 cgd
210 1.1 cgd ifound = 0;
211 1.6 cgd
212 1.6 cgd #ifdef EVCNT_COUNTERS
213 1.6 cgd /* No interrupt counting via evcnt counters */
214 1.6 cgd XXX BREAK HERE XXX
215 1.6 cgd #else /* !EVCNT_COUNTERS */
216 1.6 cgd #define INCRINTRCNT(slot) intrcnt[INTRCNT_KN15 + slot]++
217 1.6 cgd #endif /* EVCNT_COUNTERS */
218 1.6 cgd
219 1.3 cgd #define CHECKINTR(slot) \
220 1.3 cgd if (ir & tc_3000_500_intrbits[slot]) { \
221 1.1 cgd ifound = 1; \
222 1.6 cgd INCRINTRCNT(slot); \
223 1.3 cgd (*tc_3000_500_intr[slot].tci_func) \
224 1.3 cgd (tc_3000_500_intr[slot].tci_arg); \
225 1.1 cgd }
226 1.1 cgd /* Do them in order of priority; highest slot # first. */
227 1.3 cgd CHECKINTR(TC_3000_500_DEV_CXTURBO);
228 1.3 cgd CHECKINTR(TC_3000_500_DEV_IOASIC);
229 1.3 cgd CHECKINTR(TC_3000_500_DEV_TCDS);
230 1.3 cgd CHECKINTR(TC_3000_500_DEV_OPT5);
231 1.3 cgd CHECKINTR(TC_3000_500_DEV_OPT4);
232 1.3 cgd CHECKINTR(TC_3000_500_DEV_OPT3);
233 1.3 cgd CHECKINTR(TC_3000_500_DEV_OPT2);
234 1.3 cgd CHECKINTR(TC_3000_500_DEV_OPT1);
235 1.3 cgd CHECKINTR(TC_3000_500_DEV_OPT0);
236 1.1 cgd #undef CHECKINTR
237 1.1 cgd
238 1.1 cgd #ifdef DIAGNOSTIC
239 1.1 cgd #define PRINTINTR(msg, bits) \
240 1.1 cgd if (ir & bits) \
241 1.11 christos printf(msg);
242 1.1 cgd PRINTINTR("Second error occurred\n", TC_3000_500_IR_ERR2);
243 1.1 cgd PRINTINTR("DMA buffer error\n", TC_3000_500_IR_DMABE);
244 1.1 cgd PRINTINTR("DMA cross 2K boundary\n", TC_3000_500_IR_DMA2K);
245 1.1 cgd PRINTINTR("TC reset in progress\n", TC_3000_500_IR_TCRESET);
246 1.1 cgd PRINTINTR("TC parity error\n", TC_3000_500_IR_TCPAR);
247 1.1 cgd PRINTINTR("DMA tag error\n", TC_3000_500_IR_DMATAG);
248 1.1 cgd PRINTINTR("Single-bit error\n", TC_3000_500_IR_DMASBE);
249 1.1 cgd PRINTINTR("Double-bit error\n", TC_3000_500_IR_DMADBE);
250 1.1 cgd PRINTINTR("TC I/O timeout\n", TC_3000_500_IR_TCTIMEOUT);
251 1.1 cgd PRINTINTR("DMA block too long\n", TC_3000_500_IR_DMABLOCK);
252 1.1 cgd PRINTINTR("Invalid I/O address\n", TC_3000_500_IR_IOADDR);
253 1.1 cgd PRINTINTR("DMA scatter/gather invalid\n", TC_3000_500_IR_DMASG);
254 1.1 cgd PRINTINTR("Scatter/gather parity error\n",
255 1.1 cgd TC_3000_500_IR_SGPAR);
256 1.1 cgd #undef PRINTINTR
257 1.1 cgd #endif
258 1.1 cgd } while (ifound);
259 1.1 cgd }
260 1.1 cgd
261 1.8 cgd #if 0
262 1.1 cgd /*
263 1.1 cgd * tc_3000_500_ioslot --
264 1.1 cgd * Set the PBS bits for devices on the TC.
265 1.1 cgd */
266 1.1 cgd void
267 1.1 cgd tc_3000_500_ioslot(slot, flags, set)
268 1.1 cgd u_int32_t slot, flags;
269 1.1 cgd int set;
270 1.1 cgd {
271 1.1 cgd volatile u_int32_t *iosp;
272 1.1 cgd u_int32_t ios;
273 1.1 cgd int s;
274 1.1 cgd
275 1.1 cgd iosp = (volatile u_int32_t *)TC_3000_500_IOSLOT;
276 1.1 cgd ios = *iosp;
277 1.1 cgd flags <<= (slot * 3);
278 1.1 cgd if (set)
279 1.1 cgd ios |= flags;
280 1.1 cgd else
281 1.1 cgd ios &= ~flags;
282 1.1 cgd s = splhigh();
283 1.1 cgd *iosp = ios;
284 1.3 cgd tc_mb();
285 1.1 cgd splx(s);
286 1.1 cgd }
287 1.8 cgd #endif
288