tc_3000_500.c revision 1.16 1 1.16 briggs /* $NetBSD: tc_3000_500.c,v 1.16 1998/10/22 01:03:09 briggs Exp $ */
2 1.1 cgd
3 1.1 cgd /*
4 1.7 cgd * Copyright (c) 1994, 1995, 1996 Carnegie-Mellon University.
5 1.1 cgd * All rights reserved.
6 1.1 cgd *
7 1.1 cgd * Author: Chris G. Demetriou
8 1.1 cgd *
9 1.1 cgd * Permission to use, copy, modify and distribute this software and
10 1.1 cgd * its documentation is hereby granted, provided that both the copyright
11 1.1 cgd * notice and this permission notice appear in all copies of the
12 1.1 cgd * software, derivative works or modified versions, and any portions
13 1.1 cgd * thereof, and that both notices appear in supporting documentation.
14 1.1 cgd *
15 1.1 cgd * CARNEGIE MELLON ALLOWS FREE USE OF THIS SOFTWARE IN ITS "AS IS"
16 1.1 cgd * CONDITION. CARNEGIE MELLON DISCLAIMS ANY LIABILITY OF ANY KIND
17 1.1 cgd * FOR ANY DAMAGES WHATSOEVER RESULTING FROM THE USE OF THIS SOFTWARE.
18 1.1 cgd *
19 1.1 cgd * Carnegie Mellon requests users of this software to return to
20 1.1 cgd *
21 1.1 cgd * Software Distribution Coordinator or Software.Distribution (at) CS.CMU.EDU
22 1.1 cgd * School of Computer Science
23 1.1 cgd * Carnegie Mellon University
24 1.1 cgd * Pittsburgh PA 15213-3890
25 1.1 cgd *
26 1.1 cgd * any improvements or extensions that they make and grant Carnegie the
27 1.1 cgd * rights to redistribute these changes.
28 1.1 cgd */
29 1.13 cgd
30 1.14 cgd #include <sys/cdefs.h> /* RCS ID & Copyright macro defns */
31 1.14 cgd
32 1.16 briggs __KERNEL_RCSID(0, "$NetBSD: tc_3000_500.c,v 1.16 1998/10/22 01:03:09 briggs Exp $");
33 1.1 cgd
34 1.1 cgd #include <sys/param.h>
35 1.8 cgd #include <sys/systm.h>
36 1.1 cgd #include <sys/device.h>
37 1.1 cgd
38 1.1 cgd #include <machine/autoconf.h>
39 1.1 cgd #include <machine/pte.h>
40 1.16 briggs #include <machine/rpb.h>
41 1.6 cgd #ifndef EVCNT_COUNTERS
42 1.6 cgd #include <machine/intrcnt.h>
43 1.6 cgd #endif
44 1.1 cgd
45 1.3 cgd #include <dev/tc/tcvar.h>
46 1.3 cgd #include <alpha/tc/tc_conf.h>
47 1.1 cgd #include <alpha/tc/tc_3000_500.h>
48 1.16 briggs #include <alpha/tc/sfbvar.h>
49 1.1 cgd
50 1.1 cgd void tc_3000_500_intr_setup __P((void));
51 1.3 cgd void tc_3000_500_intr_establish __P((struct device *, void *,
52 1.3 cgd tc_intrlevel_t, int (*)(void *), void *));
53 1.3 cgd void tc_3000_500_intr_disestablish __P((struct device *, void *));
54 1.9 cgd void tc_3000_500_iointr __P((void *, unsigned long));
55 1.1 cgd
56 1.3 cgd int tc_3000_500_intrnull __P((void *));
57 1.16 briggs int tc_3000_500_fb_cnattach __P((u_int64_t));
58 1.3 cgd
59 1.3 cgd #define C(x) ((void *)(u_long)x)
60 1.8 cgd #define KV(x) (ALPHA_PHYS_TO_K0SEG(x))
61 1.3 cgd
62 1.3 cgd struct tc_slotdesc tc_3000_500_slots[] = {
63 1.3 cgd { KV(0x100000000), C(TC_3000_500_DEV_OPT0), }, /* 0 - opt slot 0 */
64 1.3 cgd { KV(0x120000000), C(TC_3000_500_DEV_OPT1), }, /* 1 - opt slot 1 */
65 1.3 cgd { KV(0x140000000), C(TC_3000_500_DEV_OPT2), }, /* 2 - opt slot 2 */
66 1.3 cgd { KV(0x160000000), C(TC_3000_500_DEV_OPT3), }, /* 3 - opt slot 3 */
67 1.3 cgd { KV(0x180000000), C(TC_3000_500_DEV_OPT4), }, /* 4 - opt slot 4 */
68 1.3 cgd { KV(0x1a0000000), C(TC_3000_500_DEV_OPT5), }, /* 5 - opt slot 5 */
69 1.3 cgd { KV(0x1c0000000), C(TC_3000_500_DEV_BOGUS), }, /* 6 - TCDS ASIC */
70 1.3 cgd { KV(0x1e0000000), C(TC_3000_500_DEV_BOGUS), }, /* 7 - IOCTL ASIC */
71 1.1 cgd };
72 1.3 cgd int tc_3000_500_nslots =
73 1.3 cgd sizeof(tc_3000_500_slots) / sizeof(tc_3000_500_slots[0]);
74 1.1 cgd
75 1.12 cgd struct tc_builtin tc_3000_500_graphics_builtins[] = {
76 1.3 cgd { "FLAMG-IO", 7, 0x00000000, C(TC_3000_500_DEV_IOASIC), },
77 1.3 cgd { "PMAGB-BA", 7, 0x02000000, C(TC_3000_500_DEV_CXTURBO), },
78 1.3 cgd { "PMAZ-DS ", 6, 0x00000000, C(TC_3000_500_DEV_TCDS), },
79 1.1 cgd };
80 1.12 cgd int tc_3000_500_graphics_nbuiltins = sizeof(tc_3000_500_graphics_builtins) /
81 1.12 cgd sizeof(tc_3000_500_graphics_builtins[0]);
82 1.12 cgd
83 1.12 cgd struct tc_builtin tc_3000_500_nographics_builtins[] = {
84 1.12 cgd { "FLAMG-IO", 7, 0x00000000, C(TC_3000_500_DEV_IOASIC), },
85 1.12 cgd { "PMAZ-DS ", 6, 0x00000000, C(TC_3000_500_DEV_TCDS), },
86 1.12 cgd };
87 1.12 cgd int tc_3000_500_nographics_nbuiltins = sizeof(tc_3000_500_nographics_builtins) /
88 1.12 cgd sizeof(tc_3000_500_nographics_builtins[0]);
89 1.1 cgd
90 1.3 cgd u_int32_t tc_3000_500_intrbits[TC_3000_500_NCOOKIES] = {
91 1.3 cgd TC_3000_500_IR_OPT0,
92 1.3 cgd TC_3000_500_IR_OPT1,
93 1.3 cgd TC_3000_500_IR_OPT2,
94 1.3 cgd TC_3000_500_IR_OPT3,
95 1.3 cgd TC_3000_500_IR_OPT4,
96 1.3 cgd TC_3000_500_IR_OPT5,
97 1.3 cgd TC_3000_500_IR_TCDS,
98 1.3 cgd TC_3000_500_IR_IOASIC,
99 1.3 cgd TC_3000_500_IR_CXTURBO,
100 1.1 cgd };
101 1.1 cgd
102 1.3 cgd struct tcintr {
103 1.3 cgd int (*tci_func) __P((void *));
104 1.3 cgd void *tci_arg;
105 1.3 cgd } tc_3000_500_intr[TC_3000_500_NCOOKIES];
106 1.1 cgd
107 1.5 cgd u_int32_t tc_3000_500_imask; /* intrs we want to ignore; mirrors IMR. */
108 1.5 cgd
109 1.1 cgd void
110 1.1 cgd tc_3000_500_intr_setup()
111 1.1 cgd {
112 1.3 cgd u_long i;
113 1.1 cgd
114 1.3 cgd /*
115 1.4 cgd * Disable all slot interrupts. Note that this cannot
116 1.4 cgd * actually disable CXTurbo, TCDS, and IOASIC interrupts.
117 1.3 cgd */
118 1.5 cgd tc_3000_500_imask = *(volatile u_int32_t *)TC_3000_500_IMR_READ;
119 1.3 cgd for (i = 0; i < TC_3000_500_NCOOKIES; i++)
120 1.5 cgd tc_3000_500_imask |= tc_3000_500_intrbits[i];
121 1.5 cgd *(volatile u_int32_t *)TC_3000_500_IMR_WRITE = tc_3000_500_imask;
122 1.3 cgd tc_mb();
123 1.1 cgd
124 1.3 cgd /*
125 1.3 cgd * Set up interrupt handlers.
126 1.1 cgd */
127 1.3 cgd for (i = 0; i < TC_3000_500_NCOOKIES; i++) {
128 1.3 cgd tc_3000_500_intr[i].tci_func = tc_3000_500_intrnull;
129 1.3 cgd tc_3000_500_intr[i].tci_arg = (void *)i;
130 1.3 cgd }
131 1.1 cgd }
132 1.1 cgd
133 1.1 cgd void
134 1.3 cgd tc_3000_500_intr_establish(tcadev, cookie, level, func, arg)
135 1.3 cgd struct device *tcadev;
136 1.3 cgd void *cookie, *arg;
137 1.3 cgd tc_intrlevel_t level;
138 1.3 cgd int (*func) __P((void *));
139 1.1 cgd {
140 1.3 cgd u_long dev = (u_long)cookie;
141 1.1 cgd
142 1.1 cgd #ifdef DIAGNOSTIC
143 1.3 cgd /* XXX bounds-check cookie. */
144 1.1 cgd #endif
145 1.1 cgd
146 1.3 cgd if (tc_3000_500_intr[dev].tci_func != tc_3000_500_intrnull)
147 1.3 cgd panic("tc_3000_500_intr_establish: cookie %d twice", dev);
148 1.1 cgd
149 1.3 cgd tc_3000_500_intr[dev].tci_func = func;
150 1.3 cgd tc_3000_500_intr[dev].tci_arg = arg;
151 1.1 cgd
152 1.5 cgd tc_3000_500_imask &= ~tc_3000_500_intrbits[dev];
153 1.5 cgd *(volatile u_int32_t *)TC_3000_500_IMR_WRITE = tc_3000_500_imask;
154 1.3 cgd tc_mb();
155 1.1 cgd }
156 1.1 cgd
157 1.1 cgd void
158 1.3 cgd tc_3000_500_intr_disestablish(tcadev, cookie)
159 1.3 cgd struct device *tcadev;
160 1.3 cgd void *cookie;
161 1.1 cgd {
162 1.3 cgd u_long dev = (u_long)cookie;
163 1.1 cgd
164 1.1 cgd #ifdef DIAGNOSTIC
165 1.3 cgd /* XXX bounds-check cookie. */
166 1.1 cgd #endif
167 1.1 cgd
168 1.3 cgd if (tc_3000_500_intr[dev].tci_func == tc_3000_500_intrnull)
169 1.3 cgd panic("tc_3000_500_intr_disestablish: cookie %d bad intr",
170 1.1 cgd dev);
171 1.1 cgd
172 1.5 cgd tc_3000_500_imask |= tc_3000_500_intrbits[dev];
173 1.5 cgd *(volatile u_int32_t *)TC_3000_500_IMR_WRITE = tc_3000_500_imask;
174 1.3 cgd tc_mb();
175 1.3 cgd
176 1.3 cgd tc_3000_500_intr[dev].tci_func = tc_3000_500_intrnull;
177 1.3 cgd tc_3000_500_intr[dev].tci_arg = (void *)dev;
178 1.3 cgd }
179 1.3 cgd
180 1.3 cgd int
181 1.3 cgd tc_3000_500_intrnull(val)
182 1.3 cgd void *val;
183 1.3 cgd {
184 1.1 cgd
185 1.3 cgd panic("tc_3000_500_intrnull: uncaught TC intr for cookie %ld\n",
186 1.3 cgd (u_long)val);
187 1.1 cgd }
188 1.1 cgd
189 1.1 cgd void
190 1.1 cgd tc_3000_500_iointr(framep, vec)
191 1.1 cgd void *framep;
192 1.9 cgd unsigned long vec;
193 1.1 cgd {
194 1.5 cgd u_int32_t ir;
195 1.1 cgd int ifound;
196 1.1 cgd
197 1.1 cgd #ifdef DIAGNOSTIC
198 1.1 cgd int s;
199 1.1 cgd if (vec != 0x800)
200 1.9 cgd panic("INVALID ASSUMPTION: vec 0x%lx, not 0x800", vec);
201 1.1 cgd s = splhigh();
202 1.8 cgd if (s != ALPHA_PSL_IPL_IO)
203 1.8 cgd panic("INVALID ASSUMPTION: IPL %d, not %d", s,
204 1.8 cgd ALPHA_PSL_IPL_IO);
205 1.1 cgd splx(s);
206 1.1 cgd #endif
207 1.1 cgd
208 1.1 cgd do {
209 1.3 cgd tc_syncbus();
210 1.5 cgd ir = *(volatile u_int32_t *)TC_3000_500_IR_CLEAR;
211 1.4 cgd
212 1.4 cgd /* Ignore interrupts that we haven't enabled. */
213 1.5 cgd ir &= ~(tc_3000_500_imask & 0x1ff);
214 1.1 cgd
215 1.1 cgd ifound = 0;
216 1.6 cgd
217 1.6 cgd #ifdef EVCNT_COUNTERS
218 1.6 cgd /* No interrupt counting via evcnt counters */
219 1.6 cgd XXX BREAK HERE XXX
220 1.6 cgd #else /* !EVCNT_COUNTERS */
221 1.6 cgd #define INCRINTRCNT(slot) intrcnt[INTRCNT_KN15 + slot]++
222 1.6 cgd #endif /* EVCNT_COUNTERS */
223 1.6 cgd
224 1.3 cgd #define CHECKINTR(slot) \
225 1.3 cgd if (ir & tc_3000_500_intrbits[slot]) { \
226 1.1 cgd ifound = 1; \
227 1.6 cgd INCRINTRCNT(slot); \
228 1.3 cgd (*tc_3000_500_intr[slot].tci_func) \
229 1.3 cgd (tc_3000_500_intr[slot].tci_arg); \
230 1.1 cgd }
231 1.1 cgd /* Do them in order of priority; highest slot # first. */
232 1.3 cgd CHECKINTR(TC_3000_500_DEV_CXTURBO);
233 1.3 cgd CHECKINTR(TC_3000_500_DEV_IOASIC);
234 1.3 cgd CHECKINTR(TC_3000_500_DEV_TCDS);
235 1.3 cgd CHECKINTR(TC_3000_500_DEV_OPT5);
236 1.3 cgd CHECKINTR(TC_3000_500_DEV_OPT4);
237 1.3 cgd CHECKINTR(TC_3000_500_DEV_OPT3);
238 1.3 cgd CHECKINTR(TC_3000_500_DEV_OPT2);
239 1.3 cgd CHECKINTR(TC_3000_500_DEV_OPT1);
240 1.3 cgd CHECKINTR(TC_3000_500_DEV_OPT0);
241 1.1 cgd #undef CHECKINTR
242 1.1 cgd
243 1.1 cgd #ifdef DIAGNOSTIC
244 1.1 cgd #define PRINTINTR(msg, bits) \
245 1.1 cgd if (ir & bits) \
246 1.11 christos printf(msg);
247 1.1 cgd PRINTINTR("Second error occurred\n", TC_3000_500_IR_ERR2);
248 1.1 cgd PRINTINTR("DMA buffer error\n", TC_3000_500_IR_DMABE);
249 1.1 cgd PRINTINTR("DMA cross 2K boundary\n", TC_3000_500_IR_DMA2K);
250 1.1 cgd PRINTINTR("TC reset in progress\n", TC_3000_500_IR_TCRESET);
251 1.1 cgd PRINTINTR("TC parity error\n", TC_3000_500_IR_TCPAR);
252 1.1 cgd PRINTINTR("DMA tag error\n", TC_3000_500_IR_DMATAG);
253 1.1 cgd PRINTINTR("Single-bit error\n", TC_3000_500_IR_DMASBE);
254 1.1 cgd PRINTINTR("Double-bit error\n", TC_3000_500_IR_DMADBE);
255 1.1 cgd PRINTINTR("TC I/O timeout\n", TC_3000_500_IR_TCTIMEOUT);
256 1.1 cgd PRINTINTR("DMA block too long\n", TC_3000_500_IR_DMABLOCK);
257 1.1 cgd PRINTINTR("Invalid I/O address\n", TC_3000_500_IR_IOADDR);
258 1.1 cgd PRINTINTR("DMA scatter/gather invalid\n", TC_3000_500_IR_DMASG);
259 1.1 cgd PRINTINTR("Scatter/gather parity error\n",
260 1.1 cgd TC_3000_500_IR_SGPAR);
261 1.1 cgd #undef PRINTINTR
262 1.1 cgd #endif
263 1.1 cgd } while (ifound);
264 1.16 briggs }
265 1.16 briggs
266 1.16 briggs /*
267 1.16 briggs * tc_3000_500_fb_cnattach --
268 1.16 briggs * Attempt to map the CTB output device to a slot and attach the
269 1.16 briggs * framebuffer as the output side of the console.
270 1.16 briggs */
271 1.16 briggs int
272 1.16 briggs tc_3000_500_fb_cnattach(turbo_slot)
273 1.16 briggs u_int64_t turbo_slot;
274 1.16 briggs {
275 1.16 briggs u_int32_t output_slot;
276 1.16 briggs
277 1.16 briggs output_slot = turbo_slot & 0xffffffff;
278 1.16 briggs
279 1.16 briggs if (output_slot >= tc_3000_500_nslots) {
280 1.16 briggs return 0;
281 1.16 briggs }
282 1.16 briggs
283 1.16 briggs if (hwrpb->rpb_variation & SV_GRAPHICS) {
284 1.16 briggs if (output_slot == 0) {
285 1.16 briggs sfb_cnattach(KV(0x1e0000000) + 0x02000000);
286 1.16 briggs return 1;
287 1.16 briggs }
288 1.16 briggs } else {
289 1.16 briggs /*
290 1.16 briggs * Slots 0-2 in the tc_3000_500_slots array are only
291 1.16 briggs * on the 500 models that also have the CXTurbo
292 1.16 briggs * (500/800/900) and a total of 6 TC slots. For the
293 1.16 briggs * 400/600/700, slots 0-2 are in table locations 3-5, so
294 1.16 briggs * offset the CTB slot by 3 to get the address in our table.
295 1.16 briggs */
296 1.16 briggs output_slot += 3;
297 1.16 briggs }
298 1.16 briggs return tc_fb_cnattach(tc_3000_500_slots[output_slot-1].tcs_addr);
299 1.1 cgd }
300 1.1 cgd
301 1.8 cgd #if 0
302 1.1 cgd /*
303 1.1 cgd * tc_3000_500_ioslot --
304 1.1 cgd * Set the PBS bits for devices on the TC.
305 1.1 cgd */
306 1.1 cgd void
307 1.1 cgd tc_3000_500_ioslot(slot, flags, set)
308 1.1 cgd u_int32_t slot, flags;
309 1.1 cgd int set;
310 1.1 cgd {
311 1.1 cgd volatile u_int32_t *iosp;
312 1.1 cgd u_int32_t ios;
313 1.1 cgd int s;
314 1.1 cgd
315 1.1 cgd iosp = (volatile u_int32_t *)TC_3000_500_IOSLOT;
316 1.1 cgd ios = *iosp;
317 1.1 cgd flags <<= (slot * 3);
318 1.1 cgd if (set)
319 1.1 cgd ios |= flags;
320 1.1 cgd else
321 1.1 cgd ios &= ~flags;
322 1.1 cgd s = splhigh();
323 1.1 cgd *iosp = ios;
324 1.3 cgd tc_mb();
325 1.1 cgd splx(s);
326 1.1 cgd }
327 1.8 cgd #endif
328