tc_3000_500.c revision 1.17 1 1.17 briggs /* $NetBSD: tc_3000_500.c,v 1.17 1998/10/23 23:49:31 briggs Exp $ */
2 1.1 cgd
3 1.1 cgd /*
4 1.7 cgd * Copyright (c) 1994, 1995, 1996 Carnegie-Mellon University.
5 1.1 cgd * All rights reserved.
6 1.1 cgd *
7 1.1 cgd * Author: Chris G. Demetriou
8 1.1 cgd *
9 1.1 cgd * Permission to use, copy, modify and distribute this software and
10 1.1 cgd * its documentation is hereby granted, provided that both the copyright
11 1.1 cgd * notice and this permission notice appear in all copies of the
12 1.1 cgd * software, derivative works or modified versions, and any portions
13 1.1 cgd * thereof, and that both notices appear in supporting documentation.
14 1.1 cgd *
15 1.1 cgd * CARNEGIE MELLON ALLOWS FREE USE OF THIS SOFTWARE IN ITS "AS IS"
16 1.1 cgd * CONDITION. CARNEGIE MELLON DISCLAIMS ANY LIABILITY OF ANY KIND
17 1.1 cgd * FOR ANY DAMAGES WHATSOEVER RESULTING FROM THE USE OF THIS SOFTWARE.
18 1.1 cgd *
19 1.1 cgd * Carnegie Mellon requests users of this software to return to
20 1.1 cgd *
21 1.1 cgd * Software Distribution Coordinator or Software.Distribution (at) CS.CMU.EDU
22 1.1 cgd * School of Computer Science
23 1.1 cgd * Carnegie Mellon University
24 1.1 cgd * Pittsburgh PA 15213-3890
25 1.1 cgd *
26 1.1 cgd * any improvements or extensions that they make and grant Carnegie the
27 1.1 cgd * rights to redistribute these changes.
28 1.1 cgd */
29 1.13 cgd
30 1.14 cgd #include <sys/cdefs.h> /* RCS ID & Copyright macro defns */
31 1.14 cgd
32 1.17 briggs __KERNEL_RCSID(0, "$NetBSD: tc_3000_500.c,v 1.17 1998/10/23 23:49:31 briggs Exp $");
33 1.1 cgd
34 1.1 cgd #include <sys/param.h>
35 1.8 cgd #include <sys/systm.h>
36 1.1 cgd #include <sys/device.h>
37 1.1 cgd
38 1.1 cgd #include <machine/autoconf.h>
39 1.1 cgd #include <machine/pte.h>
40 1.16 briggs #include <machine/rpb.h>
41 1.6 cgd #ifndef EVCNT_COUNTERS
42 1.6 cgd #include <machine/intrcnt.h>
43 1.6 cgd #endif
44 1.1 cgd
45 1.3 cgd #include <dev/tc/tcvar.h>
46 1.3 cgd #include <alpha/tc/tc_conf.h>
47 1.1 cgd #include <alpha/tc/tc_3000_500.h>
48 1.17 briggs
49 1.17 briggs #include "sfb.h"
50 1.17 briggs
51 1.17 briggs #if NSFB > 0
52 1.16 briggs #include <alpha/tc/sfbvar.h>
53 1.17 briggs #endif
54 1.1 cgd
55 1.1 cgd void tc_3000_500_intr_setup __P((void));
56 1.3 cgd void tc_3000_500_intr_establish __P((struct device *, void *,
57 1.3 cgd tc_intrlevel_t, int (*)(void *), void *));
58 1.3 cgd void tc_3000_500_intr_disestablish __P((struct device *, void *));
59 1.9 cgd void tc_3000_500_iointr __P((void *, unsigned long));
60 1.1 cgd
61 1.3 cgd int tc_3000_500_intrnull __P((void *));
62 1.16 briggs int tc_3000_500_fb_cnattach __P((u_int64_t));
63 1.3 cgd
64 1.3 cgd #define C(x) ((void *)(u_long)x)
65 1.8 cgd #define KV(x) (ALPHA_PHYS_TO_K0SEG(x))
66 1.3 cgd
67 1.3 cgd struct tc_slotdesc tc_3000_500_slots[] = {
68 1.3 cgd { KV(0x100000000), C(TC_3000_500_DEV_OPT0), }, /* 0 - opt slot 0 */
69 1.3 cgd { KV(0x120000000), C(TC_3000_500_DEV_OPT1), }, /* 1 - opt slot 1 */
70 1.3 cgd { KV(0x140000000), C(TC_3000_500_DEV_OPT2), }, /* 2 - opt slot 2 */
71 1.3 cgd { KV(0x160000000), C(TC_3000_500_DEV_OPT3), }, /* 3 - opt slot 3 */
72 1.3 cgd { KV(0x180000000), C(TC_3000_500_DEV_OPT4), }, /* 4 - opt slot 4 */
73 1.3 cgd { KV(0x1a0000000), C(TC_3000_500_DEV_OPT5), }, /* 5 - opt slot 5 */
74 1.3 cgd { KV(0x1c0000000), C(TC_3000_500_DEV_BOGUS), }, /* 6 - TCDS ASIC */
75 1.3 cgd { KV(0x1e0000000), C(TC_3000_500_DEV_BOGUS), }, /* 7 - IOCTL ASIC */
76 1.1 cgd };
77 1.3 cgd int tc_3000_500_nslots =
78 1.3 cgd sizeof(tc_3000_500_slots) / sizeof(tc_3000_500_slots[0]);
79 1.1 cgd
80 1.12 cgd struct tc_builtin tc_3000_500_graphics_builtins[] = {
81 1.3 cgd { "FLAMG-IO", 7, 0x00000000, C(TC_3000_500_DEV_IOASIC), },
82 1.3 cgd { "PMAGB-BA", 7, 0x02000000, C(TC_3000_500_DEV_CXTURBO), },
83 1.3 cgd { "PMAZ-DS ", 6, 0x00000000, C(TC_3000_500_DEV_TCDS), },
84 1.1 cgd };
85 1.12 cgd int tc_3000_500_graphics_nbuiltins = sizeof(tc_3000_500_graphics_builtins) /
86 1.12 cgd sizeof(tc_3000_500_graphics_builtins[0]);
87 1.12 cgd
88 1.12 cgd struct tc_builtin tc_3000_500_nographics_builtins[] = {
89 1.12 cgd { "FLAMG-IO", 7, 0x00000000, C(TC_3000_500_DEV_IOASIC), },
90 1.12 cgd { "PMAZ-DS ", 6, 0x00000000, C(TC_3000_500_DEV_TCDS), },
91 1.12 cgd };
92 1.12 cgd int tc_3000_500_nographics_nbuiltins = sizeof(tc_3000_500_nographics_builtins) /
93 1.12 cgd sizeof(tc_3000_500_nographics_builtins[0]);
94 1.1 cgd
95 1.3 cgd u_int32_t tc_3000_500_intrbits[TC_3000_500_NCOOKIES] = {
96 1.3 cgd TC_3000_500_IR_OPT0,
97 1.3 cgd TC_3000_500_IR_OPT1,
98 1.3 cgd TC_3000_500_IR_OPT2,
99 1.3 cgd TC_3000_500_IR_OPT3,
100 1.3 cgd TC_3000_500_IR_OPT4,
101 1.3 cgd TC_3000_500_IR_OPT5,
102 1.3 cgd TC_3000_500_IR_TCDS,
103 1.3 cgd TC_3000_500_IR_IOASIC,
104 1.3 cgd TC_3000_500_IR_CXTURBO,
105 1.1 cgd };
106 1.1 cgd
107 1.3 cgd struct tcintr {
108 1.3 cgd int (*tci_func) __P((void *));
109 1.3 cgd void *tci_arg;
110 1.3 cgd } tc_3000_500_intr[TC_3000_500_NCOOKIES];
111 1.1 cgd
112 1.5 cgd u_int32_t tc_3000_500_imask; /* intrs we want to ignore; mirrors IMR. */
113 1.5 cgd
114 1.1 cgd void
115 1.1 cgd tc_3000_500_intr_setup()
116 1.1 cgd {
117 1.3 cgd u_long i;
118 1.1 cgd
119 1.3 cgd /*
120 1.4 cgd * Disable all slot interrupts. Note that this cannot
121 1.4 cgd * actually disable CXTurbo, TCDS, and IOASIC interrupts.
122 1.3 cgd */
123 1.5 cgd tc_3000_500_imask = *(volatile u_int32_t *)TC_3000_500_IMR_READ;
124 1.3 cgd for (i = 0; i < TC_3000_500_NCOOKIES; i++)
125 1.5 cgd tc_3000_500_imask |= tc_3000_500_intrbits[i];
126 1.5 cgd *(volatile u_int32_t *)TC_3000_500_IMR_WRITE = tc_3000_500_imask;
127 1.3 cgd tc_mb();
128 1.1 cgd
129 1.3 cgd /*
130 1.3 cgd * Set up interrupt handlers.
131 1.1 cgd */
132 1.3 cgd for (i = 0; i < TC_3000_500_NCOOKIES; i++) {
133 1.3 cgd tc_3000_500_intr[i].tci_func = tc_3000_500_intrnull;
134 1.3 cgd tc_3000_500_intr[i].tci_arg = (void *)i;
135 1.3 cgd }
136 1.1 cgd }
137 1.1 cgd
138 1.1 cgd void
139 1.3 cgd tc_3000_500_intr_establish(tcadev, cookie, level, func, arg)
140 1.3 cgd struct device *tcadev;
141 1.3 cgd void *cookie, *arg;
142 1.3 cgd tc_intrlevel_t level;
143 1.3 cgd int (*func) __P((void *));
144 1.1 cgd {
145 1.3 cgd u_long dev = (u_long)cookie;
146 1.1 cgd
147 1.1 cgd #ifdef DIAGNOSTIC
148 1.3 cgd /* XXX bounds-check cookie. */
149 1.1 cgd #endif
150 1.1 cgd
151 1.3 cgd if (tc_3000_500_intr[dev].tci_func != tc_3000_500_intrnull)
152 1.3 cgd panic("tc_3000_500_intr_establish: cookie %d twice", dev);
153 1.1 cgd
154 1.3 cgd tc_3000_500_intr[dev].tci_func = func;
155 1.3 cgd tc_3000_500_intr[dev].tci_arg = arg;
156 1.1 cgd
157 1.5 cgd tc_3000_500_imask &= ~tc_3000_500_intrbits[dev];
158 1.5 cgd *(volatile u_int32_t *)TC_3000_500_IMR_WRITE = tc_3000_500_imask;
159 1.3 cgd tc_mb();
160 1.1 cgd }
161 1.1 cgd
162 1.1 cgd void
163 1.3 cgd tc_3000_500_intr_disestablish(tcadev, cookie)
164 1.3 cgd struct device *tcadev;
165 1.3 cgd void *cookie;
166 1.1 cgd {
167 1.3 cgd u_long dev = (u_long)cookie;
168 1.1 cgd
169 1.1 cgd #ifdef DIAGNOSTIC
170 1.3 cgd /* XXX bounds-check cookie. */
171 1.1 cgd #endif
172 1.1 cgd
173 1.3 cgd if (tc_3000_500_intr[dev].tci_func == tc_3000_500_intrnull)
174 1.3 cgd panic("tc_3000_500_intr_disestablish: cookie %d bad intr",
175 1.1 cgd dev);
176 1.1 cgd
177 1.5 cgd tc_3000_500_imask |= tc_3000_500_intrbits[dev];
178 1.5 cgd *(volatile u_int32_t *)TC_3000_500_IMR_WRITE = tc_3000_500_imask;
179 1.3 cgd tc_mb();
180 1.3 cgd
181 1.3 cgd tc_3000_500_intr[dev].tci_func = tc_3000_500_intrnull;
182 1.3 cgd tc_3000_500_intr[dev].tci_arg = (void *)dev;
183 1.3 cgd }
184 1.3 cgd
185 1.3 cgd int
186 1.3 cgd tc_3000_500_intrnull(val)
187 1.3 cgd void *val;
188 1.3 cgd {
189 1.1 cgd
190 1.3 cgd panic("tc_3000_500_intrnull: uncaught TC intr for cookie %ld\n",
191 1.3 cgd (u_long)val);
192 1.1 cgd }
193 1.1 cgd
194 1.1 cgd void
195 1.1 cgd tc_3000_500_iointr(framep, vec)
196 1.1 cgd void *framep;
197 1.9 cgd unsigned long vec;
198 1.1 cgd {
199 1.5 cgd u_int32_t ir;
200 1.1 cgd int ifound;
201 1.1 cgd
202 1.1 cgd #ifdef DIAGNOSTIC
203 1.1 cgd int s;
204 1.1 cgd if (vec != 0x800)
205 1.9 cgd panic("INVALID ASSUMPTION: vec 0x%lx, not 0x800", vec);
206 1.1 cgd s = splhigh();
207 1.8 cgd if (s != ALPHA_PSL_IPL_IO)
208 1.8 cgd panic("INVALID ASSUMPTION: IPL %d, not %d", s,
209 1.8 cgd ALPHA_PSL_IPL_IO);
210 1.1 cgd splx(s);
211 1.1 cgd #endif
212 1.1 cgd
213 1.1 cgd do {
214 1.3 cgd tc_syncbus();
215 1.5 cgd ir = *(volatile u_int32_t *)TC_3000_500_IR_CLEAR;
216 1.4 cgd
217 1.4 cgd /* Ignore interrupts that we haven't enabled. */
218 1.5 cgd ir &= ~(tc_3000_500_imask & 0x1ff);
219 1.1 cgd
220 1.1 cgd ifound = 0;
221 1.6 cgd
222 1.6 cgd #ifdef EVCNT_COUNTERS
223 1.6 cgd /* No interrupt counting via evcnt counters */
224 1.6 cgd XXX BREAK HERE XXX
225 1.6 cgd #else /* !EVCNT_COUNTERS */
226 1.6 cgd #define INCRINTRCNT(slot) intrcnt[INTRCNT_KN15 + slot]++
227 1.6 cgd #endif /* EVCNT_COUNTERS */
228 1.6 cgd
229 1.3 cgd #define CHECKINTR(slot) \
230 1.3 cgd if (ir & tc_3000_500_intrbits[slot]) { \
231 1.1 cgd ifound = 1; \
232 1.6 cgd INCRINTRCNT(slot); \
233 1.3 cgd (*tc_3000_500_intr[slot].tci_func) \
234 1.3 cgd (tc_3000_500_intr[slot].tci_arg); \
235 1.1 cgd }
236 1.1 cgd /* Do them in order of priority; highest slot # first. */
237 1.3 cgd CHECKINTR(TC_3000_500_DEV_CXTURBO);
238 1.3 cgd CHECKINTR(TC_3000_500_DEV_IOASIC);
239 1.3 cgd CHECKINTR(TC_3000_500_DEV_TCDS);
240 1.3 cgd CHECKINTR(TC_3000_500_DEV_OPT5);
241 1.3 cgd CHECKINTR(TC_3000_500_DEV_OPT4);
242 1.3 cgd CHECKINTR(TC_3000_500_DEV_OPT3);
243 1.3 cgd CHECKINTR(TC_3000_500_DEV_OPT2);
244 1.3 cgd CHECKINTR(TC_3000_500_DEV_OPT1);
245 1.3 cgd CHECKINTR(TC_3000_500_DEV_OPT0);
246 1.1 cgd #undef CHECKINTR
247 1.1 cgd
248 1.1 cgd #ifdef DIAGNOSTIC
249 1.1 cgd #define PRINTINTR(msg, bits) \
250 1.1 cgd if (ir & bits) \
251 1.11 christos printf(msg);
252 1.1 cgd PRINTINTR("Second error occurred\n", TC_3000_500_IR_ERR2);
253 1.1 cgd PRINTINTR("DMA buffer error\n", TC_3000_500_IR_DMABE);
254 1.1 cgd PRINTINTR("DMA cross 2K boundary\n", TC_3000_500_IR_DMA2K);
255 1.1 cgd PRINTINTR("TC reset in progress\n", TC_3000_500_IR_TCRESET);
256 1.1 cgd PRINTINTR("TC parity error\n", TC_3000_500_IR_TCPAR);
257 1.1 cgd PRINTINTR("DMA tag error\n", TC_3000_500_IR_DMATAG);
258 1.1 cgd PRINTINTR("Single-bit error\n", TC_3000_500_IR_DMASBE);
259 1.1 cgd PRINTINTR("Double-bit error\n", TC_3000_500_IR_DMADBE);
260 1.1 cgd PRINTINTR("TC I/O timeout\n", TC_3000_500_IR_TCTIMEOUT);
261 1.1 cgd PRINTINTR("DMA block too long\n", TC_3000_500_IR_DMABLOCK);
262 1.1 cgd PRINTINTR("Invalid I/O address\n", TC_3000_500_IR_IOADDR);
263 1.1 cgd PRINTINTR("DMA scatter/gather invalid\n", TC_3000_500_IR_DMASG);
264 1.1 cgd PRINTINTR("Scatter/gather parity error\n",
265 1.1 cgd TC_3000_500_IR_SGPAR);
266 1.1 cgd #undef PRINTINTR
267 1.1 cgd #endif
268 1.1 cgd } while (ifound);
269 1.16 briggs }
270 1.16 briggs
271 1.16 briggs /*
272 1.16 briggs * tc_3000_500_fb_cnattach --
273 1.16 briggs * Attempt to map the CTB output device to a slot and attach the
274 1.16 briggs * framebuffer as the output side of the console.
275 1.16 briggs */
276 1.16 briggs int
277 1.16 briggs tc_3000_500_fb_cnattach(turbo_slot)
278 1.16 briggs u_int64_t turbo_slot;
279 1.16 briggs {
280 1.16 briggs u_int32_t output_slot;
281 1.16 briggs
282 1.16 briggs output_slot = turbo_slot & 0xffffffff;
283 1.16 briggs
284 1.16 briggs if (output_slot >= tc_3000_500_nslots) {
285 1.16 briggs return 0;
286 1.16 briggs }
287 1.16 briggs
288 1.16 briggs if (hwrpb->rpb_variation & SV_GRAPHICS) {
289 1.16 briggs if (output_slot == 0) {
290 1.17 briggs #if NSFB > 0
291 1.16 briggs sfb_cnattach(KV(0x1e0000000) + 0x02000000);
292 1.16 briggs return 1;
293 1.17 briggs #else
294 1.17 briggs return 0;
295 1.17 briggs #endif
296 1.16 briggs }
297 1.16 briggs } else {
298 1.16 briggs /*
299 1.16 briggs * Slots 0-2 in the tc_3000_500_slots array are only
300 1.16 briggs * on the 500 models that also have the CXTurbo
301 1.16 briggs * (500/800/900) and a total of 6 TC slots. For the
302 1.16 briggs * 400/600/700, slots 0-2 are in table locations 3-5, so
303 1.16 briggs * offset the CTB slot by 3 to get the address in our table.
304 1.16 briggs */
305 1.16 briggs output_slot += 3;
306 1.16 briggs }
307 1.16 briggs return tc_fb_cnattach(tc_3000_500_slots[output_slot-1].tcs_addr);
308 1.1 cgd }
309 1.1 cgd
310 1.8 cgd #if 0
311 1.1 cgd /*
312 1.1 cgd * tc_3000_500_ioslot --
313 1.1 cgd * Set the PBS bits for devices on the TC.
314 1.1 cgd */
315 1.1 cgd void
316 1.1 cgd tc_3000_500_ioslot(slot, flags, set)
317 1.1 cgd u_int32_t slot, flags;
318 1.1 cgd int set;
319 1.1 cgd {
320 1.1 cgd volatile u_int32_t *iosp;
321 1.1 cgd u_int32_t ios;
322 1.1 cgd int s;
323 1.1 cgd
324 1.1 cgd iosp = (volatile u_int32_t *)TC_3000_500_IOSLOT;
325 1.1 cgd ios = *iosp;
326 1.1 cgd flags <<= (slot * 3);
327 1.1 cgd if (set)
328 1.1 cgd ios |= flags;
329 1.1 cgd else
330 1.1 cgd ios &= ~flags;
331 1.1 cgd s = splhigh();
332 1.1 cgd *iosp = ios;
333 1.3 cgd tc_mb();
334 1.1 cgd splx(s);
335 1.1 cgd }
336 1.8 cgd #endif
337