tc_3000_500.c revision 1.1
1 /* $NetBSD: tc_3000_500.c,v 1.1 1995/02/13 23:09:08 cgd Exp $ */ 2 3 /* 4 * Copyright (c) 1994, 1995 Carnegie-Mellon University. 5 * All rights reserved. 6 * 7 * Author: Chris G. Demetriou 8 * 9 * Permission to use, copy, modify and distribute this software and 10 * its documentation is hereby granted, provided that both the copyright 11 * notice and this permission notice appear in all copies of the 12 * software, derivative works or modified versions, and any portions 13 * thereof, and that both notices appear in supporting documentation. 14 * 15 * CARNEGIE MELLON ALLOWS FREE USE OF THIS SOFTWARE IN ITS "AS IS" 16 * CONDITION. CARNEGIE MELLON DISCLAIMS ANY LIABILITY OF ANY KIND 17 * FOR ANY DAMAGES WHATSOEVER RESULTING FROM THE USE OF THIS SOFTWARE. 18 * 19 * Carnegie Mellon requests users of this software to return to 20 * 21 * Software Distribution Coordinator or Software.Distribution (at) CS.CMU.EDU 22 * School of Computer Science 23 * Carnegie Mellon University 24 * Pittsburgh PA 15213-3890 25 * 26 * any improvements or extensions that they make and grant Carnegie the 27 * rights to redistribute these changes. 28 */ 29 30 #include <sys/param.h> 31 #include <sys/device.h> 32 33 #include <machine/autoconf.h> 34 #include <machine/pte.h> 35 36 #include <alpha/tc/tc.h> 37 #include <alpha/tc/tc_3000_500.h> 38 39 /* XXX ESTABLISH, DISESTABLISH */ 40 void tc_3000_500_intr_setup __P((void)); 41 void tc_3000_500_intr_establish 42 __P((struct confargs *, intr_handler_t, void *)); 43 void tc_3000_500_intr_disestablish __P((struct confargs *)); 44 void tc_3000_500_iointr __P((void *, int)); 45 int tc_3000_500_getdev __P((struct confargs *)); 46 47 #define KV(x) ((caddr_t)phystok0seg(x)) 48 #define TC_3000_500_NSLOTS 8 49 #define TC_3000_500_MAXDEVS 9 50 51 static struct tc_slot_desc dec_3000_500_slots[TC_3000_500_NSLOTS] = { 52 { KV(0x100000000), }, /* slot 0 - TC option slot 0 */ 53 { KV(0x120000000), }, /* slot 1 - TC option slot 1 */ 54 { KV(0x140000000), }, /* slot 2 - TC option slot 2 */ 55 { KV(0x160000000), }, /* slot 3 - TC option slot 3 */ 56 { KV(0x180000000), }, /* slot 4 - TC option slot 4 */ 57 { KV(0x1a0000000), }, /* slot 5 - TC option slot 5 */ 58 { KV(0x1c0000000), }, /* slot 6 - TCDS ASIC on cpu board */ 59 { KV(0x1e0000000), }, /* slot 7 - IOCTL ASIC on cpu board */ 60 }; 61 62 static struct confargs dec_3000_500_devs[TC_3000_500_MAXDEVS] = { 63 { "IOCTL ", 7, 0x00000000, }, 64 { "PMAGB-BA", 7, 0x02000000, }, 65 { "PMAZ-DS ", 6, 0x00000000, }, 66 { NULL, 5, 0x0, }, 67 { NULL, 4, 0x0, }, 68 { NULL, 3, 0x0, }, 69 { NULL, 2, 0x0, }, 70 { NULL, 1, 0x0, }, 71 { NULL, 0, 0x0, }, 72 }; 73 74 /* Indices into the struct confargs array. */ 75 #define TC_3000_500_DEV_IOCTL 0 76 #define TC_3000_500_DEV_CXTURBO 1 77 #define TC_3000_500_DEV_TCDS 2 78 #define TC_3000_500_DEV_OPT5 3 79 #define TC_3000_500_DEV_OPT4 4 80 #define TC_3000_500_DEV_OPT3 5 81 #define TC_3000_500_DEV_OPT2 6 82 #define TC_3000_500_DEV_OPT1 7 83 #define TC_3000_500_DEV_OPT0 8 84 85 struct tc_cpu_desc dec_3000_500_cpu = { 86 dec_3000_500_slots, TC_3000_500_NSLOTS, 87 dec_3000_500_devs, TC_3000_500_MAXDEVS, 88 tc_3000_500_intr_setup, 89 tc_3000_500_intr_establish, 90 tc_3000_500_intr_disestablish, 91 tc_3000_500_iointr, 92 }; 93 94 intr_handler_t tc_3000_500_intrhand[TC_3000_500_MAXDEVS]; 95 void *tc_3000_500_intrval[TC_3000_500_MAXDEVS]; 96 97 void 98 tc_3000_500_intr_setup() 99 { 100 int i; 101 102 /* Set up interrupt handlers. */ 103 for (i = 0; i < TC_3000_500_MAXDEVS; i++) { 104 tc_3000_500_intrhand[i] = tc_intrnull; 105 tc_3000_500_intrval[i] = (void *)(long)i; 106 } 107 108 /* 109 * XXX 110 * The System Programmer's Manual (3-15) says IMR entries for option 111 * slots are initialized to 0. I think this is wrong, and that they 112 * are initialized to 1, i.e. the option slots are disabled. Enable 113 * them. 114 * 115 * XXX 116 * The MACH code appears to enable them by setting them to 1. !?!?! 117 */ 118 *(volatile u_int32_t *)TC_3000_500_IMR_WRITE = 0; 119 MB(); 120 } 121 122 void 123 tc_3000_500_intr_establish(ca, handler, val) 124 struct confargs *ca; 125 int (*handler) __P((void *)); 126 void *val; 127 { 128 int dev = tc_3000_500_getdev(ca); 129 130 #ifdef DIAGNOSTIC 131 if (dev == -1) 132 panic("tc_3000_500_intr_establish: dev == -1"); 133 #endif 134 135 if (tc_3000_500_intrhand[dev] != tc_intrnull) 136 panic("tc_3000_500_intr_establish: dev %d twice", dev); 137 138 tc_3000_500_intrhand[dev] = handler; 139 tc_3000_500_intrval[dev] = val; 140 141 /* XXX ENABLE INTERRUPT MASK FOR DEV */ 142 } 143 144 void 145 tc_3000_500_intr_disestablish(ca) 146 struct confargs *ca; 147 { 148 int dev = tc_3000_500_getdev(ca); 149 150 #ifdef DIAGNOSTIC 151 if (dev == -1) 152 panic("tc_3000_500_intr_disestablish: somebody goofed"); 153 #endif 154 155 if (tc_3000_500_intrhand[dev] == tc_intrnull) 156 panic("tc_3000_500_intr_disestablish: dev %d missing intr", 157 dev); 158 159 tc_3000_500_intrhand[dev] = tc_intrnull; 160 tc_3000_500_intrval[dev] = (void *)(long)dev; 161 162 /* XXX DISABLE INTERRUPT MASK FOR DEV */ 163 } 164 165 void 166 tc_3000_500_iointr(framep, vec) 167 void *framep; 168 int vec; 169 { 170 u_int32_t ir; 171 int ifound; 172 173 #ifdef DIAGNOSTIC 174 int s; 175 if (vec != 0x800) 176 panic("INVALID ASSUMPTION: vec %x, not 0x800", vec); 177 s = splhigh(); 178 if (s != PSL_IPL_IO) 179 panic("INVALID ASSUMPTION: IPL %d, not %d", s, PSL_IPL_IO); 180 splx(s); 181 #endif 182 183 do { 184 MAGIC_READ; 185 MB(); 186 ir = *(volatile u_int32_t *)TC_3000_500_IR_CLEAR; 187 MB(); 188 189 ifound = 0; 190 #define CHECKINTR(slot, bits) \ 191 if (ir & bits) { \ 192 ifound = 1; \ 193 (*tc_3000_500_intrhand[slot]) \ 194 (tc_3000_500_intrval[slot]); \ 195 } 196 /* Do them in order of priority; highest slot # first. */ 197 CHECKINTR(TC_3000_500_DEV_CXTURBO, TC_3000_500_IR_CXTURBO); 198 CHECKINTR(TC_3000_500_DEV_IOCTL, TC_3000_500_IR_IOCTL); 199 CHECKINTR(TC_3000_500_DEV_TCDS, TC_3000_500_IR_TCDS); 200 CHECKINTR(TC_3000_500_DEV_OPT5, TC_3000_500_IR_OPT5); 201 CHECKINTR(TC_3000_500_DEV_OPT4, TC_3000_500_IR_OPT4); 202 CHECKINTR(TC_3000_500_DEV_OPT3, TC_3000_500_IR_OPT3); 203 CHECKINTR(TC_3000_500_DEV_OPT2, TC_3000_500_IR_OPT2); 204 CHECKINTR(TC_3000_500_DEV_OPT1, TC_3000_500_IR_OPT1); 205 CHECKINTR(TC_3000_500_DEV_OPT0, TC_3000_500_IR_OPT0); 206 #undef CHECKINTR 207 208 #ifdef DIAGNOSTIC 209 #define PRINTINTR(msg, bits) \ 210 if (ir & bits) \ 211 printf(msg); 212 PRINTINTR("Second error occurred\n", TC_3000_500_IR_ERR2); 213 PRINTINTR("DMA buffer error\n", TC_3000_500_IR_DMABE); 214 PRINTINTR("DMA cross 2K boundary\n", TC_3000_500_IR_DMA2K); 215 PRINTINTR("TC reset in progress\n", TC_3000_500_IR_TCRESET); 216 PRINTINTR("TC parity error\n", TC_3000_500_IR_TCPAR); 217 PRINTINTR("DMA tag error\n", TC_3000_500_IR_DMATAG); 218 PRINTINTR("Single-bit error\n", TC_3000_500_IR_DMASBE); 219 PRINTINTR("Double-bit error\n", TC_3000_500_IR_DMADBE); 220 PRINTINTR("TC I/O timeout\n", TC_3000_500_IR_TCTIMEOUT); 221 PRINTINTR("DMA block too long\n", TC_3000_500_IR_DMABLOCK); 222 PRINTINTR("Invalid I/O address\n", TC_3000_500_IR_IOADDR); 223 PRINTINTR("DMA scatter/gather invalid\n", TC_3000_500_IR_DMASG); 224 PRINTINTR("Scatter/gather parity error\n", 225 TC_3000_500_IR_SGPAR); 226 #undef PRINTINTR 227 #endif 228 } while (ifound); 229 } 230 231 int 232 tc_3000_500_getdev(ca) 233 struct confargs *ca; 234 { 235 int i; 236 237 for (i = 0; i < TC_3000_500_MAXDEVS; i++) 238 if (ca->ca_slot == dec_3000_500_devs[i].ca_slot && 239 ca->ca_offset == dec_3000_500_devs[i].ca_offset && 240 !strncmp(ca->ca_name, dec_3000_500_devs[i].ca_name)) 241 return (i); 242 243 return (-1); 244 } 245 246 /* 247 * tc_3000_500_ioslot -- 248 * Set the PBS bits for devices on the TC. 249 */ 250 void 251 tc_3000_500_ioslot(slot, flags, set) 252 u_int32_t slot, flags; 253 int set; 254 { 255 volatile u_int32_t *iosp; 256 u_int32_t ios; 257 int s; 258 259 iosp = (volatile u_int32_t *)TC_3000_500_IOSLOT; 260 ios = *iosp; 261 flags <<= (slot * 3); 262 if (set) 263 ios |= flags; 264 else 265 ios &= ~flags; 266 s = splhigh(); 267 *iosp = ios; 268 MB(); 269 splx(s); 270 } 271
Indexes created Thu Oct 02 10:09:58 GMT 2025