tc_3000_500.c revision 1.16
1 /* $NetBSD: tc_3000_500.c,v 1.16 1998/10/22 01:03:09 briggs Exp $ */ 2 3 /* 4 * Copyright (c) 1994, 1995, 1996 Carnegie-Mellon University. 5 * All rights reserved. 6 * 7 * Author: Chris G. Demetriou 8 * 9 * Permission to use, copy, modify and distribute this software and 10 * its documentation is hereby granted, provided that both the copyright 11 * notice and this permission notice appear in all copies of the 12 * software, derivative works or modified versions, and any portions 13 * thereof, and that both notices appear in supporting documentation. 14 * 15 * CARNEGIE MELLON ALLOWS FREE USE OF THIS SOFTWARE IN ITS "AS IS" 16 * CONDITION. CARNEGIE MELLON DISCLAIMS ANY LIABILITY OF ANY KIND 17 * FOR ANY DAMAGES WHATSOEVER RESULTING FROM THE USE OF THIS SOFTWARE. 18 * 19 * Carnegie Mellon requests users of this software to return to 20 * 21 * Software Distribution Coordinator or Software.Distribution (at) CS.CMU.EDU 22 * School of Computer Science 23 * Carnegie Mellon University 24 * Pittsburgh PA 15213-3890 25 * 26 * any improvements or extensions that they make and grant Carnegie the 27 * rights to redistribute these changes. 28 */ 29 30 #include <sys/cdefs.h> /* RCS ID & Copyright macro defns */ 31 32 __KERNEL_RCSID(0, "$NetBSD: tc_3000_500.c,v 1.16 1998/10/22 01:03:09 briggs Exp $"); 33 34 #include <sys/param.h> 35 #include <sys/systm.h> 36 #include <sys/device.h> 37 38 #include <machine/autoconf.h> 39 #include <machine/pte.h> 40 #include <machine/rpb.h> 41 #ifndef EVCNT_COUNTERS 42 #include <machine/intrcnt.h> 43 #endif 44 45 #include <dev/tc/tcvar.h> 46 #include <alpha/tc/tc_conf.h> 47 #include <alpha/tc/tc_3000_500.h> 48 #include <alpha/tc/sfbvar.h> 49 50 void tc_3000_500_intr_setup __P((void)); 51 void tc_3000_500_intr_establish __P((struct device *, void *, 52 tc_intrlevel_t, int (*)(void *), void *)); 53 void tc_3000_500_intr_disestablish __P((struct device *, void *)); 54 void tc_3000_500_iointr __P((void *, unsigned long)); 55 56 int tc_3000_500_intrnull __P((void *)); 57 int tc_3000_500_fb_cnattach __P((u_int64_t)); 58 59 #define C(x) ((void *)(u_long)x) 60 #define KV(x) (ALPHA_PHYS_TO_K0SEG(x)) 61 62 struct tc_slotdesc tc_3000_500_slots[] = { 63 { KV(0x100000000), C(TC_3000_500_DEV_OPT0), }, /* 0 - opt slot 0 */ 64 { KV(0x120000000), C(TC_3000_500_DEV_OPT1), }, /* 1 - opt slot 1 */ 65 { KV(0x140000000), C(TC_3000_500_DEV_OPT2), }, /* 2 - opt slot 2 */ 66 { KV(0x160000000), C(TC_3000_500_DEV_OPT3), }, /* 3 - opt slot 3 */ 67 { KV(0x180000000), C(TC_3000_500_DEV_OPT4), }, /* 4 - opt slot 4 */ 68 { KV(0x1a0000000), C(TC_3000_500_DEV_OPT5), }, /* 5 - opt slot 5 */ 69 { KV(0x1c0000000), C(TC_3000_500_DEV_BOGUS), }, /* 6 - TCDS ASIC */ 70 { KV(0x1e0000000), C(TC_3000_500_DEV_BOGUS), }, /* 7 - IOCTL ASIC */ 71 }; 72 int tc_3000_500_nslots = 73 sizeof(tc_3000_500_slots) / sizeof(tc_3000_500_slots[0]); 74 75 struct tc_builtin tc_3000_500_graphics_builtins[] = { 76 { "FLAMG-IO", 7, 0x00000000, C(TC_3000_500_DEV_IOASIC), }, 77 { "PMAGB-BA", 7, 0x02000000, C(TC_3000_500_DEV_CXTURBO), }, 78 { "PMAZ-DS ", 6, 0x00000000, C(TC_3000_500_DEV_TCDS), }, 79 }; 80 int tc_3000_500_graphics_nbuiltins = sizeof(tc_3000_500_graphics_builtins) / 81 sizeof(tc_3000_500_graphics_builtins[0]); 82 83 struct tc_builtin tc_3000_500_nographics_builtins[] = { 84 { "FLAMG-IO", 7, 0x00000000, C(TC_3000_500_DEV_IOASIC), }, 85 { "PMAZ-DS ", 6, 0x00000000, C(TC_3000_500_DEV_TCDS), }, 86 }; 87 int tc_3000_500_nographics_nbuiltins = sizeof(tc_3000_500_nographics_builtins) / 88 sizeof(tc_3000_500_nographics_builtins[0]); 89 90 u_int32_t tc_3000_500_intrbits[TC_3000_500_NCOOKIES] = { 91 TC_3000_500_IR_OPT0, 92 TC_3000_500_IR_OPT1, 93 TC_3000_500_IR_OPT2, 94 TC_3000_500_IR_OPT3, 95 TC_3000_500_IR_OPT4, 96 TC_3000_500_IR_OPT5, 97 TC_3000_500_IR_TCDS, 98 TC_3000_500_IR_IOASIC, 99 TC_3000_500_IR_CXTURBO, 100 }; 101 102 struct tcintr { 103 int (*tci_func) __P((void *)); 104 void *tci_arg; 105 } tc_3000_500_intr[TC_3000_500_NCOOKIES]; 106 107 u_int32_t tc_3000_500_imask; /* intrs we want to ignore; mirrors IMR. */ 108 109 void 110 tc_3000_500_intr_setup() 111 { 112 u_long i; 113 114 /* 115 * Disable all slot interrupts. Note that this cannot 116 * actually disable CXTurbo, TCDS, and IOASIC interrupts. 117 */ 118 tc_3000_500_imask = *(volatile u_int32_t *)TC_3000_500_IMR_READ; 119 for (i = 0; i < TC_3000_500_NCOOKIES; i++) 120 tc_3000_500_imask |= tc_3000_500_intrbits[i]; 121 *(volatile u_int32_t *)TC_3000_500_IMR_WRITE = tc_3000_500_imask; 122 tc_mb(); 123 124 /* 125 * Set up interrupt handlers. 126 */ 127 for (i = 0; i < TC_3000_500_NCOOKIES; i++) { 128 tc_3000_500_intr[i].tci_func = tc_3000_500_intrnull; 129 tc_3000_500_intr[i].tci_arg = (void *)i; 130 } 131 } 132 133 void 134 tc_3000_500_intr_establish(tcadev, cookie, level, func, arg) 135 struct device *tcadev; 136 void *cookie, *arg; 137 tc_intrlevel_t level; 138 int (*func) __P((void *)); 139 { 140 u_long dev = (u_long)cookie; 141 142 #ifdef DIAGNOSTIC 143 /* XXX bounds-check cookie. */ 144 #endif 145 146 if (tc_3000_500_intr[dev].tci_func != tc_3000_500_intrnull) 147 panic("tc_3000_500_intr_establish: cookie %d twice", dev); 148 149 tc_3000_500_intr[dev].tci_func = func; 150 tc_3000_500_intr[dev].tci_arg = arg; 151 152 tc_3000_500_imask &= ~tc_3000_500_intrbits[dev]; 153 *(volatile u_int32_t *)TC_3000_500_IMR_WRITE = tc_3000_500_imask; 154 tc_mb(); 155 } 156 157 void 158 tc_3000_500_intr_disestablish(tcadev, cookie) 159 struct device *tcadev; 160 void *cookie; 161 { 162 u_long dev = (u_long)cookie; 163 164 #ifdef DIAGNOSTIC 165 /* XXX bounds-check cookie. */ 166 #endif 167 168 if (tc_3000_500_intr[dev].tci_func == tc_3000_500_intrnull) 169 panic("tc_3000_500_intr_disestablish: cookie %d bad intr", 170 dev); 171 172 tc_3000_500_imask |= tc_3000_500_intrbits[dev]; 173 *(volatile u_int32_t *)TC_3000_500_IMR_WRITE = tc_3000_500_imask; 174 tc_mb(); 175 176 tc_3000_500_intr[dev].tci_func = tc_3000_500_intrnull; 177 tc_3000_500_intr[dev].tci_arg = (void *)dev; 178 } 179 180 int 181 tc_3000_500_intrnull(val) 182 void *val; 183 { 184 185 panic("tc_3000_500_intrnull: uncaught TC intr for cookie %ld\n", 186 (u_long)val); 187 } 188 189 void 190 tc_3000_500_iointr(framep, vec) 191 void *framep; 192 unsigned long vec; 193 { 194 u_int32_t ir; 195 int ifound; 196 197 #ifdef DIAGNOSTIC 198 int s; 199 if (vec != 0x800) 200 panic("INVALID ASSUMPTION: vec 0x%lx, not 0x800", vec); 201 s = splhigh(); 202 if (s != ALPHA_PSL_IPL_IO) 203 panic("INVALID ASSUMPTION: IPL %d, not %d", s, 204 ALPHA_PSL_IPL_IO); 205 splx(s); 206 #endif 207 208 do { 209 tc_syncbus(); 210 ir = *(volatile u_int32_t *)TC_3000_500_IR_CLEAR; 211 212 /* Ignore interrupts that we haven't enabled. */ 213 ir &= ~(tc_3000_500_imask & 0x1ff); 214 215 ifound = 0; 216 217 #ifdef EVCNT_COUNTERS 218 /* No interrupt counting via evcnt counters */ 219 XXX BREAK HERE XXX 220 #else /* !EVCNT_COUNTERS */ 221 #define INCRINTRCNT(slot) intrcnt[INTRCNT_KN15 + slot]++ 222 #endif /* EVCNT_COUNTERS */ 223 224 #define CHECKINTR(slot) \ 225 if (ir & tc_3000_500_intrbits[slot]) { \ 226 ifound = 1; \ 227 INCRINTRCNT(slot); \ 228 (*tc_3000_500_intr[slot].tci_func) \ 229 (tc_3000_500_intr[slot].tci_arg); \ 230 } 231 /* Do them in order of priority; highest slot # first. */ 232 CHECKINTR(TC_3000_500_DEV_CXTURBO); 233 CHECKINTR(TC_3000_500_DEV_IOASIC); 234 CHECKINTR(TC_3000_500_DEV_TCDS); 235 CHECKINTR(TC_3000_500_DEV_OPT5); 236 CHECKINTR(TC_3000_500_DEV_OPT4); 237 CHECKINTR(TC_3000_500_DEV_OPT3); 238 CHECKINTR(TC_3000_500_DEV_OPT2); 239 CHECKINTR(TC_3000_500_DEV_OPT1); 240 CHECKINTR(TC_3000_500_DEV_OPT0); 241 #undef CHECKINTR 242 243 #ifdef DIAGNOSTIC 244 #define PRINTINTR(msg, bits) \ 245 if (ir & bits) \ 246 printf(msg); 247 PRINTINTR("Second error occurred\n", TC_3000_500_IR_ERR2); 248 PRINTINTR("DMA buffer error\n", TC_3000_500_IR_DMABE); 249 PRINTINTR("DMA cross 2K boundary\n", TC_3000_500_IR_DMA2K); 250 PRINTINTR("TC reset in progress\n", TC_3000_500_IR_TCRESET); 251 PRINTINTR("TC parity error\n", TC_3000_500_IR_TCPAR); 252 PRINTINTR("DMA tag error\n", TC_3000_500_IR_DMATAG); 253 PRINTINTR("Single-bit error\n", TC_3000_500_IR_DMASBE); 254 PRINTINTR("Double-bit error\n", TC_3000_500_IR_DMADBE); 255 PRINTINTR("TC I/O timeout\n", TC_3000_500_IR_TCTIMEOUT); 256 PRINTINTR("DMA block too long\n", TC_3000_500_IR_DMABLOCK); 257 PRINTINTR("Invalid I/O address\n", TC_3000_500_IR_IOADDR); 258 PRINTINTR("DMA scatter/gather invalid\n", TC_3000_500_IR_DMASG); 259 PRINTINTR("Scatter/gather parity error\n", 260 TC_3000_500_IR_SGPAR); 261 #undef PRINTINTR 262 #endif 263 } while (ifound); 264 } 265 266 /* 267 * tc_3000_500_fb_cnattach -- 268 * Attempt to map the CTB output device to a slot and attach the 269 * framebuffer as the output side of the console. 270 */ 271 int 272 tc_3000_500_fb_cnattach(turbo_slot) 273 u_int64_t turbo_slot; 274 { 275 u_int32_t output_slot; 276 277 output_slot = turbo_slot & 0xffffffff; 278 279 if (output_slot >= tc_3000_500_nslots) { 280 return 0; 281 } 282 283 if (hwrpb->rpb_variation & SV_GRAPHICS) { 284 if (output_slot == 0) { 285 sfb_cnattach(KV(0x1e0000000) + 0x02000000); 286 return 1; 287 } 288 } else { 289 /* 290 * Slots 0-2 in the tc_3000_500_slots array are only 291 * on the 500 models that also have the CXTurbo 292 * (500/800/900) and a total of 6 TC slots. For the 293 * 400/600/700, slots 0-2 are in table locations 3-5, so 294 * offset the CTB slot by 3 to get the address in our table. 295 */ 296 output_slot += 3; 297 } 298 return tc_fb_cnattach(tc_3000_500_slots[output_slot-1].tcs_addr); 299 } 300 301 #if 0 302 /* 303 * tc_3000_500_ioslot -- 304 * Set the PBS bits for devices on the TC. 305 */ 306 void 307 tc_3000_500_ioslot(slot, flags, set) 308 u_int32_t slot, flags; 309 int set; 310 { 311 volatile u_int32_t *iosp; 312 u_int32_t ios; 313 int s; 314 315 iosp = (volatile u_int32_t *)TC_3000_500_IOSLOT; 316 ios = *iosp; 317 flags <<= (slot * 3); 318 if (set) 319 ios |= flags; 320 else 321 ios &= ~flags; 322 s = splhigh(); 323 *iosp = ios; 324 tc_mb(); 325 splx(s); 326 } 327 #endif 328
Indexes created Thu Oct 02 10:09:58 GMT 2025