tc_3000_500.c revision 1.17
1 /* $NetBSD: tc_3000_500.c,v 1.17 1998/10/23 23:49:31 briggs Exp $ */ 2 3 /* 4 * Copyright (c) 1994, 1995, 1996 Carnegie-Mellon University. 5 * All rights reserved. 6 * 7 * Author: Chris G. Demetriou 8 * 9 * Permission to use, copy, modify and distribute this software and 10 * its documentation is hereby granted, provided that both the copyright 11 * notice and this permission notice appear in all copies of the 12 * software, derivative works or modified versions, and any portions 13 * thereof, and that both notices appear in supporting documentation. 14 * 15 * CARNEGIE MELLON ALLOWS FREE USE OF THIS SOFTWARE IN ITS "AS IS" 16 * CONDITION. CARNEGIE MELLON DISCLAIMS ANY LIABILITY OF ANY KIND 17 * FOR ANY DAMAGES WHATSOEVER RESULTING FROM THE USE OF THIS SOFTWARE. 18 * 19 * Carnegie Mellon requests users of this software to return to 20 * 21 * Software Distribution Coordinator or Software.Distribution (at) CS.CMU.EDU 22 * School of Computer Science 23 * Carnegie Mellon University 24 * Pittsburgh PA 15213-3890 25 * 26 * any improvements or extensions that they make and grant Carnegie the 27 * rights to redistribute these changes. 28 */ 29 30 #include <sys/cdefs.h> /* RCS ID & Copyright macro defns */ 31 32 __KERNEL_RCSID(0, "$NetBSD: tc_3000_500.c,v 1.17 1998/10/23 23:49:31 briggs Exp $"); 33 34 #include <sys/param.h> 35 #include <sys/systm.h> 36 #include <sys/device.h> 37 38 #include <machine/autoconf.h> 39 #include <machine/pte.h> 40 #include <machine/rpb.h> 41 #ifndef EVCNT_COUNTERS 42 #include <machine/intrcnt.h> 43 #endif 44 45 #include <dev/tc/tcvar.h> 46 #include <alpha/tc/tc_conf.h> 47 #include <alpha/tc/tc_3000_500.h> 48 49 #include "sfb.h" 50 51 #if NSFB > 0 52 #include <alpha/tc/sfbvar.h> 53 #endif 54 55 void tc_3000_500_intr_setup __P((void)); 56 void tc_3000_500_intr_establish __P((struct device *, void *, 57 tc_intrlevel_t, int (*)(void *), void *)); 58 void tc_3000_500_intr_disestablish __P((struct device *, void *)); 59 void tc_3000_500_iointr __P((void *, unsigned long)); 60 61 int tc_3000_500_intrnull __P((void *)); 62 int tc_3000_500_fb_cnattach __P((u_int64_t)); 63 64 #define C(x) ((void *)(u_long)x) 65 #define KV(x) (ALPHA_PHYS_TO_K0SEG(x)) 66 67 struct tc_slotdesc tc_3000_500_slots[] = { 68 { KV(0x100000000), C(TC_3000_500_DEV_OPT0), }, /* 0 - opt slot 0 */ 69 { KV(0x120000000), C(TC_3000_500_DEV_OPT1), }, /* 1 - opt slot 1 */ 70 { KV(0x140000000), C(TC_3000_500_DEV_OPT2), }, /* 2 - opt slot 2 */ 71 { KV(0x160000000), C(TC_3000_500_DEV_OPT3), }, /* 3 - opt slot 3 */ 72 { KV(0x180000000), C(TC_3000_500_DEV_OPT4), }, /* 4 - opt slot 4 */ 73 { KV(0x1a0000000), C(TC_3000_500_DEV_OPT5), }, /* 5 - opt slot 5 */ 74 { KV(0x1c0000000), C(TC_3000_500_DEV_BOGUS), }, /* 6 - TCDS ASIC */ 75 { KV(0x1e0000000), C(TC_3000_500_DEV_BOGUS), }, /* 7 - IOCTL ASIC */ 76 }; 77 int tc_3000_500_nslots = 78 sizeof(tc_3000_500_slots) / sizeof(tc_3000_500_slots[0]); 79 80 struct tc_builtin tc_3000_500_graphics_builtins[] = { 81 { "FLAMG-IO", 7, 0x00000000, C(TC_3000_500_DEV_IOASIC), }, 82 { "PMAGB-BA", 7, 0x02000000, C(TC_3000_500_DEV_CXTURBO), }, 83 { "PMAZ-DS ", 6, 0x00000000, C(TC_3000_500_DEV_TCDS), }, 84 }; 85 int tc_3000_500_graphics_nbuiltins = sizeof(tc_3000_500_graphics_builtins) / 86 sizeof(tc_3000_500_graphics_builtins[0]); 87 88 struct tc_builtin tc_3000_500_nographics_builtins[] = { 89 { "FLAMG-IO", 7, 0x00000000, C(TC_3000_500_DEV_IOASIC), }, 90 { "PMAZ-DS ", 6, 0x00000000, C(TC_3000_500_DEV_TCDS), }, 91 }; 92 int tc_3000_500_nographics_nbuiltins = sizeof(tc_3000_500_nographics_builtins) / 93 sizeof(tc_3000_500_nographics_builtins[0]); 94 95 u_int32_t tc_3000_500_intrbits[TC_3000_500_NCOOKIES] = { 96 TC_3000_500_IR_OPT0, 97 TC_3000_500_IR_OPT1, 98 TC_3000_500_IR_OPT2, 99 TC_3000_500_IR_OPT3, 100 TC_3000_500_IR_OPT4, 101 TC_3000_500_IR_OPT5, 102 TC_3000_500_IR_TCDS, 103 TC_3000_500_IR_IOASIC, 104 TC_3000_500_IR_CXTURBO, 105 }; 106 107 struct tcintr { 108 int (*tci_func) __P((void *)); 109 void *tci_arg; 110 } tc_3000_500_intr[TC_3000_500_NCOOKIES]; 111 112 u_int32_t tc_3000_500_imask; /* intrs we want to ignore; mirrors IMR. */ 113 114 void 115 tc_3000_500_intr_setup() 116 { 117 u_long i; 118 119 /* 120 * Disable all slot interrupts. Note that this cannot 121 * actually disable CXTurbo, TCDS, and IOASIC interrupts. 122 */ 123 tc_3000_500_imask = *(volatile u_int32_t *)TC_3000_500_IMR_READ; 124 for (i = 0; i < TC_3000_500_NCOOKIES; i++) 125 tc_3000_500_imask |= tc_3000_500_intrbits[i]; 126 *(volatile u_int32_t *)TC_3000_500_IMR_WRITE = tc_3000_500_imask; 127 tc_mb(); 128 129 /* 130 * Set up interrupt handlers. 131 */ 132 for (i = 0; i < TC_3000_500_NCOOKIES; i++) { 133 tc_3000_500_intr[i].tci_func = tc_3000_500_intrnull; 134 tc_3000_500_intr[i].tci_arg = (void *)i; 135 } 136 } 137 138 void 139 tc_3000_500_intr_establish(tcadev, cookie, level, func, arg) 140 struct device *tcadev; 141 void *cookie, *arg; 142 tc_intrlevel_t level; 143 int (*func) __P((void *)); 144 { 145 u_long dev = (u_long)cookie; 146 147 #ifdef DIAGNOSTIC 148 /* XXX bounds-check cookie. */ 149 #endif 150 151 if (tc_3000_500_intr[dev].tci_func != tc_3000_500_intrnull) 152 panic("tc_3000_500_intr_establish: cookie %d twice", dev); 153 154 tc_3000_500_intr[dev].tci_func = func; 155 tc_3000_500_intr[dev].tci_arg = arg; 156 157 tc_3000_500_imask &= ~tc_3000_500_intrbits[dev]; 158 *(volatile u_int32_t *)TC_3000_500_IMR_WRITE = tc_3000_500_imask; 159 tc_mb(); 160 } 161 162 void 163 tc_3000_500_intr_disestablish(tcadev, cookie) 164 struct device *tcadev; 165 void *cookie; 166 { 167 u_long dev = (u_long)cookie; 168 169 #ifdef DIAGNOSTIC 170 /* XXX bounds-check cookie. */ 171 #endif 172 173 if (tc_3000_500_intr[dev].tci_func == tc_3000_500_intrnull) 174 panic("tc_3000_500_intr_disestablish: cookie %d bad intr", 175 dev); 176 177 tc_3000_500_imask |= tc_3000_500_intrbits[dev]; 178 *(volatile u_int32_t *)TC_3000_500_IMR_WRITE = tc_3000_500_imask; 179 tc_mb(); 180 181 tc_3000_500_intr[dev].tci_func = tc_3000_500_intrnull; 182 tc_3000_500_intr[dev].tci_arg = (void *)dev; 183 } 184 185 int 186 tc_3000_500_intrnull(val) 187 void *val; 188 { 189 190 panic("tc_3000_500_intrnull: uncaught TC intr for cookie %ld\n", 191 (u_long)val); 192 } 193 194 void 195 tc_3000_500_iointr(framep, vec) 196 void *framep; 197 unsigned long vec; 198 { 199 u_int32_t ir; 200 int ifound; 201 202 #ifdef DIAGNOSTIC 203 int s; 204 if (vec != 0x800) 205 panic("INVALID ASSUMPTION: vec 0x%lx, not 0x800", vec); 206 s = splhigh(); 207 if (s != ALPHA_PSL_IPL_IO) 208 panic("INVALID ASSUMPTION: IPL %d, not %d", s, 209 ALPHA_PSL_IPL_IO); 210 splx(s); 211 #endif 212 213 do { 214 tc_syncbus(); 215 ir = *(volatile u_int32_t *)TC_3000_500_IR_CLEAR; 216 217 /* Ignore interrupts that we haven't enabled. */ 218 ir &= ~(tc_3000_500_imask & 0x1ff); 219 220 ifound = 0; 221 222 #ifdef EVCNT_COUNTERS 223 /* No interrupt counting via evcnt counters */ 224 XXX BREAK HERE XXX 225 #else /* !EVCNT_COUNTERS */ 226 #define INCRINTRCNT(slot) intrcnt[INTRCNT_KN15 + slot]++ 227 #endif /* EVCNT_COUNTERS */ 228 229 #define CHECKINTR(slot) \ 230 if (ir & tc_3000_500_intrbits[slot]) { \ 231 ifound = 1; \ 232 INCRINTRCNT(slot); \ 233 (*tc_3000_500_intr[slot].tci_func) \ 234 (tc_3000_500_intr[slot].tci_arg); \ 235 } 236 /* Do them in order of priority; highest slot # first. */ 237 CHECKINTR(TC_3000_500_DEV_CXTURBO); 238 CHECKINTR(TC_3000_500_DEV_IOASIC); 239 CHECKINTR(TC_3000_500_DEV_TCDS); 240 CHECKINTR(TC_3000_500_DEV_OPT5); 241 CHECKINTR(TC_3000_500_DEV_OPT4); 242 CHECKINTR(TC_3000_500_DEV_OPT3); 243 CHECKINTR(TC_3000_500_DEV_OPT2); 244 CHECKINTR(TC_3000_500_DEV_OPT1); 245 CHECKINTR(TC_3000_500_DEV_OPT0); 246 #undef CHECKINTR 247 248 #ifdef DIAGNOSTIC 249 #define PRINTINTR(msg, bits) \ 250 if (ir & bits) \ 251 printf(msg); 252 PRINTINTR("Second error occurred\n", TC_3000_500_IR_ERR2); 253 PRINTINTR("DMA buffer error\n", TC_3000_500_IR_DMABE); 254 PRINTINTR("DMA cross 2K boundary\n", TC_3000_500_IR_DMA2K); 255 PRINTINTR("TC reset in progress\n", TC_3000_500_IR_TCRESET); 256 PRINTINTR("TC parity error\n", TC_3000_500_IR_TCPAR); 257 PRINTINTR("DMA tag error\n", TC_3000_500_IR_DMATAG); 258 PRINTINTR("Single-bit error\n", TC_3000_500_IR_DMASBE); 259 PRINTINTR("Double-bit error\n", TC_3000_500_IR_DMADBE); 260 PRINTINTR("TC I/O timeout\n", TC_3000_500_IR_TCTIMEOUT); 261 PRINTINTR("DMA block too long\n", TC_3000_500_IR_DMABLOCK); 262 PRINTINTR("Invalid I/O address\n", TC_3000_500_IR_IOADDR); 263 PRINTINTR("DMA scatter/gather invalid\n", TC_3000_500_IR_DMASG); 264 PRINTINTR("Scatter/gather parity error\n", 265 TC_3000_500_IR_SGPAR); 266 #undef PRINTINTR 267 #endif 268 } while (ifound); 269 } 270 271 /* 272 * tc_3000_500_fb_cnattach -- 273 * Attempt to map the CTB output device to a slot and attach the 274 * framebuffer as the output side of the console. 275 */ 276 int 277 tc_3000_500_fb_cnattach(turbo_slot) 278 u_int64_t turbo_slot; 279 { 280 u_int32_t output_slot; 281 282 output_slot = turbo_slot & 0xffffffff; 283 284 if (output_slot >= tc_3000_500_nslots) { 285 return 0; 286 } 287 288 if (hwrpb->rpb_variation & SV_GRAPHICS) { 289 if (output_slot == 0) { 290 #if NSFB > 0 291 sfb_cnattach(KV(0x1e0000000) + 0x02000000); 292 return 1; 293 #else 294 return 0; 295 #endif 296 } 297 } else { 298 /* 299 * Slots 0-2 in the tc_3000_500_slots array are only 300 * on the 500 models that also have the CXTurbo 301 * (500/800/900) and a total of 6 TC slots. For the 302 * 400/600/700, slots 0-2 are in table locations 3-5, so 303 * offset the CTB slot by 3 to get the address in our table. 304 */ 305 output_slot += 3; 306 } 307 return tc_fb_cnattach(tc_3000_500_slots[output_slot-1].tcs_addr); 308 } 309 310 #if 0 311 /* 312 * tc_3000_500_ioslot -- 313 * Set the PBS bits for devices on the TC. 314 */ 315 void 316 tc_3000_500_ioslot(slot, flags, set) 317 u_int32_t slot, flags; 318 int set; 319 { 320 volatile u_int32_t *iosp; 321 u_int32_t ios; 322 int s; 323 324 iosp = (volatile u_int32_t *)TC_3000_500_IOSLOT; 325 ios = *iosp; 326 flags <<= (slot * 3); 327 if (set) 328 ios |= flags; 329 else 330 ios &= ~flags; 331 s = splhigh(); 332 *iosp = ios; 333 tc_mb(); 334 splx(s); 335 } 336 #endif 337
Indexes created Thu Oct 02 10:09:58 GMT 2025