tc_3000_500.c revision 1.20
1 /* $NetBSD: tc_3000_500.c,v 1.20 1999/08/07 12:58:29 drochner Exp $ */ 2 3 /* 4 * Copyright (c) 1994, 1995, 1996 Carnegie-Mellon University. 5 * All rights reserved. 6 * 7 * Author: Chris G. Demetriou 8 * 9 * Permission to use, copy, modify and distribute this software and 10 * its documentation is hereby granted, provided that both the copyright 11 * notice and this permission notice appear in all copies of the 12 * software, derivative works or modified versions, and any portions 13 * thereof, and that both notices appear in supporting documentation. 14 * 15 * CARNEGIE MELLON ALLOWS FREE USE OF THIS SOFTWARE IN ITS "AS IS" 16 * CONDITION. CARNEGIE MELLON DISCLAIMS ANY LIABILITY OF ANY KIND 17 * FOR ANY DAMAGES WHATSOEVER RESULTING FROM THE USE OF THIS SOFTWARE. 18 * 19 * Carnegie Mellon requests users of this software to return to 20 * 21 * Software Distribution Coordinator or Software.Distribution (at) CS.CMU.EDU 22 * School of Computer Science 23 * Carnegie Mellon University 24 * Pittsburgh PA 15213-3890 25 * 26 * any improvements or extensions that they make and grant Carnegie the 27 * rights to redistribute these changes. 28 */ 29 30 #include <sys/cdefs.h> /* RCS ID & Copyright macro defns */ 31 32 __KERNEL_RCSID(0, "$NetBSD: tc_3000_500.c,v 1.20 1999/08/07 12:58:29 drochner Exp $"); 33 34 #include <sys/param.h> 35 #include <sys/systm.h> 36 #include <sys/device.h> 37 38 #include <machine/autoconf.h> 39 #include <machine/pte.h> 40 #include <machine/rpb.h> 41 #ifndef EVCNT_COUNTERS 42 #include <machine/intrcnt.h> 43 #endif 44 45 #include <dev/tc/tcvar.h> 46 #include <alpha/tc/tc_conf.h> 47 #include <alpha/tc/tc_3000_500.h> 48 49 #include "wsdisplay.h" 50 #include "sfb.h" 51 52 #if NSFB > 0 53 #include <alpha/tc/sfbvar.h> 54 #endif 55 56 void tc_3000_500_intr_setup __P((void)); 57 void tc_3000_500_intr_establish __P((struct device *, void *, 58 tc_intrlevel_t, int (*)(void *), void *)); 59 void tc_3000_500_intr_disestablish __P((struct device *, void *)); 60 void tc_3000_500_iointr __P((void *, unsigned long)); 61 62 int tc_3000_500_intrnull __P((void *)); 63 int tc_3000_500_fb_cnattach __P((u_int64_t)); 64 65 #define C(x) ((void *)(u_long)x) 66 #define KV(x) (ALPHA_PHYS_TO_K0SEG(x)) 67 68 struct tc_slotdesc tc_3000_500_slots[] = { 69 { KV(0x100000000), C(TC_3000_500_DEV_OPT0), }, /* 0 - opt slot 0 */ 70 { KV(0x120000000), C(TC_3000_500_DEV_OPT1), }, /* 1 - opt slot 1 */ 71 { KV(0x140000000), C(TC_3000_500_DEV_OPT2), }, /* 2 - opt slot 2 */ 72 { KV(0x160000000), C(TC_3000_500_DEV_OPT3), }, /* 3 - opt slot 3 */ 73 { KV(0x180000000), C(TC_3000_500_DEV_OPT4), }, /* 4 - opt slot 4 */ 74 { KV(0x1a0000000), C(TC_3000_500_DEV_OPT5), }, /* 5 - opt slot 5 */ 75 { KV(0x1c0000000), C(TC_3000_500_DEV_BOGUS), }, /* 6 - TCDS ASIC */ 76 { KV(0x1e0000000), C(TC_3000_500_DEV_BOGUS), }, /* 7 - IOCTL ASIC */ 77 }; 78 int tc_3000_500_nslots = 79 sizeof(tc_3000_500_slots) / sizeof(tc_3000_500_slots[0]); 80 81 struct tc_builtin tc_3000_500_graphics_builtins[] = { 82 { "FLAMG-IO", 7, 0x00000000, C(TC_3000_500_DEV_IOASIC), }, 83 { "PMAGB-BA", 7, 0x02000000, C(TC_3000_500_DEV_CXTURBO), }, 84 { "PMAZ-DS ", 6, 0x00000000, C(TC_3000_500_DEV_TCDS), }, 85 }; 86 int tc_3000_500_graphics_nbuiltins = sizeof(tc_3000_500_graphics_builtins) / 87 sizeof(tc_3000_500_graphics_builtins[0]); 88 89 struct tc_builtin tc_3000_500_nographics_builtins[] = { 90 { "FLAMG-IO", 7, 0x00000000, C(TC_3000_500_DEV_IOASIC), }, 91 { "PMAZ-DS ", 6, 0x00000000, C(TC_3000_500_DEV_TCDS), }, 92 }; 93 int tc_3000_500_nographics_nbuiltins = sizeof(tc_3000_500_nographics_builtins) / 94 sizeof(tc_3000_500_nographics_builtins[0]); 95 96 u_int32_t tc_3000_500_intrbits[TC_3000_500_NCOOKIES] = { 97 TC_3000_500_IR_OPT0, 98 TC_3000_500_IR_OPT1, 99 TC_3000_500_IR_OPT2, 100 TC_3000_500_IR_OPT3, 101 TC_3000_500_IR_OPT4, 102 TC_3000_500_IR_OPT5, 103 TC_3000_500_IR_TCDS, 104 TC_3000_500_IR_IOASIC, 105 TC_3000_500_IR_CXTURBO, 106 }; 107 108 struct tcintr { 109 int (*tci_func) __P((void *)); 110 void *tci_arg; 111 } tc_3000_500_intr[TC_3000_500_NCOOKIES]; 112 113 u_int32_t tc_3000_500_imask; /* intrs we want to ignore; mirrors IMR. */ 114 115 void 116 tc_3000_500_intr_setup() 117 { 118 u_long i; 119 120 /* 121 * Disable all slot interrupts. Note that this cannot 122 * actually disable CXTurbo, TCDS, and IOASIC interrupts. 123 */ 124 tc_3000_500_imask = *(volatile u_int32_t *)TC_3000_500_IMR_READ; 125 for (i = 0; i < TC_3000_500_NCOOKIES; i++) 126 tc_3000_500_imask |= tc_3000_500_intrbits[i]; 127 *(volatile u_int32_t *)TC_3000_500_IMR_WRITE = tc_3000_500_imask; 128 tc_mb(); 129 130 /* 131 * Set up interrupt handlers. 132 */ 133 for (i = 0; i < TC_3000_500_NCOOKIES; i++) { 134 tc_3000_500_intr[i].tci_func = tc_3000_500_intrnull; 135 tc_3000_500_intr[i].tci_arg = (void *)i; 136 } 137 } 138 139 void 140 tc_3000_500_intr_establish(tcadev, cookie, level, func, arg) 141 struct device *tcadev; 142 void *cookie, *arg; 143 tc_intrlevel_t level; 144 int (*func) __P((void *)); 145 { 146 u_long dev = (u_long)cookie; 147 148 #ifdef DIAGNOSTIC 149 /* XXX bounds-check cookie. */ 150 #endif 151 152 if (tc_3000_500_intr[dev].tci_func != tc_3000_500_intrnull) 153 panic("tc_3000_500_intr_establish: cookie %lu twice", dev); 154 155 tc_3000_500_intr[dev].tci_func = func; 156 tc_3000_500_intr[dev].tci_arg = arg; 157 158 tc_3000_500_imask &= ~tc_3000_500_intrbits[dev]; 159 *(volatile u_int32_t *)TC_3000_500_IMR_WRITE = tc_3000_500_imask; 160 tc_mb(); 161 } 162 163 void 164 tc_3000_500_intr_disestablish(tcadev, cookie) 165 struct device *tcadev; 166 void *cookie; 167 { 168 u_long dev = (u_long)cookie; 169 170 #ifdef DIAGNOSTIC 171 /* XXX bounds-check cookie. */ 172 #endif 173 174 if (tc_3000_500_intr[dev].tci_func == tc_3000_500_intrnull) 175 panic("tc_3000_500_intr_disestablish: cookie %lu bad intr", 176 dev); 177 178 tc_3000_500_imask |= tc_3000_500_intrbits[dev]; 179 *(volatile u_int32_t *)TC_3000_500_IMR_WRITE = tc_3000_500_imask; 180 tc_mb(); 181 182 tc_3000_500_intr[dev].tci_func = tc_3000_500_intrnull; 183 tc_3000_500_intr[dev].tci_arg = (void *)dev; 184 } 185 186 int 187 tc_3000_500_intrnull(val) 188 void *val; 189 { 190 191 panic("tc_3000_500_intrnull: uncaught TC intr for cookie %ld\n", 192 (u_long)val); 193 } 194 195 void 196 tc_3000_500_iointr(framep, vec) 197 void *framep; 198 unsigned long vec; 199 { 200 u_int32_t ir; 201 int ifound; 202 203 #ifdef DIAGNOSTIC 204 int s; 205 if (vec != 0x800) 206 panic("INVALID ASSUMPTION: vec 0x%lx, not 0x800", vec); 207 s = splhigh(); 208 if (s != ALPHA_PSL_IPL_IO) 209 panic("INVALID ASSUMPTION: IPL %d, not %d", s, 210 ALPHA_PSL_IPL_IO); 211 splx(s); 212 #endif 213 214 do { 215 tc_syncbus(); 216 ir = *(volatile u_int32_t *)TC_3000_500_IR_CLEAR; 217 218 /* Ignore interrupts that we haven't enabled. */ 219 ir &= ~(tc_3000_500_imask & 0x1ff); 220 221 ifound = 0; 222 223 #ifdef EVCNT_COUNTERS 224 /* No interrupt counting via evcnt counters */ 225 XXX BREAK HERE XXX 226 #else /* !EVCNT_COUNTERS */ 227 #define INCRINTRCNT(slot) intrcnt[INTRCNT_KN15 + slot]++ 228 #endif /* EVCNT_COUNTERS */ 229 230 #define CHECKINTR(slot) \ 231 if (ir & tc_3000_500_intrbits[slot]) { \ 232 ifound = 1; \ 233 INCRINTRCNT(slot); \ 234 (*tc_3000_500_intr[slot].tci_func) \ 235 (tc_3000_500_intr[slot].tci_arg); \ 236 } 237 /* Do them in order of priority; highest slot # first. */ 238 CHECKINTR(TC_3000_500_DEV_CXTURBO); 239 CHECKINTR(TC_3000_500_DEV_IOASIC); 240 CHECKINTR(TC_3000_500_DEV_TCDS); 241 CHECKINTR(TC_3000_500_DEV_OPT5); 242 CHECKINTR(TC_3000_500_DEV_OPT4); 243 CHECKINTR(TC_3000_500_DEV_OPT3); 244 CHECKINTR(TC_3000_500_DEV_OPT2); 245 CHECKINTR(TC_3000_500_DEV_OPT1); 246 CHECKINTR(TC_3000_500_DEV_OPT0); 247 #undef CHECKINTR 248 249 #ifdef DIAGNOSTIC 250 #define PRINTINTR(msg, bits) \ 251 if (ir & bits) \ 252 printf(msg); 253 PRINTINTR("Second error occurred\n", TC_3000_500_IR_ERR2); 254 PRINTINTR("DMA buffer error\n", TC_3000_500_IR_DMABE); 255 PRINTINTR("DMA cross 2K boundary\n", TC_3000_500_IR_DMA2K); 256 PRINTINTR("TC reset in progress\n", TC_3000_500_IR_TCRESET); 257 PRINTINTR("TC parity error\n", TC_3000_500_IR_TCPAR); 258 PRINTINTR("DMA tag error\n", TC_3000_500_IR_DMATAG); 259 PRINTINTR("Single-bit error\n", TC_3000_500_IR_DMASBE); 260 PRINTINTR("Double-bit error\n", TC_3000_500_IR_DMADBE); 261 PRINTINTR("TC I/O timeout\n", TC_3000_500_IR_TCTIMEOUT); 262 PRINTINTR("DMA block too long\n", TC_3000_500_IR_DMABLOCK); 263 PRINTINTR("Invalid I/O address\n", TC_3000_500_IR_IOADDR); 264 PRINTINTR("DMA scatter/gather invalid\n", TC_3000_500_IR_DMASG); 265 PRINTINTR("Scatter/gather parity error\n", 266 TC_3000_500_IR_SGPAR); 267 #undef PRINTINTR 268 #endif 269 } while (ifound); 270 } 271 272 #if NWSDISPLAY > 0 273 /* 274 * tc_3000_500_fb_cnattach -- 275 * Attempt to map the CTB output device to a slot and attach the 276 * framebuffer as the output side of the console. 277 */ 278 int 279 tc_3000_500_fb_cnattach(turbo_slot) 280 u_int64_t turbo_slot; 281 { 282 u_int32_t output_slot; 283 284 output_slot = turbo_slot & 0xffffffff; 285 286 if (output_slot >= tc_3000_500_nslots) { 287 return EINVAL; 288 } 289 290 if (hwrpb->rpb_variation & SV_GRAPHICS) { 291 if (output_slot == 0) { 292 #if NSFB > 0 293 sfb_cnattach(KV(0x1e0000000) + 0x02000000); 294 return 0; 295 #else 296 return ENXIO; 297 #endif 298 } 299 } else { 300 /* 301 * Slots 0-2 in the tc_3000_500_slots array are only 302 * on the 500 models that also have the CXTurbo 303 * (500/800/900) and a total of 6 TC slots. For the 304 * 400/600/700, slots 0-2 are in table locations 3-5, so 305 * offset the CTB slot by 3 to get the address in our table. 306 */ 307 output_slot += 3; 308 } 309 return tc_fb_cnattach(tc_3000_500_slots[output_slot-1].tcs_addr); 310 } 311 #endif /* NWSDISPLAY */ 312 313 #if 0 314 /* 315 * tc_3000_500_ioslot -- 316 * Set the PBS bits for devices on the TC. 317 */ 318 void 319 tc_3000_500_ioslot(slot, flags, set) 320 u_int32_t slot, flags; 321 int set; 322 { 323 volatile u_int32_t *iosp; 324 u_int32_t ios; 325 int s; 326 327 iosp = (volatile u_int32_t *)TC_3000_500_IOSLOT; 328 ios = *iosp; 329 flags <<= (slot * 3); 330 if (set) 331 ios |= flags; 332 else 333 ios &= ~flags; 334 s = splhigh(); 335 *iosp = ios; 336 tc_mb(); 337 splx(s); 338 } 339 #endif 340
Indexes created Thu Oct 02 14:10:14 GMT 2025