tc_3000_500.c revision 1.3
1 /* $NetBSD: tc_3000_500.c,v 1.3 1995/12/20 00:43:30 cgd Exp $ */ 2 3 /* 4 * Copyright (c) 1994, 1995 Carnegie-Mellon University. 5 * All rights reserved. 6 * 7 * Author: Chris G. Demetriou 8 * 9 * Permission to use, copy, modify and distribute this software and 10 * its documentation is hereby granted, provided that both the copyright 11 * notice and this permission notice appear in all copies of the 12 * software, derivative works or modified versions, and any portions 13 * thereof, and that both notices appear in supporting documentation. 14 * 15 * CARNEGIE MELLON ALLOWS FREE USE OF THIS SOFTWARE IN ITS "AS IS" 16 * CONDITION. CARNEGIE MELLON DISCLAIMS ANY LIABILITY OF ANY KIND 17 * FOR ANY DAMAGES WHATSOEVER RESULTING FROM THE USE OF THIS SOFTWARE. 18 * 19 * Carnegie Mellon requests users of this software to return to 20 * 21 * Software Distribution Coordinator or Software.Distribution (at) CS.CMU.EDU 22 * School of Computer Science 23 * Carnegie Mellon University 24 * Pittsburgh PA 15213-3890 25 * 26 * any improvements or extensions that they make and grant Carnegie the 27 * rights to redistribute these changes. 28 */ 29 30 #include <sys/param.h> 31 #include <sys/device.h> 32 33 #include <machine/autoconf.h> 34 #include <machine/pte.h> 35 36 #include <dev/tc/tcvar.h> 37 #include <alpha/tc/tc_conf.h> 38 #include <alpha/tc/tc_3000_500.h> 39 40 void tc_3000_500_intr_setup __P((void)); 41 void tc_3000_500_intr_establish __P((struct device *, void *, 42 tc_intrlevel_t, int (*)(void *), void *)); 43 void tc_3000_500_intr_disestablish __P((struct device *, void *)); 44 void tc_3000_500_iointr __P((void *, int)); 45 46 int tc_3000_500_intrnull __P((void *)); 47 48 #define C(x) ((void *)(u_long)x) 49 #define KV(x) (phystok0seg(x)) 50 51 struct tc_slotdesc tc_3000_500_slots[] = { 52 { KV(0x100000000), C(TC_3000_500_DEV_OPT0), }, /* 0 - opt slot 0 */ 53 { KV(0x120000000), C(TC_3000_500_DEV_OPT1), }, /* 1 - opt slot 1 */ 54 { KV(0x140000000), C(TC_3000_500_DEV_OPT2), }, /* 2 - opt slot 2 */ 55 { KV(0x160000000), C(TC_3000_500_DEV_OPT3), }, /* 3 - opt slot 3 */ 56 { KV(0x180000000), C(TC_3000_500_DEV_OPT4), }, /* 4 - opt slot 4 */ 57 { KV(0x1a0000000), C(TC_3000_500_DEV_OPT5), }, /* 5 - opt slot 5 */ 58 { KV(0x1c0000000), C(TC_3000_500_DEV_BOGUS), }, /* 6 - TCDS ASIC */ 59 { KV(0x1e0000000), C(TC_3000_500_DEV_BOGUS), }, /* 7 - IOCTL ASIC */ 60 }; 61 int tc_3000_500_nslots = 62 sizeof(tc_3000_500_slots) / sizeof(tc_3000_500_slots[0]); 63 64 struct tc_builtin tc_3000_500_builtins[] = { 65 { "FLAMG-IO", 7, 0x00000000, C(TC_3000_500_DEV_IOASIC), }, 66 { "PMAGB-BA", 7, 0x02000000, C(TC_3000_500_DEV_CXTURBO), }, 67 { "PMAZ-DS ", 6, 0x00000000, C(TC_3000_500_DEV_TCDS), }, 68 }; 69 int tc_3000_500_nbuiltins = 70 sizeof(tc_3000_500_builtins) / sizeof(tc_3000_500_builtins[0]); 71 72 u_int32_t tc_3000_500_intrbits[TC_3000_500_NCOOKIES] = { 73 TC_3000_500_IR_OPT0, 74 TC_3000_500_IR_OPT1, 75 TC_3000_500_IR_OPT2, 76 TC_3000_500_IR_OPT3, 77 TC_3000_500_IR_OPT4, 78 TC_3000_500_IR_OPT5, 79 TC_3000_500_IR_TCDS, 80 TC_3000_500_IR_IOASIC, 81 TC_3000_500_IR_CXTURBO, 82 }; 83 84 struct tcintr { 85 int (*tci_func) __P((void *)); 86 void *tci_arg; 87 } tc_3000_500_intr[TC_3000_500_NCOOKIES]; 88 89 void 90 tc_3000_500_intr_setup() 91 { 92 u_long i; 93 u_int32_t imr; 94 95 /* 96 * Disable all slot interrupts. 97 */ 98 imr = *(volatile u_int32_t *)TC_3000_500_IMR_READ; 99 for (i = 0; i < TC_3000_500_NCOOKIES; i++) 100 imr |= tc_3000_500_intrbits[i]; 101 *(volatile u_int32_t *)TC_3000_500_IMR_WRITE = imr; 102 tc_mb(); 103 104 /* 105 * Set up interrupt handlers. 106 */ 107 for (i = 0; i < TC_3000_500_NCOOKIES; i++) { 108 tc_3000_500_intr[i].tci_func = tc_3000_500_intrnull; 109 tc_3000_500_intr[i].tci_arg = (void *)i; 110 } 111 } 112 113 void 114 tc_3000_500_intr_establish(tcadev, cookie, level, func, arg) 115 struct device *tcadev; 116 void *cookie, *arg; 117 tc_intrlevel_t level; 118 int (*func) __P((void *)); 119 { 120 u_long dev = (u_long)cookie; 121 u_int32_t imr; 122 123 #ifdef DIAGNOSTIC 124 /* XXX bounds-check cookie. */ 125 #endif 126 127 if (tc_3000_500_intr[dev].tci_func != tc_3000_500_intrnull) 128 panic("tc_3000_500_intr_establish: cookie %d twice", dev); 129 130 tc_3000_500_intr[dev].tci_func = func; 131 tc_3000_500_intr[dev].tci_arg = arg; 132 133 imr = *(volatile u_int32_t *)TC_3000_500_IMR_READ; 134 imr &= ~tc_3000_500_intrbits[dev]; 135 *(volatile u_int32_t *)TC_3000_500_IMR_WRITE = imr; 136 tc_mb(); 137 } 138 139 void 140 tc_3000_500_intr_disestablish(tcadev, cookie) 141 struct device *tcadev; 142 void *cookie; 143 { 144 u_long dev = (u_long)cookie; 145 u_int32_t imr; 146 147 #ifdef DIAGNOSTIC 148 /* XXX bounds-check cookie. */ 149 #endif 150 151 if (tc_3000_500_intr[dev].tci_func == tc_3000_500_intrnull) 152 panic("tc_3000_500_intr_disestablish: cookie %d bad intr", 153 dev); 154 155 imr = *(volatile u_int32_t *)TC_3000_500_IMR_READ; 156 imr |= tc_3000_500_intrbits[dev]; 157 *(volatile u_int32_t *)TC_3000_500_IMR_WRITE = imr; 158 tc_mb(); 159 160 tc_3000_500_intr[dev].tci_func = tc_3000_500_intrnull; 161 tc_3000_500_intr[dev].tci_arg = (void *)dev; 162 } 163 164 int 165 tc_3000_500_intrnull(val) 166 void *val; 167 { 168 169 panic("tc_3000_500_intrnull: uncaught TC intr for cookie %ld\n", 170 (u_long)val); 171 } 172 173 void 174 tc_3000_500_iointr(framep, vec) 175 void *framep; 176 int vec; 177 { 178 u_int32_t ir; 179 int ifound; 180 181 #ifdef DIAGNOSTIC 182 int s; 183 if (vec != 0x800) 184 panic("INVALID ASSUMPTION: vec %x, not 0x800", vec); 185 s = splhigh(); 186 if (s != PSL_IPL_IO) 187 panic("INVALID ASSUMPTION: IPL %d, not %d", s, PSL_IPL_IO); 188 splx(s); 189 #endif 190 191 do { 192 tc_syncbus(); 193 ir = *(volatile u_int32_t *)TC_3000_500_IR_CLEAR; 194 195 ifound = 0; 196 #define CHECKINTR(slot) \ 197 if (ir & tc_3000_500_intrbits[slot]) { \ 198 ifound = 1; \ 199 (*tc_3000_500_intr[slot].tci_func) \ 200 (tc_3000_500_intr[slot].tci_arg); \ 201 } 202 /* Do them in order of priority; highest slot # first. */ 203 CHECKINTR(TC_3000_500_DEV_CXTURBO); 204 CHECKINTR(TC_3000_500_DEV_IOASIC); 205 CHECKINTR(TC_3000_500_DEV_TCDS); 206 CHECKINTR(TC_3000_500_DEV_OPT5); 207 CHECKINTR(TC_3000_500_DEV_OPT4); 208 CHECKINTR(TC_3000_500_DEV_OPT3); 209 CHECKINTR(TC_3000_500_DEV_OPT2); 210 CHECKINTR(TC_3000_500_DEV_OPT1); 211 CHECKINTR(TC_3000_500_DEV_OPT0); 212 #undef CHECKINTR 213 214 #ifdef DIAGNOSTIC 215 #define PRINTINTR(msg, bits) \ 216 if (ir & bits) \ 217 printf(msg); 218 PRINTINTR("Second error occurred\n", TC_3000_500_IR_ERR2); 219 PRINTINTR("DMA buffer error\n", TC_3000_500_IR_DMABE); 220 PRINTINTR("DMA cross 2K boundary\n", TC_3000_500_IR_DMA2K); 221 PRINTINTR("TC reset in progress\n", TC_3000_500_IR_TCRESET); 222 PRINTINTR("TC parity error\n", TC_3000_500_IR_TCPAR); 223 PRINTINTR("DMA tag error\n", TC_3000_500_IR_DMATAG); 224 PRINTINTR("Single-bit error\n", TC_3000_500_IR_DMASBE); 225 PRINTINTR("Double-bit error\n", TC_3000_500_IR_DMADBE); 226 PRINTINTR("TC I/O timeout\n", TC_3000_500_IR_TCTIMEOUT); 227 PRINTINTR("DMA block too long\n", TC_3000_500_IR_DMABLOCK); 228 PRINTINTR("Invalid I/O address\n", TC_3000_500_IR_IOADDR); 229 PRINTINTR("DMA scatter/gather invalid\n", TC_3000_500_IR_DMASG); 230 PRINTINTR("Scatter/gather parity error\n", 231 TC_3000_500_IR_SGPAR); 232 #undef PRINTINTR 233 #endif 234 } while (ifound); 235 } 236 237 /* 238 * tc_3000_500_ioslot -- 239 * Set the PBS bits for devices on the TC. 240 */ 241 void 242 tc_3000_500_ioslot(slot, flags, set) 243 u_int32_t slot, flags; 244 int set; 245 { 246 volatile u_int32_t *iosp; 247 u_int32_t ios; 248 int s; 249 250 iosp = (volatile u_int32_t *)TC_3000_500_IOSLOT; 251 ios = *iosp; 252 flags <<= (slot * 3); 253 if (set) 254 ios |= flags; 255 else 256 ios &= ~flags; 257 s = splhigh(); 258 *iosp = ios; 259 tc_mb(); 260 splx(s); 261 } 262
Indexes created Thu Oct 02 10:09:58 GMT 2025