tc_bus_mem.c revision 1.1
1 /* $NetBSD: tc_bus_mem.c,v 1.1 1996/05/18 00:00:51 cgd Exp $ */ 2 3 /* 4 * Copyright (c) 1996 Carnegie-Mellon University. 5 * All rights reserved. 6 * 7 * Author: Chris G. Demetriou 8 * 9 * Permission to use, copy, modify and distribute this software and 10 * its documentation is hereby granted, provided that both the copyright 11 * notice and this permission notice appear in all copies of the 12 * software, derivative works or modified versions, and any portions 13 * thereof, and that both notices appear in supporting documentation. 14 * 15 * CARNEGIE MELLON ALLOWS FREE USE OF THIS SOFTWARE IN ITS "AS IS" 16 * CONDITION. CARNEGIE MELLON DISCLAIMS ANY LIABILITY OF ANY KIND 17 * FOR ANY DAMAGES WHATSOEVER RESULTING FROM THE USE OF THIS SOFTWARE. 18 * 19 * Carnegie Mellon requests users of this software to return to 20 * 21 * Software Distribution Coordinator or Software.Distribution (at) CS.CMU.EDU 22 * School of Computer Science 23 * Carnegie Mellon University 24 * Pittsburgh PA 15213-3890 25 * 26 * any improvements or extensions that they make and grant Carnegie the 27 * rights to redistribute these changes. 28 */ 29 30 /* 31 * Common TurboChannel Chipset "bus memory" functions. 32 */ 33 34 #include <sys/param.h> 35 #include <sys/malloc.h> 36 #include <sys/syslog.h> 37 #include <sys/device.h> 38 #include <vm/vm.h> 39 40 #include <machine/bus.h> 41 #include <dev/tc/tcvar.h> 42 43 int tc_mem_map __P((void *, bus_mem_addr_t, bus_mem_size_t, 44 int, bus_mem_handle_t *)); 45 void tc_mem_unmap __P((void *, bus_mem_handle_t, 46 bus_mem_size_t)); 47 u_int8_t tc_mem_read_1 __P((void *, bus_mem_handle_t, 48 bus_mem_size_t)); 49 u_int16_t tc_mem_read_2 __P((void *, bus_mem_handle_t, 50 bus_mem_size_t)); 51 u_int32_t tc_mem_read_4 __P((void *, bus_mem_handle_t, 52 bus_mem_size_t)); 53 u_int64_t tc_mem_read_8 __P((void *, bus_mem_handle_t, 54 bus_mem_size_t)); 55 void tc_mem_write_1 __P((void *, bus_mem_handle_t, 56 bus_mem_size_t, u_int8_t)); 57 void tc_mem_write_2 __P((void *, bus_mem_handle_t, 58 bus_mem_size_t, u_int16_t)); 59 void tc_mem_write_4 __P((void *, bus_mem_handle_t, 60 bus_mem_size_t, u_int32_t)); 61 void tc_mem_write_8 __P((void *, bus_mem_handle_t, 62 bus_mem_size_t, u_int64_t)); 63 64 void 65 tc_bus_mem_init(bc, memv) 66 bus_chipset_tag_t bc; 67 void *memv; 68 { 69 70 bc->bc_m_v = memv; 71 72 bc->bc_m_map = tc_mem_map; 73 bc->bc_m_unmap = tc_mem_unmap; 74 75 bc->bc_mr1 = tc_mem_read_1; 76 bc->bc_mr2 = tc_mem_read_2; 77 bc->bc_mr4 = tc_mem_read_4; 78 bc->bc_mr8 = tc_mem_read_8; 79 80 bc->bc_mw1 = tc_mem_write_1; 81 bc->bc_mw2 = tc_mem_write_2; 82 bc->bc_mw4 = tc_mem_write_4; 83 bc->bc_mw8 = tc_mem_write_8; 84 } 85 86 int 87 tc_mem_map(v, memaddr, memsize, cacheable, memhp) 88 void *v; 89 bus_mem_addr_t memaddr; 90 bus_mem_size_t memsize; 91 int cacheable; 92 bus_mem_handle_t *memhp; 93 { 94 95 if (memaddr & 0x7) 96 panic("tc_mem_map needs 8 byte alignment"); 97 if (cacheable) 98 *memhp = phystok0seg(memaddr); 99 else 100 *memhp = phystok0seg(TC_DENSE_TO_SPARSE(memaddr)); 101 return (0); 102 } 103 104 void 105 tc_mem_unmap(v, memh, memsize) 106 void *v; 107 bus_mem_handle_t memh; 108 bus_mem_size_t memsize; 109 { 110 111 /* XXX nothing to do. */ 112 } 113 114 u_int8_t 115 tc_mem_read_1(v, memh, off) 116 void *v; 117 bus_mem_handle_t memh; 118 bus_mem_size_t off; 119 { 120 volatile u_int8_t *p; 121 122 if ((memh & TC_SPACE_SPARSE) != 0) 123 panic("tc_mem_read_1 not implemented for sparse space"); 124 125 p = (u_int8_t *)(memh + off); 126 return (*p); 127 } 128 129 u_int16_t 130 tc_mem_read_2(v, memh, off) 131 void *v; 132 bus_mem_handle_t memh; 133 bus_mem_size_t off; 134 { 135 volatile u_int16_t *p; 136 137 if ((memh & TC_SPACE_SPARSE) != 0) 138 panic("tc_mem_read_2 not implemented for sparse space"); 139 140 p = (u_int16_t *)(memh + off); 141 return (*p); 142 } 143 144 u_int32_t 145 tc_mem_read_4(v, memh, off) 146 void *v; 147 bus_mem_handle_t memh; 148 bus_mem_size_t off; 149 { 150 volatile u_int32_t *p; 151 152 if ((memh & TC_SPACE_SPARSE) != 0) 153 /* Nothing special to do for 4-byte sparse space accesses */ 154 p = (u_int32_t *)(memh + (off << 1)); 155 else 156 p = (u_int32_t *)(memh + off); 157 return (*p); 158 } 159 160 u_int64_t 161 tc_mem_read_8(v, memh, off) 162 void *v; 163 bus_mem_handle_t memh; 164 bus_mem_size_t off; 165 { 166 volatile u_int64_t *p; 167 168 if ((memh & TC_SPACE_SPARSE) != 0) 169 panic("tc_mem_read_8 not implemented for sparse space"); 170 171 p = (u_int64_t *)(memh + off); 172 return (*p); 173 } 174 175 void 176 tc_mem_write_1(v, memh, off, val) 177 void *v; 178 bus_mem_handle_t memh; 179 bus_mem_size_t off; 180 u_int8_t val; 181 { 182 183 if ((memh & TC_SPACE_SPARSE) != 0) { 184 volatile u_int64_t *p, v; 185 u_int64_t shift, msk; 186 187 shift = off & 0x3; 188 off &= 0x3; 189 190 p = (u_int64_t *)(memh + (off << 1)); 191 192 msk = ~(0x1 << shift) & 0xf; 193 v = (msk << 32) | (((u_int64_t)val) << (shift * 8)); 194 195 *p = val; 196 } else { 197 volatile u_int8_t *p; 198 199 p = (u_int8_t *)(memh + off); 200 *p = val; 201 } 202 } 203 204 void 205 tc_mem_write_2(v, memh, off, val) 206 void *v; 207 bus_mem_handle_t memh; 208 bus_mem_size_t off; 209 u_int16_t val; 210 { 211 212 if ((memh & TC_SPACE_SPARSE) != 0) { 213 volatile u_int64_t *p, v; 214 u_int64_t shift, msk; 215 216 shift = off & 0x2; 217 off &= 0x3; 218 219 p = (u_int64_t *)(memh + (off << 1)); 220 221 msk = ~(0x3 << shift) & 0xf; 222 v = (msk << 32) | (((u_int64_t)val) << (shift * 8)); 223 224 *p = val; 225 } else { 226 volatile u_int16_t *p; 227 228 p = (u_int16_t *)(memh + off); 229 *p = val; 230 } 231 } 232 233 void 234 tc_mem_write_4(v, memh, off, val) 235 void *v; 236 bus_mem_handle_t memh; 237 bus_mem_size_t off; 238 u_int32_t val; 239 { 240 volatile u_int32_t *p; 241 242 if ((memh & TC_SPACE_SPARSE) != 0) 243 /* Nothing special to do for 4-byte sparse space accesses */ 244 p = (u_int32_t *)(memh + (off << 1)); 245 else 246 p = (u_int32_t *)(memh + off); 247 *p = val; 248 } 249 250 void 251 tc_mem_write_8(v, memh, off, val) 252 void *v; 253 bus_mem_handle_t memh; 254 bus_mem_size_t off; 255 u_int64_t val; 256 { 257 volatile u_int64_t *p; 258 259 if ((memh & TC_SPACE_SPARSE) != 0) 260 panic("tc_mem_read_8 not implemented for sparse space"); 261 262 p = (u_int64_t *)(memh + off); 263 *p = val; 264 } 265
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