tc_bus_mem.c revision 1.2
1 /* $NetBSD: tc_bus_mem.c,v 1.2 1996/05/20 03:14:07 cgd Exp $ */ 2 3 /* 4 * Copyright (c) 1996 Carnegie-Mellon University. 5 * All rights reserved. 6 * 7 * Author: Chris G. Demetriou 8 * 9 * Permission to use, copy, modify and distribute this software and 10 * its documentation is hereby granted, provided that both the copyright 11 * notice and this permission notice appear in all copies of the 12 * software, derivative works or modified versions, and any portions 13 * thereof, and that both notices appear in supporting documentation. 14 * 15 * CARNEGIE MELLON ALLOWS FREE USE OF THIS SOFTWARE IN ITS "AS IS" 16 * CONDITION. CARNEGIE MELLON DISCLAIMS ANY LIABILITY OF ANY KIND 17 * FOR ANY DAMAGES WHATSOEVER RESULTING FROM THE USE OF THIS SOFTWARE. 18 * 19 * Carnegie Mellon requests users of this software to return to 20 * 21 * Software Distribution Coordinator or Software.Distribution (at) CS.CMU.EDU 22 * School of Computer Science 23 * Carnegie Mellon University 24 * Pittsburgh PA 15213-3890 25 * 26 * any improvements or extensions that they make and grant Carnegie the 27 * rights to redistribute these changes. 28 */ 29 30 /* 31 * Common TurboChannel Chipset "bus memory" functions. 32 */ 33 34 #include <sys/param.h> 35 #include <sys/malloc.h> 36 #include <sys/syslog.h> 37 #include <sys/device.h> 38 #include <vm/vm.h> 39 40 #include <machine/bus.h> 41 #include <dev/tc/tcvar.h> 42 43 int tc_mem_map __P((void *, bus_mem_addr_t, bus_mem_size_t, 44 int, bus_mem_handle_t *)); 45 void tc_mem_unmap __P((void *, bus_mem_handle_t, 46 bus_mem_size_t)); 47 u_int8_t tc_mem_read_1 __P((void *, bus_mem_handle_t, 48 bus_mem_size_t)); 49 u_int16_t tc_mem_read_2 __P((void *, bus_mem_handle_t, 50 bus_mem_size_t)); 51 u_int32_t tc_mem_read_4 __P((void *, bus_mem_handle_t, 52 bus_mem_size_t)); 53 u_int64_t tc_mem_read_8 __P((void *, bus_mem_handle_t, 54 bus_mem_size_t)); 55 void tc_mem_write_1 __P((void *, bus_mem_handle_t, 56 bus_mem_size_t, u_int8_t)); 57 void tc_mem_write_2 __P((void *, bus_mem_handle_t, 58 bus_mem_size_t, u_int16_t)); 59 void tc_mem_write_4 __P((void *, bus_mem_handle_t, 60 bus_mem_size_t, u_int32_t)); 61 void tc_mem_write_8 __P((void *, bus_mem_handle_t, 62 bus_mem_size_t, u_int64_t)); 63 64 void 65 tc_bus_mem_init(bc, memv) 66 bus_chipset_tag_t bc; 67 void *memv; 68 { 69 70 bc->bc_m_v = memv; 71 72 bc->bc_m_map = tc_mem_map; 73 bc->bc_m_unmap = tc_mem_unmap; 74 75 bc->bc_mr1 = tc_mem_read_1; 76 bc->bc_mr2 = tc_mem_read_2; 77 bc->bc_mr4 = tc_mem_read_4; 78 bc->bc_mr8 = tc_mem_read_8; 79 80 bc->bc_mw1 = tc_mem_write_1; 81 bc->bc_mw2 = tc_mem_write_2; 82 bc->bc_mw4 = tc_mem_write_4; 83 bc->bc_mw8 = tc_mem_write_8; 84 } 85 86 int 87 tc_mem_map(v, memaddr, memsize, cacheable, memhp) 88 void *v; 89 bus_mem_addr_t memaddr; 90 bus_mem_size_t memsize; 91 int cacheable; 92 bus_mem_handle_t *memhp; 93 { 94 95 if (memaddr & 0x7) 96 panic("tc_mem_map needs 8 byte alignment"); 97 if (cacheable) 98 *memhp = phystok0seg(memaddr); 99 else 100 *memhp = phystok0seg(TC_DENSE_TO_SPARSE(memaddr)); 101 return (0); 102 } 103 104 void 105 tc_mem_unmap(v, memh, memsize) 106 void *v; 107 bus_mem_handle_t memh; 108 bus_mem_size_t memsize; 109 { 110 111 /* XXX nothing to do. */ 112 } 113 114 u_int8_t 115 tc_mem_read_1(v, memh, off) 116 void *v; 117 bus_mem_handle_t memh; 118 bus_mem_size_t off; 119 { 120 volatile u_int8_t *p; 121 122 wbflush(); 123 124 if ((memh & TC_SPACE_SPARSE) != 0) 125 panic("tc_mem_read_1 not implemented for sparse space"); 126 127 p = (u_int8_t *)(memh + off); 128 return (*p); 129 } 130 131 u_int16_t 132 tc_mem_read_2(v, memh, off) 133 void *v; 134 bus_mem_handle_t memh; 135 bus_mem_size_t off; 136 { 137 volatile u_int16_t *p; 138 139 wbflush(); 140 141 if ((memh & TC_SPACE_SPARSE) != 0) 142 panic("tc_mem_read_2 not implemented for sparse space"); 143 144 p = (u_int16_t *)(memh + off); 145 return (*p); 146 } 147 148 u_int32_t 149 tc_mem_read_4(v, memh, off) 150 void *v; 151 bus_mem_handle_t memh; 152 bus_mem_size_t off; 153 { 154 volatile u_int32_t *p; 155 156 wbflush(); 157 158 if ((memh & TC_SPACE_SPARSE) != 0) 159 /* Nothing special to do for 4-byte sparse space accesses */ 160 p = (u_int32_t *)(memh + (off << 1)); 161 else 162 p = (u_int32_t *)(memh + off); 163 return (*p); 164 } 165 166 u_int64_t 167 tc_mem_read_8(v, memh, off) 168 void *v; 169 bus_mem_handle_t memh; 170 bus_mem_size_t off; 171 { 172 volatile u_int64_t *p; 173 174 wbflush(); 175 176 if ((memh & TC_SPACE_SPARSE) != 0) 177 panic("tc_mem_read_8 not implemented for sparse space"); 178 179 p = (u_int64_t *)(memh + off); 180 return (*p); 181 } 182 183 void 184 tc_mem_write_1(v, memh, off, val) 185 void *v; 186 bus_mem_handle_t memh; 187 bus_mem_size_t off; 188 u_int8_t val; 189 { 190 191 if ((memh & TC_SPACE_SPARSE) != 0) { 192 volatile u_int64_t *p, v; 193 u_int64_t shift, msk; 194 195 shift = off & 0x3; 196 off &= 0x3; 197 198 p = (u_int64_t *)(memh + (off << 1)); 199 200 msk = ~(0x1 << shift) & 0xf; 201 v = (msk << 32) | (((u_int64_t)val) << (shift * 8)); 202 203 *p = val; 204 } else { 205 volatile u_int8_t *p; 206 207 p = (u_int8_t *)(memh + off); 208 *p = val; 209 } 210 wbflush(); 211 } 212 213 void 214 tc_mem_write_2(v, memh, off, val) 215 void *v; 216 bus_mem_handle_t memh; 217 bus_mem_size_t off; 218 u_int16_t val; 219 { 220 221 if ((memh & TC_SPACE_SPARSE) != 0) { 222 volatile u_int64_t *p, v; 223 u_int64_t shift, msk; 224 225 shift = off & 0x2; 226 off &= 0x3; 227 228 p = (u_int64_t *)(memh + (off << 1)); 229 230 msk = ~(0x3 << shift) & 0xf; 231 v = (msk << 32) | (((u_int64_t)val) << (shift * 8)); 232 233 *p = val; 234 } else { 235 volatile u_int16_t *p; 236 237 p = (u_int16_t *)(memh + off); 238 *p = val; 239 } 240 wbflush(); 241 } 242 243 void 244 tc_mem_write_4(v, memh, off, val) 245 void *v; 246 bus_mem_handle_t memh; 247 bus_mem_size_t off; 248 u_int32_t val; 249 { 250 volatile u_int32_t *p; 251 252 if ((memh & TC_SPACE_SPARSE) != 0) 253 /* Nothing special to do for 4-byte sparse space accesses */ 254 p = (u_int32_t *)(memh + (off << 1)); 255 else 256 p = (u_int32_t *)(memh + off); 257 *p = val; 258 wbflush(); 259 } 260 261 void 262 tc_mem_write_8(v, memh, off, val) 263 void *v; 264 bus_mem_handle_t memh; 265 bus_mem_size_t off; 266 u_int64_t val; 267 { 268 volatile u_int64_t *p; 269 270 if ((memh & TC_SPACE_SPARSE) != 0) 271 panic("tc_mem_read_8 not implemented for sparse space"); 272 273 p = (u_int64_t *)(memh + off); 274 *p = val; 275 wbflush(); 276 } 277
Indexes created Mon Sep 29 03:10:08 GMT 2025