tc_bus_mem.c revision 1.24
1 /* $NetBSD: tc_bus_mem.c,v 1.24 2000/06/29 09:02:58 mrg Exp $ */ 2 3 /* 4 * Copyright (c) 1996 Carnegie-Mellon University. 5 * All rights reserved. 6 * 7 * Author: Chris G. Demetriou 8 * 9 * Permission to use, copy, modify and distribute this software and 10 * its documentation is hereby granted, provided that both the copyright 11 * notice and this permission notice appear in all copies of the 12 * software, derivative works or modified versions, and any portions 13 * thereof, and that both notices appear in supporting documentation. 14 * 15 * CARNEGIE MELLON ALLOWS FREE USE OF THIS SOFTWARE IN ITS "AS IS" 16 * CONDITION. CARNEGIE MELLON DISCLAIMS ANY LIABILITY OF ANY KIND 17 * FOR ANY DAMAGES WHATSOEVER RESULTING FROM THE USE OF THIS SOFTWARE. 18 * 19 * Carnegie Mellon requests users of this software to return to 20 * 21 * Software Distribution Coordinator or Software.Distribution (at) CS.CMU.EDU 22 * School of Computer Science 23 * Carnegie Mellon University 24 * Pittsburgh PA 15213-3890 25 * 26 * any improvements or extensions that they make and grant Carnegie the 27 * rights to redistribute these changes. 28 */ 29 30 /* 31 * Common TurboChannel Chipset "bus memory" functions. 32 */ 33 34 #include <sys/cdefs.h> /* RCS ID & Copyright macro defns */ 35 36 __KERNEL_RCSID(0, "$NetBSD: tc_bus_mem.c,v 1.24 2000/06/29 09:02:58 mrg Exp $"); 37 38 #include <sys/param.h> 39 #include <sys/systm.h> 40 #include <sys/malloc.h> 41 #include <sys/syslog.h> 42 #include <sys/device.h> 43 44 #include <uvm/uvm_extern.h> 45 46 #include <machine/bus.h> 47 #include <dev/tc/tcvar.h> 48 49 #define __C(A,B) __CONCAT(A,B) 50 51 /* mapping/unmapping */ 52 int tc_mem_map __P((void *, bus_addr_t, bus_size_t, int, 53 bus_space_handle_t *, int)); 54 void tc_mem_unmap __P((void *, bus_space_handle_t, bus_size_t, int)); 55 int tc_mem_subregion __P((void *, bus_space_handle_t, bus_size_t, 56 bus_size_t, bus_space_handle_t *)); 57 58 int tc_mem_translate __P((void *, bus_addr_t, bus_size_t, 59 int, struct alpha_bus_space_translation *)); 60 int tc_mem_get_window __P((void *, int, 61 struct alpha_bus_space_translation *)); 62 63 /* allocation/deallocation */ 64 int tc_mem_alloc __P((void *, bus_addr_t, bus_addr_t, bus_size_t, 65 bus_size_t, bus_addr_t, int, bus_addr_t *, 66 bus_space_handle_t *)); 67 void tc_mem_free __P((void *, bus_space_handle_t, bus_size_t)); 68 69 /* get kernel virtual address */ 70 void * tc_mem_vaddr __P((void *, bus_space_handle_t)); 71 72 /* barrier */ 73 inline void tc_mem_barrier __P((void *, bus_space_handle_t, 74 bus_size_t, bus_size_t, int)); 75 76 /* read (single) */ 77 inline u_int8_t tc_mem_read_1 __P((void *, bus_space_handle_t, bus_size_t)); 78 inline u_int16_t tc_mem_read_2 __P((void *, bus_space_handle_t, bus_size_t)); 79 inline u_int32_t tc_mem_read_4 __P((void *, bus_space_handle_t, bus_size_t)); 80 inline u_int64_t tc_mem_read_8 __P((void *, bus_space_handle_t, bus_size_t)); 81 82 /* read multiple */ 83 void tc_mem_read_multi_1 __P((void *, bus_space_handle_t, 84 bus_size_t, u_int8_t *, bus_size_t)); 85 void tc_mem_read_multi_2 __P((void *, bus_space_handle_t, 86 bus_size_t, u_int16_t *, bus_size_t)); 87 void tc_mem_read_multi_4 __P((void *, bus_space_handle_t, 88 bus_size_t, u_int32_t *, bus_size_t)); 89 void tc_mem_read_multi_8 __P((void *, bus_space_handle_t, 90 bus_size_t, u_int64_t *, bus_size_t)); 91 92 /* read region */ 93 void tc_mem_read_region_1 __P((void *, bus_space_handle_t, 94 bus_size_t, u_int8_t *, bus_size_t)); 95 void tc_mem_read_region_2 __P((void *, bus_space_handle_t, 96 bus_size_t, u_int16_t *, bus_size_t)); 97 void tc_mem_read_region_4 __P((void *, bus_space_handle_t, 98 bus_size_t, u_int32_t *, bus_size_t)); 99 void tc_mem_read_region_8 __P((void *, bus_space_handle_t, 100 bus_size_t, u_int64_t *, bus_size_t)); 101 102 /* write (single) */ 103 inline void tc_mem_write_1 __P((void *, bus_space_handle_t, bus_size_t, 104 u_int8_t)); 105 inline void tc_mem_write_2 __P((void *, bus_space_handle_t, bus_size_t, 106 u_int16_t)); 107 inline void tc_mem_write_4 __P((void *, bus_space_handle_t, bus_size_t, 108 u_int32_t)); 109 inline void tc_mem_write_8 __P((void *, bus_space_handle_t, bus_size_t, 110 u_int64_t)); 111 112 /* write multiple */ 113 void tc_mem_write_multi_1 __P((void *, bus_space_handle_t, 114 bus_size_t, const u_int8_t *, bus_size_t)); 115 void tc_mem_write_multi_2 __P((void *, bus_space_handle_t, 116 bus_size_t, const u_int16_t *, bus_size_t)); 117 void tc_mem_write_multi_4 __P((void *, bus_space_handle_t, 118 bus_size_t, const u_int32_t *, bus_size_t)); 119 void tc_mem_write_multi_8 __P((void *, bus_space_handle_t, 120 bus_size_t, const u_int64_t *, bus_size_t)); 121 122 /* write region */ 123 void tc_mem_write_region_1 __P((void *, bus_space_handle_t, 124 bus_size_t, const u_int8_t *, bus_size_t)); 125 void tc_mem_write_region_2 __P((void *, bus_space_handle_t, 126 bus_size_t, const u_int16_t *, bus_size_t)); 127 void tc_mem_write_region_4 __P((void *, bus_space_handle_t, 128 bus_size_t, const u_int32_t *, bus_size_t)); 129 void tc_mem_write_region_8 __P((void *, bus_space_handle_t, 130 bus_size_t, const u_int64_t *, bus_size_t)); 131 132 /* set multiple */ 133 void tc_mem_set_multi_1 __P((void *, bus_space_handle_t, 134 bus_size_t, u_int8_t, bus_size_t)); 135 void tc_mem_set_multi_2 __P((void *, bus_space_handle_t, 136 bus_size_t, u_int16_t, bus_size_t)); 137 void tc_mem_set_multi_4 __P((void *, bus_space_handle_t, 138 bus_size_t, u_int32_t, bus_size_t)); 139 void tc_mem_set_multi_8 __P((void *, bus_space_handle_t, 140 bus_size_t, u_int64_t, bus_size_t)); 141 142 /* set region */ 143 void tc_mem_set_region_1 __P((void *, bus_space_handle_t, 144 bus_size_t, u_int8_t, bus_size_t)); 145 void tc_mem_set_region_2 __P((void *, bus_space_handle_t, 146 bus_size_t, u_int16_t, bus_size_t)); 147 void tc_mem_set_region_4 __P((void *, bus_space_handle_t, 148 bus_size_t, u_int32_t, bus_size_t)); 149 void tc_mem_set_region_8 __P((void *, bus_space_handle_t, 150 bus_size_t, u_int64_t, bus_size_t)); 151 152 /* copy */ 153 void tc_mem_copy_region_1 __P((void *, bus_space_handle_t, 154 bus_size_t, bus_space_handle_t, bus_size_t, bus_size_t)); 155 void tc_mem_copy_region_2 __P((void *, bus_space_handle_t, 156 bus_size_t, bus_space_handle_t, bus_size_t, bus_size_t)); 157 void tc_mem_copy_region_4 __P((void *, bus_space_handle_t, 158 bus_size_t, bus_space_handle_t, bus_size_t, bus_size_t)); 159 void tc_mem_copy_region_8 __P((void *, bus_space_handle_t, 160 bus_size_t, bus_space_handle_t, bus_size_t, bus_size_t)); 161 162 static struct alpha_bus_space tc_mem_space = { 163 /* cookie */ 164 NULL, 165 166 /* mapping/unmapping */ 167 tc_mem_map, 168 tc_mem_unmap, 169 tc_mem_subregion, 170 171 tc_mem_translate, 172 tc_mem_get_window, 173 174 /* allocation/deallocation */ 175 tc_mem_alloc, 176 tc_mem_free, 177 178 /* get kernel virtual address */ 179 tc_mem_vaddr, 180 181 /* barrier */ 182 tc_mem_barrier, 183 184 /* read (single) */ 185 tc_mem_read_1, 186 tc_mem_read_2, 187 tc_mem_read_4, 188 tc_mem_read_8, 189 190 /* read multiple */ 191 tc_mem_read_multi_1, 192 tc_mem_read_multi_2, 193 tc_mem_read_multi_4, 194 tc_mem_read_multi_8, 195 196 /* read region */ 197 tc_mem_read_region_1, 198 tc_mem_read_region_2, 199 tc_mem_read_region_4, 200 tc_mem_read_region_8, 201 202 /* write (single) */ 203 tc_mem_write_1, 204 tc_mem_write_2, 205 tc_mem_write_4, 206 tc_mem_write_8, 207 208 /* write multiple */ 209 tc_mem_write_multi_1, 210 tc_mem_write_multi_2, 211 tc_mem_write_multi_4, 212 tc_mem_write_multi_8, 213 214 /* write region */ 215 tc_mem_write_region_1, 216 tc_mem_write_region_2, 217 tc_mem_write_region_4, 218 tc_mem_write_region_8, 219 220 /* set multiple */ 221 tc_mem_set_multi_1, 222 tc_mem_set_multi_2, 223 tc_mem_set_multi_4, 224 tc_mem_set_multi_8, 225 226 /* set region */ 227 tc_mem_set_region_1, 228 tc_mem_set_region_2, 229 tc_mem_set_region_4, 230 tc_mem_set_region_8, 231 232 /* copy */ 233 tc_mem_copy_region_1, 234 tc_mem_copy_region_2, 235 tc_mem_copy_region_4, 236 tc_mem_copy_region_8, 237 }; 238 239 bus_space_tag_t 240 tc_bus_mem_init(memv) 241 void *memv; 242 { 243 bus_space_tag_t h = &tc_mem_space; 244 245 h->abs_cookie = memv; 246 return (h); 247 } 248 249 /* ARGSUSED */ 250 int 251 tc_mem_translate(v, memaddr, memlen, flags, abst) 252 void *v; 253 bus_addr_t memaddr; 254 bus_size_t memlen; 255 int flags; 256 struct alpha_bus_space_translation *abst; 257 { 258 259 return (EOPNOTSUPP); 260 } 261 262 /* ARGSUSED */ 263 int 264 tc_mem_get_window(v, window, abst) 265 void *v; 266 int window; 267 struct alpha_bus_space_translation *abst; 268 { 269 270 return (EOPNOTSUPP); 271 } 272 273 /* ARGSUSED */ 274 int 275 tc_mem_map(v, memaddr, memsize, flags, memhp, acct) 276 void *v; 277 bus_addr_t memaddr; 278 bus_size_t memsize; 279 int flags; 280 bus_space_handle_t *memhp; 281 int acct; 282 { 283 int cacheable = flags & BUS_SPACE_MAP_CACHEABLE; 284 int linear = flags & BUS_SPACE_MAP_LINEAR; 285 286 /* Requests for linear uncacheable space can't be satisfied. */ 287 if (linear && !cacheable) 288 return (EOPNOTSUPP); 289 290 if (memaddr & 0x7) 291 panic("tc_mem_map needs 8 byte alignment"); 292 if (cacheable) 293 *memhp = ALPHA_PHYS_TO_K0SEG(memaddr); 294 else 295 *memhp = ALPHA_PHYS_TO_K0SEG(TC_DENSE_TO_SPARSE(memaddr)); 296 return (0); 297 } 298 299 /* ARGSUSED */ 300 void 301 tc_mem_unmap(v, memh, memsize, acct) 302 void *v; 303 bus_space_handle_t memh; 304 bus_size_t memsize; 305 int acct; 306 { 307 308 /* XXX XX XXX nothing to do. */ 309 } 310 311 int 312 tc_mem_subregion(v, memh, offset, size, nmemh) 313 void *v; 314 bus_space_handle_t memh, *nmemh; 315 bus_size_t offset, size; 316 { 317 318 /* Disallow subregioning that would make the handle unaligned. */ 319 if ((offset & 0x7) != 0) 320 return (1); 321 322 if ((memh & TC_SPACE_SPARSE) != 0) 323 *nmemh = memh + (offset << 1); 324 else 325 *nmemh = memh + offset; 326 327 return (0); 328 } 329 330 int 331 tc_mem_alloc(v, rstart, rend, size, align, boundary, flags, addrp, bshp) 332 void *v; 333 bus_addr_t rstart, rend, *addrp; 334 bus_size_t size, align, boundary; 335 int flags; 336 bus_space_handle_t *bshp; 337 { 338 339 /* XXX XXX XXX XXX XXX XXX */ 340 panic("tc_mem_alloc unimplemented"); 341 } 342 343 void 344 tc_mem_free(v, bsh, size) 345 void *v; 346 bus_space_handle_t bsh; 347 bus_size_t size; 348 { 349 350 /* XXX XXX XXX XXX XXX XXX */ 351 panic("tc_mem_free unimplemented"); 352 } 353 354 void * 355 tc_mem_vaddr(v, bsh) 356 void *v; 357 bus_space_handle_t bsh; 358 { 359 #ifdef DIAGNOSTIC 360 if ((bsh & TC_SPACE_SPARSE) != 0) { 361 /* 362 * tc_mem_map() catches linear && !cacheable, 363 * so we shouldn't come here 364 */ 365 panic("tc_mem_vaddr"); 366 } 367 #endif 368 return ((void *)bsh); 369 } 370 371 inline void 372 tc_mem_barrier(v, h, o, l, f) 373 void *v; 374 bus_space_handle_t h; 375 bus_size_t o, l; 376 int f; 377 { 378 379 if ((f & BUS_SPACE_BARRIER_READ) != 0) 380 alpha_mb(); 381 else if ((f & BUS_SPACE_BARRIER_WRITE) != 0) 382 alpha_wmb(); 383 } 384 385 inline u_int8_t 386 tc_mem_read_1(v, memh, off) 387 void *v; 388 bus_space_handle_t memh; 389 bus_size_t off; 390 { 391 volatile u_int8_t *p; 392 393 alpha_mb(); /* XXX XXX XXX */ 394 395 if ((memh & TC_SPACE_SPARSE) != 0) 396 panic("tc_mem_read_1 not implemented for sparse space"); 397 398 p = (u_int8_t *)(memh + off); 399 return (*p); 400 } 401 402 inline u_int16_t 403 tc_mem_read_2(v, memh, off) 404 void *v; 405 bus_space_handle_t memh; 406 bus_size_t off; 407 { 408 volatile u_int16_t *p; 409 410 alpha_mb(); /* XXX XXX XXX */ 411 412 if ((memh & TC_SPACE_SPARSE) != 0) 413 panic("tc_mem_read_2 not implemented for sparse space"); 414 415 p = (u_int16_t *)(memh + off); 416 return (*p); 417 } 418 419 inline u_int32_t 420 tc_mem_read_4(v, memh, off) 421 void *v; 422 bus_space_handle_t memh; 423 bus_size_t off; 424 { 425 volatile u_int32_t *p; 426 427 alpha_mb(); /* XXX XXX XXX */ 428 429 if ((memh & TC_SPACE_SPARSE) != 0) 430 /* Nothing special to do for 4-byte sparse space accesses */ 431 p = (u_int32_t *)(memh + (off << 1)); 432 else 433 p = (u_int32_t *)(memh + off); 434 return (*p); 435 } 436 437 inline u_int64_t 438 tc_mem_read_8(v, memh, off) 439 void *v; 440 bus_space_handle_t memh; 441 bus_size_t off; 442 { 443 volatile u_int64_t *p; 444 445 alpha_mb(); /* XXX XXX XXX */ 446 447 if ((memh & TC_SPACE_SPARSE) != 0) 448 panic("tc_mem_read_8 not implemented for sparse space"); 449 450 p = (u_int64_t *)(memh + off); 451 return (*p); 452 } 453 454 #define tc_mem_read_multi_N(BYTES,TYPE) \ 455 void \ 456 __C(tc_mem_read_multi_,BYTES)(v, h, o, a, c) \ 457 void *v; \ 458 bus_space_handle_t h; \ 459 bus_size_t o, c; \ 460 TYPE *a; \ 461 { \ 462 \ 463 while (c-- > 0) { \ 464 tc_mem_barrier(v, h, o, sizeof *a, BUS_SPACE_BARRIER_READ); \ 465 *a++ = __C(tc_mem_read_,BYTES)(v, h, o); \ 466 } \ 467 } 468 tc_mem_read_multi_N(1,u_int8_t) 469 tc_mem_read_multi_N(2,u_int16_t) 470 tc_mem_read_multi_N(4,u_int32_t) 471 tc_mem_read_multi_N(8,u_int64_t) 472 473 #define tc_mem_read_region_N(BYTES,TYPE) \ 474 void \ 475 __C(tc_mem_read_region_,BYTES)(v, h, o, a, c) \ 476 void *v; \ 477 bus_space_handle_t h; \ 478 bus_size_t o, c; \ 479 TYPE *a; \ 480 { \ 481 \ 482 while (c-- > 0) { \ 483 *a++ = __C(tc_mem_read_,BYTES)(v, h, o); \ 484 o += sizeof *a; \ 485 } \ 486 } 487 tc_mem_read_region_N(1,u_int8_t) 488 tc_mem_read_region_N(2,u_int16_t) 489 tc_mem_read_region_N(4,u_int32_t) 490 tc_mem_read_region_N(8,u_int64_t) 491 492 inline void 493 tc_mem_write_1(v, memh, off, val) 494 void *v; 495 bus_space_handle_t memh; 496 bus_size_t off; 497 u_int8_t val; 498 { 499 500 if ((memh & TC_SPACE_SPARSE) != 0) { 501 volatile u_int64_t *p, v; 502 u_int64_t shift, msk; 503 504 shift = off & 0x3; 505 off &= 0x3; 506 507 p = (u_int64_t *)(memh + (off << 1)); 508 509 msk = ~(0x1 << shift) & 0xf; 510 v = (msk << 32) | (((u_int64_t)val) << (shift * 8)); 511 512 *p = val; 513 } else { 514 volatile u_int8_t *p; 515 516 p = (u_int8_t *)(memh + off); 517 *p = val; 518 } 519 alpha_mb(); /* XXX XXX XXX */ 520 } 521 522 inline void 523 tc_mem_write_2(v, memh, off, val) 524 void *v; 525 bus_space_handle_t memh; 526 bus_size_t off; 527 u_int16_t val; 528 { 529 530 if ((memh & TC_SPACE_SPARSE) != 0) { 531 volatile u_int64_t *p, v; 532 u_int64_t shift, msk; 533 534 shift = off & 0x2; 535 off &= 0x3; 536 537 p = (u_int64_t *)(memh + (off << 1)); 538 539 msk = ~(0x3 << shift) & 0xf; 540 v = (msk << 32) | (((u_int64_t)val) << (shift * 8)); 541 542 *p = val; 543 } else { 544 volatile u_int16_t *p; 545 546 p = (u_int16_t *)(memh + off); 547 *p = val; 548 } 549 alpha_mb(); /* XXX XXX XXX */ 550 } 551 552 inline void 553 tc_mem_write_4(v, memh, off, val) 554 void *v; 555 bus_space_handle_t memh; 556 bus_size_t off; 557 u_int32_t val; 558 { 559 volatile u_int32_t *p; 560 561 if ((memh & TC_SPACE_SPARSE) != 0) 562 /* Nothing special to do for 4-byte sparse space accesses */ 563 p = (u_int32_t *)(memh + (off << 1)); 564 else 565 p = (u_int32_t *)(memh + off); 566 *p = val; 567 alpha_mb(); /* XXX XXX XXX */ 568 } 569 570 inline void 571 tc_mem_write_8(v, memh, off, val) 572 void *v; 573 bus_space_handle_t memh; 574 bus_size_t off; 575 u_int64_t val; 576 { 577 volatile u_int64_t *p; 578 579 if ((memh & TC_SPACE_SPARSE) != 0) 580 panic("tc_mem_read_8 not implemented for sparse space"); 581 582 p = (u_int64_t *)(memh + off); 583 *p = val; 584 alpha_mb(); /* XXX XXX XXX */ 585 } 586 587 #define tc_mem_write_multi_N(BYTES,TYPE) \ 588 void \ 589 __C(tc_mem_write_multi_,BYTES)(v, h, o, a, c) \ 590 void *v; \ 591 bus_space_handle_t h; \ 592 bus_size_t o, c; \ 593 const TYPE *a; \ 594 { \ 595 \ 596 while (c-- > 0) { \ 597 __C(tc_mem_write_,BYTES)(v, h, o, *a++); \ 598 tc_mem_barrier(v, h, o, sizeof *a, BUS_SPACE_BARRIER_WRITE); \ 599 } \ 600 } 601 tc_mem_write_multi_N(1,u_int8_t) 602 tc_mem_write_multi_N(2,u_int16_t) 603 tc_mem_write_multi_N(4,u_int32_t) 604 tc_mem_write_multi_N(8,u_int64_t) 605 606 #define tc_mem_write_region_N(BYTES,TYPE) \ 607 void \ 608 __C(tc_mem_write_region_,BYTES)(v, h, o, a, c) \ 609 void *v; \ 610 bus_space_handle_t h; \ 611 bus_size_t o, c; \ 612 const TYPE *a; \ 613 { \ 614 \ 615 while (c-- > 0) { \ 616 __C(tc_mem_write_,BYTES)(v, h, o, *a++); \ 617 o += sizeof *a; \ 618 } \ 619 } 620 tc_mem_write_region_N(1,u_int8_t) 621 tc_mem_write_region_N(2,u_int16_t) 622 tc_mem_write_region_N(4,u_int32_t) 623 tc_mem_write_region_N(8,u_int64_t) 624 625 #define tc_mem_set_multi_N(BYTES,TYPE) \ 626 void \ 627 __C(tc_mem_set_multi_,BYTES)(v, h, o, val, c) \ 628 void *v; \ 629 bus_space_handle_t h; \ 630 bus_size_t o, c; \ 631 TYPE val; \ 632 { \ 633 \ 634 while (c-- > 0) { \ 635 __C(tc_mem_write_,BYTES)(v, h, o, val); \ 636 tc_mem_barrier(v, h, o, sizeof val, BUS_SPACE_BARRIER_WRITE); \ 637 } \ 638 } 639 tc_mem_set_multi_N(1,u_int8_t) 640 tc_mem_set_multi_N(2,u_int16_t) 641 tc_mem_set_multi_N(4,u_int32_t) 642 tc_mem_set_multi_N(8,u_int64_t) 643 644 #define tc_mem_set_region_N(BYTES,TYPE) \ 645 void \ 646 __C(tc_mem_set_region_,BYTES)(v, h, o, val, c) \ 647 void *v; \ 648 bus_space_handle_t h; \ 649 bus_size_t o, c; \ 650 TYPE val; \ 651 { \ 652 \ 653 while (c-- > 0) { \ 654 __C(tc_mem_write_,BYTES)(v, h, o, val); \ 655 o += sizeof val; \ 656 } \ 657 } 658 tc_mem_set_region_N(1,u_int8_t) 659 tc_mem_set_region_N(2,u_int16_t) 660 tc_mem_set_region_N(4,u_int32_t) 661 tc_mem_set_region_N(8,u_int64_t) 662 663 #define tc_mem_copy_region_N(BYTES) \ 664 void \ 665 __C(tc_mem_copy_region_,BYTES)(v, h1, o1, h2, o2, c) \ 666 void *v; \ 667 bus_space_handle_t h1, h2; \ 668 bus_size_t o1, o2, c; \ 669 { \ 670 bus_size_t o; \ 671 \ 672 if ((h1 & TC_SPACE_SPARSE) != 0 && \ 673 (h2 & TC_SPACE_SPARSE) != 0) { \ 674 memmove((void *)(h2 + o2), (void *)(h1 + o1), c * BYTES); \ 675 return; \ 676 } \ 677 \ 678 if (h1 + o1 >= h2 + o2) \ 679 /* src after dest: copy forward */ \ 680 for (o = 0; c > 0; c--, o += BYTES) \ 681 __C(tc_mem_write_,BYTES)(v, h2, o2 + o, \ 682 __C(tc_mem_read_,BYTES)(v, h1, o1 + o)); \ 683 else \ 684 /* dest after src: copy backwards */ \ 685 for (o = (c - 1) * BYTES; c > 0; c--, o -= BYTES) \ 686 __C(tc_mem_write_,BYTES)(v, h2, o2 + o, \ 687 __C(tc_mem_read_,BYTES)(v, h1, o1 + o)); \ 688 } 689 tc_mem_copy_region_N(1) 690 tc_mem_copy_region_N(2) 691 tc_mem_copy_region_N(4) 692 tc_mem_copy_region_N(8) 693
Indexes created Tue Sep 30 11:09:46 GMT 2025