tc_bus_mem.c revision 1.3
1 /* $NetBSD: tc_bus_mem.c,v 1.3 1996/06/03 20:18:57 cgd Exp $ */ 2 3 /* 4 * Copyright (c) 1996 Carnegie-Mellon University. 5 * All rights reserved. 6 * 7 * Author: Chris G. Demetriou 8 * 9 * Permission to use, copy, modify and distribute this software and 10 * its documentation is hereby granted, provided that both the copyright 11 * notice and this permission notice appear in all copies of the 12 * software, derivative works or modified versions, and any portions 13 * thereof, and that both notices appear in supporting documentation. 14 * 15 * CARNEGIE MELLON ALLOWS FREE USE OF THIS SOFTWARE IN ITS "AS IS" 16 * CONDITION. CARNEGIE MELLON DISCLAIMS ANY LIABILITY OF ANY KIND 17 * FOR ANY DAMAGES WHATSOEVER RESULTING FROM THE USE OF THIS SOFTWARE. 18 * 19 * Carnegie Mellon requests users of this software to return to 20 * 21 * Software Distribution Coordinator or Software.Distribution (at) CS.CMU.EDU 22 * School of Computer Science 23 * Carnegie Mellon University 24 * Pittsburgh PA 15213-3890 25 * 26 * any improvements or extensions that they make and grant Carnegie the 27 * rights to redistribute these changes. 28 */ 29 30 /* 31 * Common TurboChannel Chipset "bus memory" functions. 32 */ 33 34 #include <sys/param.h> 35 #include <sys/malloc.h> 36 #include <sys/syslog.h> 37 #include <sys/device.h> 38 #include <vm/vm.h> 39 40 #include <machine/bus.h> 41 #include <dev/tc/tcvar.h> 42 43 int tc_mem_map __P((void *, bus_mem_addr_t, bus_mem_size_t, 44 int, bus_mem_handle_t *)); 45 void tc_mem_unmap __P((void *, bus_mem_handle_t, 46 bus_mem_size_t)); 47 u_int8_t tc_mem_read_1 __P((void *, bus_mem_handle_t, 48 bus_mem_size_t)); 49 u_int16_t tc_mem_read_2 __P((void *, bus_mem_handle_t, 50 bus_mem_size_t)); 51 u_int32_t tc_mem_read_4 __P((void *, bus_mem_handle_t, 52 bus_mem_size_t)); 53 u_int64_t tc_mem_read_8 __P((void *, bus_mem_handle_t, 54 bus_mem_size_t)); 55 void tc_mem_write_1 __P((void *, bus_mem_handle_t, 56 bus_mem_size_t, u_int8_t)); 57 void tc_mem_write_2 __P((void *, bus_mem_handle_t, 58 bus_mem_size_t, u_int16_t)); 59 void tc_mem_write_4 __P((void *, bus_mem_handle_t, 60 bus_mem_size_t, u_int32_t)); 61 void tc_mem_write_8 __P((void *, bus_mem_handle_t, 62 bus_mem_size_t, u_int64_t)); 63 64 /* XXX DOES NOT BELONG */ 65 vm_offset_t tc_XXX_dmamap __P((void *)); 66 67 void 68 tc_bus_mem_init(bc, memv) 69 bus_chipset_tag_t bc; 70 void *memv; 71 { 72 73 bc->bc_m_v = memv; 74 75 bc->bc_m_map = tc_mem_map; 76 bc->bc_m_unmap = tc_mem_unmap; 77 78 bc->bc_mr1 = tc_mem_read_1; 79 bc->bc_mr2 = tc_mem_read_2; 80 bc->bc_mr4 = tc_mem_read_4; 81 bc->bc_mr8 = tc_mem_read_8; 82 83 bc->bc_mw1 = tc_mem_write_1; 84 bc->bc_mw2 = tc_mem_write_2; 85 bc->bc_mw4 = tc_mem_write_4; 86 bc->bc_mw8 = tc_mem_write_8; 87 88 /* XXX DOES NOT BELONG */ 89 bc->bc_XXX_dmamap = tc_XXX_dmamap; 90 } 91 92 int 93 tc_mem_map(v, memaddr, memsize, cacheable, memhp) 94 void *v; 95 bus_mem_addr_t memaddr; 96 bus_mem_size_t memsize; 97 int cacheable; 98 bus_mem_handle_t *memhp; 99 { 100 101 if (memaddr & 0x7) 102 panic("tc_mem_map needs 8 byte alignment"); 103 if (cacheable) 104 *memhp = phystok0seg(memaddr); 105 else 106 *memhp = phystok0seg(TC_DENSE_TO_SPARSE(memaddr)); 107 return (0); 108 } 109 110 void 111 tc_mem_unmap(v, memh, memsize) 112 void *v; 113 bus_mem_handle_t memh; 114 bus_mem_size_t memsize; 115 { 116 117 /* XXX nothing to do. */ 118 } 119 120 u_int8_t 121 tc_mem_read_1(v, memh, off) 122 void *v; 123 bus_mem_handle_t memh; 124 bus_mem_size_t off; 125 { 126 volatile u_int8_t *p; 127 128 wbflush(); 129 130 if ((memh & TC_SPACE_SPARSE) != 0) 131 panic("tc_mem_read_1 not implemented for sparse space"); 132 133 p = (u_int8_t *)(memh + off); 134 return (*p); 135 } 136 137 u_int16_t 138 tc_mem_read_2(v, memh, off) 139 void *v; 140 bus_mem_handle_t memh; 141 bus_mem_size_t off; 142 { 143 volatile u_int16_t *p; 144 145 wbflush(); 146 147 if ((memh & TC_SPACE_SPARSE) != 0) 148 panic("tc_mem_read_2 not implemented for sparse space"); 149 150 p = (u_int16_t *)(memh + off); 151 return (*p); 152 } 153 154 u_int32_t 155 tc_mem_read_4(v, memh, off) 156 void *v; 157 bus_mem_handle_t memh; 158 bus_mem_size_t off; 159 { 160 volatile u_int32_t *p; 161 162 wbflush(); 163 164 if ((memh & TC_SPACE_SPARSE) != 0) 165 /* Nothing special to do for 4-byte sparse space accesses */ 166 p = (u_int32_t *)(memh + (off << 1)); 167 else 168 p = (u_int32_t *)(memh + off); 169 return (*p); 170 } 171 172 u_int64_t 173 tc_mem_read_8(v, memh, off) 174 void *v; 175 bus_mem_handle_t memh; 176 bus_mem_size_t off; 177 { 178 volatile u_int64_t *p; 179 180 wbflush(); 181 182 if ((memh & TC_SPACE_SPARSE) != 0) 183 panic("tc_mem_read_8 not implemented for sparse space"); 184 185 p = (u_int64_t *)(memh + off); 186 return (*p); 187 } 188 189 void 190 tc_mem_write_1(v, memh, off, val) 191 void *v; 192 bus_mem_handle_t memh; 193 bus_mem_size_t off; 194 u_int8_t val; 195 { 196 197 if ((memh & TC_SPACE_SPARSE) != 0) { 198 volatile u_int64_t *p, v; 199 u_int64_t shift, msk; 200 201 shift = off & 0x3; 202 off &= 0x3; 203 204 p = (u_int64_t *)(memh + (off << 1)); 205 206 msk = ~(0x1 << shift) & 0xf; 207 v = (msk << 32) | (((u_int64_t)val) << (shift * 8)); 208 209 *p = val; 210 } else { 211 volatile u_int8_t *p; 212 213 p = (u_int8_t *)(memh + off); 214 *p = val; 215 } 216 wbflush(); 217 } 218 219 void 220 tc_mem_write_2(v, memh, off, val) 221 void *v; 222 bus_mem_handle_t memh; 223 bus_mem_size_t off; 224 u_int16_t val; 225 { 226 227 if ((memh & TC_SPACE_SPARSE) != 0) { 228 volatile u_int64_t *p, v; 229 u_int64_t shift, msk; 230 231 shift = off & 0x2; 232 off &= 0x3; 233 234 p = (u_int64_t *)(memh + (off << 1)); 235 236 msk = ~(0x3 << shift) & 0xf; 237 v = (msk << 32) | (((u_int64_t)val) << (shift * 8)); 238 239 *p = val; 240 } else { 241 volatile u_int16_t *p; 242 243 p = (u_int16_t *)(memh + off); 244 *p = val; 245 } 246 wbflush(); 247 } 248 249 void 250 tc_mem_write_4(v, memh, off, val) 251 void *v; 252 bus_mem_handle_t memh; 253 bus_mem_size_t off; 254 u_int32_t val; 255 { 256 volatile u_int32_t *p; 257 258 if ((memh & TC_SPACE_SPARSE) != 0) 259 /* Nothing special to do for 4-byte sparse space accesses */ 260 p = (u_int32_t *)(memh + (off << 1)); 261 else 262 p = (u_int32_t *)(memh + off); 263 *p = val; 264 wbflush(); 265 } 266 267 void 268 tc_mem_write_8(v, memh, off, val) 269 void *v; 270 bus_mem_handle_t memh; 271 bus_mem_size_t off; 272 u_int64_t val; 273 { 274 volatile u_int64_t *p; 275 276 if ((memh & TC_SPACE_SPARSE) != 0) 277 panic("tc_mem_read_8 not implemented for sparse space"); 278 279 p = (u_int64_t *)(memh + off); 280 *p = val; 281 wbflush(); 282 } 283 284 /* XXX DOES NOT BELONG */ 285 vm_offset_t 286 tc_XXX_dmamap(addr) 287 void *addr; 288 { 289 290 return (vtophys(addr)); 291 } 292
Indexes created Mon Sep 29 21:09:56 GMT 2025