tc_bus_mem.c revision 1.37
1 /* $NetBSD: tc_bus_mem.c,v 1.37 2016/08/03 17:16:07 christos Exp $ */ 2 3 /* 4 * Copyright (c) 1996 Carnegie-Mellon University. 5 * All rights reserved. 6 * 7 * Author: Chris G. Demetriou 8 * 9 * Permission to use, copy, modify and distribute this software and 10 * its documentation is hereby granted, provided that both the copyright 11 * notice and this permission notice appear in all copies of the 12 * software, derivative works or modified versions, and any portions 13 * thereof, and that both notices appear in supporting documentation. 14 * 15 * CARNEGIE MELLON ALLOWS FREE USE OF THIS SOFTWARE IN ITS "AS IS" 16 * CONDITION. CARNEGIE MELLON DISCLAIMS ANY LIABILITY OF ANY KIND 17 * FOR ANY DAMAGES WHATSOEVER RESULTING FROM THE USE OF THIS SOFTWARE. 18 * 19 * Carnegie Mellon requests users of this software to return to 20 * 21 * Software Distribution Coordinator or Software.Distribution (at) CS.CMU.EDU 22 * School of Computer Science 23 * Carnegie Mellon University 24 * Pittsburgh PA 15213-3890 25 * 26 * any improvements or extensions that they make and grant Carnegie the 27 * rights to redistribute these changes. 28 */ 29 30 /* 31 * Common TurboChannel Chipset "bus memory" functions. 32 */ 33 34 #include <sys/cdefs.h> /* RCS ID & Copyright macro defns */ 35 36 __KERNEL_RCSID(0, "$NetBSD: tc_bus_mem.c,v 1.37 2016/08/03 17:16:07 christos Exp $"); 37 38 #include <sys/param.h> 39 #include <sys/systm.h> 40 #include <sys/malloc.h> 41 #include <sys/syslog.h> 42 #include <sys/device.h> 43 44 #include <sys/bus.h> 45 #include <dev/tc/tcvar.h> 46 47 #define __C(A,B) __CONCAT(A,B) 48 49 /* mapping/unmapping */ 50 int tc_mem_map(void *, bus_addr_t, bus_size_t, int, 51 bus_space_handle_t *, int); 52 void tc_mem_unmap(void *, bus_space_handle_t, bus_size_t, int); 53 int tc_mem_subregion(void *, bus_space_handle_t, bus_size_t, 54 bus_size_t, bus_space_handle_t *); 55 56 int tc_mem_translate(void *, bus_addr_t, bus_size_t, 57 int, struct alpha_bus_space_translation *); 58 int tc_mem_get_window(void *, int, 59 struct alpha_bus_space_translation *); 60 61 /* allocation/deallocation */ 62 int tc_mem_alloc(void *, bus_addr_t, bus_addr_t, bus_size_t, 63 bus_size_t, bus_addr_t, int, bus_addr_t *, 64 bus_space_handle_t *); 65 void tc_mem_free(void *, bus_space_handle_t, bus_size_t); 66 67 /* get kernel virtual address */ 68 void * tc_mem_vaddr(void *, bus_space_handle_t); 69 70 /* mmap for user */ 71 paddr_t tc_mem_mmap(void *, bus_addr_t, off_t, int, int); 72 73 /* barrier */ 74 static inline void tc_mem_barrier(void *, bus_space_handle_t, 75 bus_size_t, bus_size_t, int); 76 77 /* read (single) */ 78 static inline uint8_t tc_mem_read_1(void *, bus_space_handle_t, bus_size_t); 79 static inline uint16_t tc_mem_read_2(void *, bus_space_handle_t, bus_size_t); 80 static inline uint32_t tc_mem_read_4(void *, bus_space_handle_t, bus_size_t); 81 static inline uint64_t tc_mem_read_8(void *, bus_space_handle_t, bus_size_t); 82 83 /* read multiple */ 84 void tc_mem_read_multi_1(void *, bus_space_handle_t, 85 bus_size_t, uint8_t *, bus_size_t); 86 void tc_mem_read_multi_2(void *, bus_space_handle_t, 87 bus_size_t, uint16_t *, bus_size_t); 88 void tc_mem_read_multi_4(void *, bus_space_handle_t, 89 bus_size_t, uint32_t *, bus_size_t); 90 void tc_mem_read_multi_8(void *, bus_space_handle_t, 91 bus_size_t, uint64_t *, bus_size_t); 92 93 /* read region */ 94 void tc_mem_read_region_1(void *, bus_space_handle_t, 95 bus_size_t, uint8_t *, bus_size_t); 96 void tc_mem_read_region_2(void *, bus_space_handle_t, 97 bus_size_t, uint16_t *, bus_size_t); 98 void tc_mem_read_region_4(void *, bus_space_handle_t, 99 bus_size_t, uint32_t *, bus_size_t); 100 void tc_mem_read_region_8(void *, bus_space_handle_t, 101 bus_size_t, uint64_t *, bus_size_t); 102 103 /* write (single) */ 104 static inline void tc_mem_write_1(void *, bus_space_handle_t, bus_size_t, 105 uint8_t); 106 static inline void tc_mem_write_2(void *, bus_space_handle_t, bus_size_t, 107 uint16_t); 108 static inline void tc_mem_write_4(void *, bus_space_handle_t, bus_size_t, 109 uint32_t); 110 static inline void tc_mem_write_8(void *, bus_space_handle_t, bus_size_t, 111 uint64_t); 112 113 /* write multiple */ 114 void tc_mem_write_multi_1(void *, bus_space_handle_t, 115 bus_size_t, const uint8_t *, bus_size_t); 116 void tc_mem_write_multi_2(void *, bus_space_handle_t, 117 bus_size_t, const uint16_t *, bus_size_t); 118 void tc_mem_write_multi_4(void *, bus_space_handle_t, 119 bus_size_t, const uint32_t *, bus_size_t); 120 void tc_mem_write_multi_8(void *, bus_space_handle_t, 121 bus_size_t, const uint64_t *, bus_size_t); 122 123 /* write region */ 124 void tc_mem_write_region_1(void *, bus_space_handle_t, 125 bus_size_t, const uint8_t *, bus_size_t); 126 void tc_mem_write_region_2(void *, bus_space_handle_t, 127 bus_size_t, const uint16_t *, bus_size_t); 128 void tc_mem_write_region_4(void *, bus_space_handle_t, 129 bus_size_t, const uint32_t *, bus_size_t); 130 void tc_mem_write_region_8(void *, bus_space_handle_t, 131 bus_size_t, const uint64_t *, bus_size_t); 132 133 /* set multiple */ 134 void tc_mem_set_multi_1(void *, bus_space_handle_t, 135 bus_size_t, uint8_t, bus_size_t); 136 void tc_mem_set_multi_2(void *, bus_space_handle_t, 137 bus_size_t, uint16_t, bus_size_t); 138 void tc_mem_set_multi_4(void *, bus_space_handle_t, 139 bus_size_t, uint32_t, bus_size_t); 140 void tc_mem_set_multi_8(void *, bus_space_handle_t, 141 bus_size_t, uint64_t, bus_size_t); 142 143 /* set region */ 144 void tc_mem_set_region_1(void *, bus_space_handle_t, 145 bus_size_t, uint8_t, bus_size_t); 146 void tc_mem_set_region_2(void *, bus_space_handle_t, 147 bus_size_t, uint16_t, bus_size_t); 148 void tc_mem_set_region_4(void *, bus_space_handle_t, 149 bus_size_t, uint32_t, bus_size_t); 150 void tc_mem_set_region_8(void *, bus_space_handle_t, 151 bus_size_t, uint64_t, bus_size_t); 152 153 /* copy */ 154 void tc_mem_copy_region_1(void *, bus_space_handle_t, 155 bus_size_t, bus_space_handle_t, bus_size_t, bus_size_t); 156 void tc_mem_copy_region_2(void *, bus_space_handle_t, 157 bus_size_t, bus_space_handle_t, bus_size_t, bus_size_t); 158 void tc_mem_copy_region_4(void *, bus_space_handle_t, 159 bus_size_t, bus_space_handle_t, bus_size_t, bus_size_t); 160 void tc_mem_copy_region_8(void *, bus_space_handle_t, 161 bus_size_t, bus_space_handle_t, bus_size_t, bus_size_t); 162 163 static struct alpha_bus_space tc_mem_space = { 164 /* cookie */ 165 NULL, 166 167 /* mapping/unmapping */ 168 tc_mem_map, 169 tc_mem_unmap, 170 tc_mem_subregion, 171 172 tc_mem_translate, 173 tc_mem_get_window, 174 175 /* allocation/deallocation */ 176 tc_mem_alloc, 177 tc_mem_free, 178 179 /* get kernel virtual address */ 180 tc_mem_vaddr, 181 182 /* mmap for user */ 183 tc_mem_mmap, 184 185 /* barrier */ 186 tc_mem_barrier, 187 188 /* read (single) */ 189 tc_mem_read_1, 190 tc_mem_read_2, 191 tc_mem_read_4, 192 tc_mem_read_8, 193 194 /* read multiple */ 195 tc_mem_read_multi_1, 196 tc_mem_read_multi_2, 197 tc_mem_read_multi_4, 198 tc_mem_read_multi_8, 199 200 /* read region */ 201 tc_mem_read_region_1, 202 tc_mem_read_region_2, 203 tc_mem_read_region_4, 204 tc_mem_read_region_8, 205 206 /* write (single) */ 207 tc_mem_write_1, 208 tc_mem_write_2, 209 tc_mem_write_4, 210 tc_mem_write_8, 211 212 /* write multiple */ 213 tc_mem_write_multi_1, 214 tc_mem_write_multi_2, 215 tc_mem_write_multi_4, 216 tc_mem_write_multi_8, 217 218 /* write region */ 219 tc_mem_write_region_1, 220 tc_mem_write_region_2, 221 tc_mem_write_region_4, 222 tc_mem_write_region_8, 223 224 /* set multiple */ 225 tc_mem_set_multi_1, 226 tc_mem_set_multi_2, 227 tc_mem_set_multi_4, 228 tc_mem_set_multi_8, 229 230 /* set region */ 231 tc_mem_set_region_1, 232 tc_mem_set_region_2, 233 tc_mem_set_region_4, 234 tc_mem_set_region_8, 235 236 /* copy */ 237 tc_mem_copy_region_1, 238 tc_mem_copy_region_2, 239 tc_mem_copy_region_4, 240 tc_mem_copy_region_8, 241 }; 242 243 bus_space_tag_t 244 tc_bus_mem_init(void *memv) 245 { 246 bus_space_tag_t h = &tc_mem_space; 247 248 h->abs_cookie = memv; 249 return (h); 250 } 251 252 /* ARGSUSED */ 253 int 254 tc_mem_translate(void *v, bus_addr_t memaddr, bus_size_t memlen, int flags, struct alpha_bus_space_translation *abst) 255 { 256 257 return (EOPNOTSUPP); 258 } 259 260 /* ARGSUSED */ 261 int 262 tc_mem_get_window(void *v, int window, struct alpha_bus_space_translation *abst) 263 { 264 265 return (EOPNOTSUPP); 266 } 267 268 /* ARGSUSED */ 269 int 270 tc_mem_map(void *v, bus_addr_t memaddr, bus_size_t memsize, int flags, bus_space_handle_t *memhp, int acct) 271 { 272 int cacheable = flags & BUS_SPACE_MAP_CACHEABLE; 273 int linear = flags & BUS_SPACE_MAP_LINEAR; 274 275 /* Requests for linear uncacheable space can't be satisfied. */ 276 if (linear && !cacheable) 277 return (EOPNOTSUPP); 278 279 if (memaddr & 0x7) 280 panic("%s: need 8 byte alignment", __func__); 281 if (cacheable) 282 *memhp = ALPHA_PHYS_TO_K0SEG(memaddr); 283 else 284 *memhp = ALPHA_PHYS_TO_K0SEG(TC_DENSE_TO_SPARSE(memaddr)); 285 return (0); 286 } 287 288 /* ARGSUSED */ 289 void 290 tc_mem_unmap(void *v, bus_space_handle_t memh, bus_size_t memsize, int acct) 291 { 292 293 /* XXX XX XXX nothing to do. */ 294 } 295 296 int 297 tc_mem_subregion(void *v, bus_space_handle_t memh, bus_size_t offset, bus_size_t size, bus_space_handle_t *nmemh) 298 { 299 300 /* Disallow subregioning that would make the handle unaligned. */ 301 if ((offset & 0x7) != 0) 302 return (1); 303 304 if ((memh & TC_SPACE_SPARSE) != 0) 305 *nmemh = memh + (offset << 1); 306 else 307 *nmemh = memh + offset; 308 309 return (0); 310 } 311 312 int 313 tc_mem_alloc(void *v, bus_addr_t rstart, bus_addr_t rend, bus_size_t size, bus_size_t align, bus_size_t boundary, int flags, bus_addr_t *addrp, bus_space_handle_t *bshp) 314 { 315 316 /* XXX XXX XXX XXX XXX XXX */ 317 panic("%s: unimplemented", __func__); 318 } 319 320 void 321 tc_mem_free(void *v, bus_space_handle_t bsh, bus_size_t size) 322 { 323 324 /* XXX XXX XXX XXX XXX XXX */ 325 panic("%s: unimplemented", __func__); 326 } 327 328 void * 329 tc_mem_vaddr(void *v, bus_space_handle_t bsh) 330 { 331 #ifdef DIAGNOSTIC 332 if ((bsh & TC_SPACE_SPARSE) != 0) { 333 /* 334 * tc_mem_map() catches linear && !cacheable, 335 * so we shouldn't come here 336 */ 337 panic("%s: can't do sparse", __func__); 338 } 339 #endif 340 return ((void *)bsh); 341 } 342 343 paddr_t 344 tc_mem_mmap(void *v, bus_addr_t addr, off_t off, int prot, int flags) 345 { 346 int linear = flags & BUS_SPACE_MAP_LINEAR; 347 bus_addr_t rv; 348 349 if (linear) 350 rv = addr + off; 351 else 352 rv = TC_DENSE_TO_SPARSE(addr + off); 353 354 return (alpha_btop(rv)); 355 } 356 357 static inline void 358 tc_mem_barrier(void *v, bus_space_handle_t h, bus_size_t o, bus_size_t l, int f) 359 { 360 361 if ((f & BUS_SPACE_BARRIER_READ) != 0) 362 alpha_mb(); 363 else if ((f & BUS_SPACE_BARRIER_WRITE) != 0) 364 alpha_wmb(); 365 } 366 367 /* 368 * https://web-docs.gsi.de/~kraemer/COLLECTION/DEC/d3syspmb.pdf 369 * http://h20565.www2.hpe.com/hpsc/doc/public/display?docId=emr_na-c04623255 370 */ 371 #define TC_SPARSE_PTR(memh, off) \ 372 ((void *)((memh) + ((off & ((bus_size_t)-1 << 2)) << 1))) 373 374 static inline uint8_t 375 tc_mem_read_1(void *v, bus_space_handle_t memh, bus_size_t off) 376 { 377 378 alpha_mb(); /* XXX XXX XXX */ 379 380 if ((memh & TC_SPACE_SPARSE) != 0) { 381 volatile uint32_t *p; 382 383 p = TC_SPARSE_PTR(memh, off); 384 return ((*p >> ((off & 3) << 3)) & 0xff); 385 } else { 386 volatile uint8_t *p; 387 388 p = (uint8_t *)(memh + off); 389 return (*p); 390 } 391 } 392 393 static inline uint16_t 394 tc_mem_read_2(void *v, bus_space_handle_t memh, bus_size_t off) 395 { 396 397 alpha_mb(); /* XXX XXX XXX */ 398 399 if ((memh & TC_SPACE_SPARSE) != 0) { 400 volatile uint32_t *p; 401 402 p = TC_SPARSE_PTR(memh, off); 403 return ((*p >> ((off & 2) << 3)) & 0xffff); 404 } else { 405 volatile uint16_t *p; 406 407 p = (uint16_t *)(memh + off); 408 return (*p); 409 } 410 } 411 412 static inline uint32_t 413 tc_mem_read_4(void *v, bus_space_handle_t memh, bus_size_t off) 414 { 415 volatile uint32_t *p; 416 417 alpha_mb(); /* XXX XXX XXX */ 418 419 if ((memh & TC_SPACE_SPARSE) != 0) 420 /* Nothing special to do for 4-byte sparse space accesses */ 421 p = (uint32_t *)(memh + (off << 1)); 422 else 423 /* 424 * LDL to a dense space address always results in two 425 * TURBOchannel I/O read transactions to consecutive longword 426 * addresses. Use caution in dense space if the option has 427 * registers with read side effects. 428 */ 429 p = (uint32_t *)(memh + off); 430 return (*p); 431 } 432 433 static inline uint64_t 434 tc_mem_read_8(void *v, bus_space_handle_t memh, bus_size_t off) 435 { 436 volatile uint64_t *p; 437 438 alpha_mb(); /* XXX XXX XXX */ 439 440 if ((memh & TC_SPACE_SPARSE) != 0) 441 panic("%s: not implemented for sparse space", __func__); 442 443 p = (uint64_t *)(memh + off); 444 return (*p); 445 } 446 447 #define tc_mem_read_multi_N(BYTES,TYPE) \ 448 void \ 449 __C(tc_mem_read_multi_,BYTES)( \ 450 void *v, \ 451 bus_space_handle_t h, \ 452 bus_size_t o, \ 453 TYPE *a, \ 454 bus_size_t c) \ 455 { \ 456 \ 457 while (c-- > 0) { \ 458 tc_mem_barrier(v, h, o, sizeof *a, BUS_SPACE_BARRIER_READ); \ 459 *a++ = __C(tc_mem_read_,BYTES)(v, h, o); \ 460 } \ 461 } 462 tc_mem_read_multi_N(1,uint8_t) 463 tc_mem_read_multi_N(2,uint16_t) 464 tc_mem_read_multi_N(4,uint32_t) 465 tc_mem_read_multi_N(8,uint64_t) 466 467 #define tc_mem_read_region_N(BYTES,TYPE) \ 468 void \ 469 __C(tc_mem_read_region_,BYTES)( \ 470 void *v, \ 471 bus_space_handle_t h, \ 472 bus_size_t o, \ 473 TYPE *a, \ 474 bus_size_t c) \ 475 { \ 476 \ 477 while (c-- > 0) { \ 478 *a++ = __C(tc_mem_read_,BYTES)(v, h, o); \ 479 o += sizeof *a; \ 480 } \ 481 } 482 tc_mem_read_region_N(1,uint8_t) 483 tc_mem_read_region_N(2,uint16_t) 484 tc_mem_read_region_N(4,uint32_t) 485 tc_mem_read_region_N(8,uint64_t) 486 487 #define TC_SPARSE_WR_PVAL(msk, b, v) \ 488 ((UINT64_C(msk) << (32 + (b))) | ((uint64_t)(v) << ((b) << 3))) 489 490 static inline void 491 tc_mem_write_1(void *v, bus_space_handle_t memh, bus_size_t off, uint8_t val) 492 { 493 494 if ((memh & TC_SPACE_SPARSE) != 0) { 495 volatile uint64_t *p; 496 497 p = TC_SPARSE_PTR(memh, off); 498 *p = TC_SPARSE_WR_PVAL(0x1, off & 3, val); 499 } else 500 panic("%s: not implemented for dense space", __func__); 501 502 alpha_mb(); /* XXX XXX XXX */ 503 } 504 505 static inline void 506 tc_mem_write_2(void *v, bus_space_handle_t memh, bus_size_t off, uint16_t val) 507 { 508 509 if ((memh & TC_SPACE_SPARSE) != 0) { 510 volatile uint64_t *p; 511 512 p = TC_SPARSE_PTR(memh, off); 513 *p = TC_SPARSE_WR_PVAL(0x3, off & 2, val); 514 } else 515 panic("%s: not implemented for dense space", __func__); 516 517 alpha_mb(); /* XXX XXX XXX */ 518 } 519 520 static inline void 521 tc_mem_write_4(void *v, bus_space_handle_t memh, bus_size_t off, uint32_t val) 522 { 523 volatile uint32_t *p; 524 525 if ((memh & TC_SPACE_SPARSE) != 0) 526 /* Nothing special to do for 4-byte sparse space accesses */ 527 p = (uint32_t *)(memh + (off << 1)); 528 else 529 p = (uint32_t *)(memh + off); 530 *p = val; 531 532 alpha_mb(); /* XXX XXX XXX */ 533 } 534 535 static inline void 536 tc_mem_write_8(void *v, bus_space_handle_t memh, bus_size_t off, uint64_t val) 537 { 538 volatile uint64_t *p; 539 540 if ((memh & TC_SPACE_SPARSE) != 0) 541 panic("%s: not implemented for sparse space", __func__); 542 543 p = (uint64_t *)(memh + off); 544 *p = val; 545 546 alpha_mb(); /* XXX XXX XXX */ 547 } 548 549 #define tc_mem_write_multi_N(BYTES,TYPE) \ 550 void \ 551 __C(tc_mem_write_multi_,BYTES)( \ 552 void *v, \ 553 bus_space_handle_t h, \ 554 bus_size_t o, \ 555 const TYPE *a, \ 556 bus_size_t c) \ 557 { \ 558 \ 559 while (c-- > 0) { \ 560 __C(tc_mem_write_,BYTES)(v, h, o, *a++); \ 561 tc_mem_barrier(v, h, o, sizeof *a, BUS_SPACE_BARRIER_WRITE); \ 562 } \ 563 } 564 tc_mem_write_multi_N(1,uint8_t) 565 tc_mem_write_multi_N(2,uint16_t) 566 tc_mem_write_multi_N(4,uint32_t) 567 tc_mem_write_multi_N(8,uint64_t) 568 569 #define tc_mem_write_region_N(BYTES,TYPE) \ 570 void \ 571 __C(tc_mem_write_region_,BYTES)( \ 572 void *v, \ 573 bus_space_handle_t h, \ 574 bus_size_t o, \ 575 const TYPE *a, \ 576 bus_size_t c) \ 577 { \ 578 \ 579 while (c-- > 0) { \ 580 __C(tc_mem_write_,BYTES)(v, h, o, *a++); \ 581 o += sizeof *a; \ 582 } \ 583 } 584 tc_mem_write_region_N(1,uint8_t) 585 tc_mem_write_region_N(2,uint16_t) 586 tc_mem_write_region_N(4,uint32_t) 587 tc_mem_write_region_N(8,uint64_t) 588 589 #define tc_mem_set_multi_N(BYTES,TYPE) \ 590 void \ 591 __C(tc_mem_set_multi_,BYTES)( \ 592 void *v, \ 593 bus_space_handle_t h, \ 594 bus_size_t o, \ 595 TYPE val, \ 596 bus_size_t c) \ 597 { \ 598 \ 599 while (c-- > 0) { \ 600 __C(tc_mem_write_,BYTES)(v, h, o, val); \ 601 tc_mem_barrier(v, h, o, sizeof val, BUS_SPACE_BARRIER_WRITE); \ 602 } \ 603 } 604 tc_mem_set_multi_N(1,uint8_t) 605 tc_mem_set_multi_N(2,uint16_t) 606 tc_mem_set_multi_N(4,uint32_t) 607 tc_mem_set_multi_N(8,uint64_t) 608 609 #define tc_mem_set_region_N(BYTES,TYPE) \ 610 void \ 611 __C(tc_mem_set_region_,BYTES)( \ 612 void *v, \ 613 bus_space_handle_t h, \ 614 bus_size_t o, \ 615 TYPE val, \ 616 bus_size_t c) \ 617 { \ 618 \ 619 while (c-- > 0) { \ 620 __C(tc_mem_write_,BYTES)(v, h, o, val); \ 621 o += sizeof val; \ 622 } \ 623 } 624 tc_mem_set_region_N(1,uint8_t) 625 tc_mem_set_region_N(2,uint16_t) 626 tc_mem_set_region_N(4,uint32_t) 627 tc_mem_set_region_N(8,uint64_t) 628 629 #define tc_mem_copy_region_N(BYTES) \ 630 void \ 631 __C(tc_mem_copy_region_,BYTES)( \ 632 void *v, \ 633 bus_space_handle_t h1, \ 634 bus_size_t o1, \ 635 bus_space_handle_t h2, \ 636 bus_size_t o2, \ 637 bus_size_t c) \ 638 { \ 639 bus_size_t o; \ 640 \ 641 if ((h1 & TC_SPACE_SPARSE) != 0 && \ 642 (h2 & TC_SPACE_SPARSE) != 0) { \ 643 memmove((void *)(h2 + o2), (void *)(h1 + o1), c * BYTES); \ 644 return; \ 645 } \ 646 \ 647 if (h1 + o1 >= h2 + o2) \ 648 /* src after dest: copy forward */ \ 649 for (o = 0; c > 0; c--, o += BYTES) \ 650 __C(tc_mem_write_,BYTES)(v, h2, o2 + o, \ 651 __C(tc_mem_read_,BYTES)(v, h1, o1 + o)); \ 652 else \ 653 /* dest after src: copy backwards */ \ 654 for (o = (c - 1) * BYTES; c > 0; c--, o -= BYTES) \ 655 __C(tc_mem_write_,BYTES)(v, h2, o2 + o, \ 656 __C(tc_mem_read_,BYTES)(v, h1, o1 + o)); \ 657 } 658 tc_mem_copy_region_N(1) 659 tc_mem_copy_region_N(2) 660 tc_mem_copy_region_N(4) 661 tc_mem_copy_region_N(8) 662
Indexes created Tue Sep 30 07:10:03 GMT 2025