tc_bus_mem.c revision 1.4
1 /* $NetBSD: tc_bus_mem.c,v 1.4 1996/06/11 21:16:29 cgd Exp $ */ 2 3 /* 4 * Copyright (c) 1996 Carnegie-Mellon University. 5 * All rights reserved. 6 * 7 * Author: Chris G. Demetriou 8 * 9 * Permission to use, copy, modify and distribute this software and 10 * its documentation is hereby granted, provided that both the copyright 11 * notice and this permission notice appear in all copies of the 12 * software, derivative works or modified versions, and any portions 13 * thereof, and that both notices appear in supporting documentation. 14 * 15 * CARNEGIE MELLON ALLOWS FREE USE OF THIS SOFTWARE IN ITS "AS IS" 16 * CONDITION. CARNEGIE MELLON DISCLAIMS ANY LIABILITY OF ANY KIND 17 * FOR ANY DAMAGES WHATSOEVER RESULTING FROM THE USE OF THIS SOFTWARE. 18 * 19 * Carnegie Mellon requests users of this software to return to 20 * 21 * Software Distribution Coordinator or Software.Distribution (at) CS.CMU.EDU 22 * School of Computer Science 23 * Carnegie Mellon University 24 * Pittsburgh PA 15213-3890 25 * 26 * any improvements or extensions that they make and grant Carnegie the 27 * rights to redistribute these changes. 28 */ 29 30 /* 31 * Common TurboChannel Chipset "bus memory" functions. 32 */ 33 34 #include <sys/param.h> 35 #include <sys/malloc.h> 36 #include <sys/syslog.h> 37 #include <sys/device.h> 38 #include <vm/vm.h> 39 40 #include <machine/bus.h> 41 #include <dev/tc/tcvar.h> 42 43 int tc_mem_map __P((void *, bus_mem_addr_t, bus_mem_size_t, 44 int, bus_mem_handle_t *)); 45 void tc_mem_unmap __P((void *, bus_mem_handle_t, 46 bus_mem_size_t)); 47 int tc_mem_subregion __P((void *, bus_mem_handle_t, bus_mem_size_t, 48 bus_mem_size_t, bus_mem_handle_t *)); 49 u_int8_t tc_mem_read_1 __P((void *, bus_mem_handle_t, 50 bus_mem_size_t)); 51 u_int16_t tc_mem_read_2 __P((void *, bus_mem_handle_t, 52 bus_mem_size_t)); 53 u_int32_t tc_mem_read_4 __P((void *, bus_mem_handle_t, 54 bus_mem_size_t)); 55 u_int64_t tc_mem_read_8 __P((void *, bus_mem_handle_t, 56 bus_mem_size_t)); 57 void tc_mem_write_1 __P((void *, bus_mem_handle_t, 58 bus_mem_size_t, u_int8_t)); 59 void tc_mem_write_2 __P((void *, bus_mem_handle_t, 60 bus_mem_size_t, u_int16_t)); 61 void tc_mem_write_4 __P((void *, bus_mem_handle_t, 62 bus_mem_size_t, u_int32_t)); 63 void tc_mem_write_8 __P((void *, bus_mem_handle_t, 64 bus_mem_size_t, u_int64_t)); 65 66 /* XXX DOES NOT BELONG */ 67 vm_offset_t tc_XXX_dmamap __P((void *)); 68 69 void 70 tc_bus_mem_init(bc, memv) 71 bus_chipset_tag_t bc; 72 void *memv; 73 { 74 75 bc->bc_m_v = memv; 76 77 bc->bc_m_map = tc_mem_map; 78 bc->bc_m_unmap = tc_mem_unmap; 79 bc->bc_m_subregion = tc_mem_subregion; 80 81 bc->bc_mr1 = tc_mem_read_1; 82 bc->bc_mr2 = tc_mem_read_2; 83 bc->bc_mr4 = tc_mem_read_4; 84 bc->bc_mr8 = tc_mem_read_8; 85 86 bc->bc_mw1 = tc_mem_write_1; 87 bc->bc_mw2 = tc_mem_write_2; 88 bc->bc_mw4 = tc_mem_write_4; 89 bc->bc_mw8 = tc_mem_write_8; 90 91 /* XXX DOES NOT BELONG */ 92 bc->bc_XXX_dmamap = tc_XXX_dmamap; 93 } 94 95 int 96 tc_mem_map(v, memaddr, memsize, cacheable, memhp) 97 void *v; 98 bus_mem_addr_t memaddr; 99 bus_mem_size_t memsize; 100 int cacheable; 101 bus_mem_handle_t *memhp; 102 { 103 104 if (memaddr & 0x7) 105 panic("tc_mem_map needs 8 byte alignment"); 106 if (cacheable) 107 *memhp = phystok0seg(memaddr); 108 else 109 *memhp = phystok0seg(TC_DENSE_TO_SPARSE(memaddr)); 110 return (0); 111 } 112 113 void 114 tc_mem_unmap(v, memh, memsize) 115 void *v; 116 bus_mem_handle_t memh; 117 bus_mem_size_t memsize; 118 { 119 120 /* XXX nothing to do. */ 121 } 122 123 int 124 tc_mem_subregion(v, memh, offset, size, nmemh) 125 void *v; 126 bus_mem_handle_t memh, *nmemh; 127 bus_mem_size_t offset, size; 128 { 129 130 if ((memh & TC_SPACE_SPARSE) != 0) 131 *nmemh = memh + (off << 1); 132 else 133 *nmemh = memh + off; 134 return (0); 135 } 136 137 u_int8_t 138 tc_mem_read_1(v, memh, off) 139 void *v; 140 bus_mem_handle_t memh; 141 bus_mem_size_t off; 142 { 143 volatile u_int8_t *p; 144 145 wbflush(); 146 147 if ((memh & TC_SPACE_SPARSE) != 0) 148 panic("tc_mem_read_1 not implemented for sparse space"); 149 150 p = (u_int8_t *)(memh + off); 151 return (*p); 152 } 153 154 u_int16_t 155 tc_mem_read_2(v, memh, off) 156 void *v; 157 bus_mem_handle_t memh; 158 bus_mem_size_t off; 159 { 160 volatile u_int16_t *p; 161 162 wbflush(); 163 164 if ((memh & TC_SPACE_SPARSE) != 0) 165 panic("tc_mem_read_2 not implemented for sparse space"); 166 167 p = (u_int16_t *)(memh + off); 168 return (*p); 169 } 170 171 u_int32_t 172 tc_mem_read_4(v, memh, off) 173 void *v; 174 bus_mem_handle_t memh; 175 bus_mem_size_t off; 176 { 177 volatile u_int32_t *p; 178 179 wbflush(); 180 181 if ((memh & TC_SPACE_SPARSE) != 0) 182 /* Nothing special to do for 4-byte sparse space accesses */ 183 p = (u_int32_t *)(memh + (off << 1)); 184 else 185 p = (u_int32_t *)(memh + off); 186 return (*p); 187 } 188 189 u_int64_t 190 tc_mem_read_8(v, memh, off) 191 void *v; 192 bus_mem_handle_t memh; 193 bus_mem_size_t off; 194 { 195 volatile u_int64_t *p; 196 197 wbflush(); 198 199 if ((memh & TC_SPACE_SPARSE) != 0) 200 panic("tc_mem_read_8 not implemented for sparse space"); 201 202 p = (u_int64_t *)(memh + off); 203 return (*p); 204 } 205 206 void 207 tc_mem_write_1(v, memh, off, val) 208 void *v; 209 bus_mem_handle_t memh; 210 bus_mem_size_t off; 211 u_int8_t val; 212 { 213 214 if ((memh & TC_SPACE_SPARSE) != 0) { 215 volatile u_int64_t *p, v; 216 u_int64_t shift, msk; 217 218 shift = off & 0x3; /* XXX breaks if subregion */ 219 off &= 0x3; 220 221 p = (u_int64_t *)(memh + (off << 1)); 222 223 msk = ~(0x1 << shift) & 0xf; 224 v = (msk << 32) | (((u_int64_t)val) << (shift * 8)); 225 226 *p = val; 227 } else { 228 volatile u_int8_t *p; 229 230 p = (u_int8_t *)(memh + off); 231 *p = val; 232 } 233 wbflush(); 234 } 235 236 void 237 tc_mem_write_2(v, memh, off, val) 238 void *v; 239 bus_mem_handle_t memh; 240 bus_mem_size_t off; 241 u_int16_t val; 242 { 243 244 if ((memh & TC_SPACE_SPARSE) != 0) { 245 volatile u_int64_t *p, v; 246 u_int64_t shift, msk; 247 248 shift = off & 0x2; /* XXX breaks if subregion */ 249 off &= 0x3; 250 251 p = (u_int64_t *)(memh + (off << 1)); 252 253 msk = ~(0x3 << shift) & 0xf; 254 v = (msk << 32) | (((u_int64_t)val) << (shift * 8)); 255 256 *p = val; 257 } else { 258 volatile u_int16_t *p; 259 260 p = (u_int16_t *)(memh + off); 261 *p = val; 262 } 263 wbflush(); 264 } 265 266 void 267 tc_mem_write_4(v, memh, off, val) 268 void *v; 269 bus_mem_handle_t memh; 270 bus_mem_size_t off; 271 u_int32_t val; 272 { 273 volatile u_int32_t *p; 274 275 if ((memh & TC_SPACE_SPARSE) != 0) 276 /* Nothing special to do for 4-byte sparse space accesses */ 277 p = (u_int32_t *)(memh + (off << 1)); 278 else 279 p = (u_int32_t *)(memh + off); 280 *p = val; 281 wbflush(); 282 } 283 284 void 285 tc_mem_write_8(v, memh, off, val) 286 void *v; 287 bus_mem_handle_t memh; 288 bus_mem_size_t off; 289 u_int64_t val; 290 { 291 volatile u_int64_t *p; 292 293 if ((memh & TC_SPACE_SPARSE) != 0) 294 panic("tc_mem_read_8 not implemented for sparse space"); 295 296 p = (u_int64_t *)(memh + off); 297 *p = val; 298 wbflush(); 299 } 300 301 /* XXX DOES NOT BELONG */ 302 vm_offset_t 303 tc_XXX_dmamap(addr) 304 void *addr; 305 { 306 307 return (vtophys(addr)); 308 } 309
Indexes created Tue Sep 30 11:09:46 GMT 2025