tc_bus_mem.c revision 1.6
1 /* $NetBSD: tc_bus_mem.c,v 1.6 1996/06/11 21:28:31 cgd Exp $ */ 2 3 /* 4 * Copyright (c) 1996 Carnegie-Mellon University. 5 * All rights reserved. 6 * 7 * Author: Chris G. Demetriou 8 * 9 * Permission to use, copy, modify and distribute this software and 10 * its documentation is hereby granted, provided that both the copyright 11 * notice and this permission notice appear in all copies of the 12 * software, derivative works or modified versions, and any portions 13 * thereof, and that both notices appear in supporting documentation. 14 * 15 * CARNEGIE MELLON ALLOWS FREE USE OF THIS SOFTWARE IN ITS "AS IS" 16 * CONDITION. CARNEGIE MELLON DISCLAIMS ANY LIABILITY OF ANY KIND 17 * FOR ANY DAMAGES WHATSOEVER RESULTING FROM THE USE OF THIS SOFTWARE. 18 * 19 * Carnegie Mellon requests users of this software to return to 20 * 21 * Software Distribution Coordinator or Software.Distribution (at) CS.CMU.EDU 22 * School of Computer Science 23 * Carnegie Mellon University 24 * Pittsburgh PA 15213-3890 25 * 26 * any improvements or extensions that they make and grant Carnegie the 27 * rights to redistribute these changes. 28 */ 29 30 /* 31 * Common TurboChannel Chipset "bus memory" functions. 32 */ 33 34 #include <sys/param.h> 35 #include <sys/malloc.h> 36 #include <sys/syslog.h> 37 #include <sys/device.h> 38 #include <vm/vm.h> 39 40 #include <machine/bus.h> 41 #include <dev/tc/tcvar.h> 42 43 int tc_mem_map __P((void *, bus_mem_addr_t, bus_mem_size_t, 44 int, bus_mem_handle_t *)); 45 void tc_mem_unmap __P((void *, bus_mem_handle_t, 46 bus_mem_size_t)); 47 int tc_mem_subregion __P((void *, bus_mem_handle_t, bus_mem_size_t, 48 bus_mem_size_t, bus_mem_handle_t *)); 49 u_int8_t tc_mem_read_1 __P((void *, bus_mem_handle_t, 50 bus_mem_size_t)); 51 u_int16_t tc_mem_read_2 __P((void *, bus_mem_handle_t, 52 bus_mem_size_t)); 53 u_int32_t tc_mem_read_4 __P((void *, bus_mem_handle_t, 54 bus_mem_size_t)); 55 u_int64_t tc_mem_read_8 __P((void *, bus_mem_handle_t, 56 bus_mem_size_t)); 57 void tc_mem_write_1 __P((void *, bus_mem_handle_t, 58 bus_mem_size_t, u_int8_t)); 59 void tc_mem_write_2 __P((void *, bus_mem_handle_t, 60 bus_mem_size_t, u_int16_t)); 61 void tc_mem_write_4 __P((void *, bus_mem_handle_t, 62 bus_mem_size_t, u_int32_t)); 63 void tc_mem_write_8 __P((void *, bus_mem_handle_t, 64 bus_mem_size_t, u_int64_t)); 65 66 /* XXX DOES NOT BELONG */ 67 vm_offset_t tc_XXX_dmamap __P((void *)); 68 69 void 70 tc_bus_mem_init(bc, memv) 71 bus_chipset_tag_t bc; 72 void *memv; 73 { 74 75 bc->bc_m_v = memv; 76 77 bc->bc_m_map = tc_mem_map; 78 bc->bc_m_unmap = tc_mem_unmap; 79 bc->bc_m_subregion = tc_mem_subregion; 80 81 bc->bc_mr1 = tc_mem_read_1; 82 bc->bc_mr2 = tc_mem_read_2; 83 bc->bc_mr4 = tc_mem_read_4; 84 bc->bc_mr8 = tc_mem_read_8; 85 86 bc->bc_mw1 = tc_mem_write_1; 87 bc->bc_mw2 = tc_mem_write_2; 88 bc->bc_mw4 = tc_mem_write_4; 89 bc->bc_mw8 = tc_mem_write_8; 90 91 /* XXX DOES NOT BELONG */ 92 bc->bc_XXX_dmamap = tc_XXX_dmamap; 93 } 94 95 int 96 tc_mem_map(v, memaddr, memsize, cacheable, memhp) 97 void *v; 98 bus_mem_addr_t memaddr; 99 bus_mem_size_t memsize; 100 int cacheable; 101 bus_mem_handle_t *memhp; 102 { 103 104 if (memaddr & 0x7) 105 panic("tc_mem_map needs 8 byte alignment"); 106 if (cacheable) 107 *memhp = phystok0seg(memaddr); 108 else 109 *memhp = phystok0seg(TC_DENSE_TO_SPARSE(memaddr)); 110 return (0); 111 } 112 113 void 114 tc_mem_unmap(v, memh, memsize) 115 void *v; 116 bus_mem_handle_t memh; 117 bus_mem_size_t memsize; 118 { 119 120 /* XXX nothing to do. */ 121 } 122 123 int 124 tc_mem_subregion(v, memh, offset, size, nmemh) 125 void *v; 126 bus_mem_handle_t memh, *nmemh; 127 bus_mem_size_t offset, size; 128 { 129 130 /* Disallow subregioning that would make the handle unaligned. */ 131 if ((offset & 0x7) != 0) 132 return (1); 133 134 if ((memh & TC_SPACE_SPARSE) != 0) 135 *nmemh = memh + (offset << 1); 136 else 137 *nmemh = memh + offset; 138 139 return (0); 140 } 141 142 u_int8_t 143 tc_mem_read_1(v, memh, off) 144 void *v; 145 bus_mem_handle_t memh; 146 bus_mem_size_t off; 147 { 148 volatile u_int8_t *p; 149 150 wbflush(); 151 152 if ((memh & TC_SPACE_SPARSE) != 0) 153 panic("tc_mem_read_1 not implemented for sparse space"); 154 155 p = (u_int8_t *)(memh + off); 156 return (*p); 157 } 158 159 u_int16_t 160 tc_mem_read_2(v, memh, off) 161 void *v; 162 bus_mem_handle_t memh; 163 bus_mem_size_t off; 164 { 165 volatile u_int16_t *p; 166 167 wbflush(); 168 169 if ((memh & TC_SPACE_SPARSE) != 0) 170 panic("tc_mem_read_2 not implemented for sparse space"); 171 172 p = (u_int16_t *)(memh + off); 173 return (*p); 174 } 175 176 u_int32_t 177 tc_mem_read_4(v, memh, off) 178 void *v; 179 bus_mem_handle_t memh; 180 bus_mem_size_t off; 181 { 182 volatile u_int32_t *p; 183 184 wbflush(); 185 186 if ((memh & TC_SPACE_SPARSE) != 0) 187 /* Nothing special to do for 4-byte sparse space accesses */ 188 p = (u_int32_t *)(memh + (off << 1)); 189 else 190 p = (u_int32_t *)(memh + off); 191 return (*p); 192 } 193 194 u_int64_t 195 tc_mem_read_8(v, memh, off) 196 void *v; 197 bus_mem_handle_t memh; 198 bus_mem_size_t off; 199 { 200 volatile u_int64_t *p; 201 202 wbflush(); 203 204 if ((memh & TC_SPACE_SPARSE) != 0) 205 panic("tc_mem_read_8 not implemented for sparse space"); 206 207 p = (u_int64_t *)(memh + off); 208 return (*p); 209 } 210 211 void 212 tc_mem_write_1(v, memh, off, val) 213 void *v; 214 bus_mem_handle_t memh; 215 bus_mem_size_t off; 216 u_int8_t val; 217 { 218 219 if ((memh & TC_SPACE_SPARSE) != 0) { 220 volatile u_int64_t *p, v; 221 u_int64_t shift, msk; 222 223 shift = off & 0x3; 224 off &= 0x3; 225 226 p = (u_int64_t *)(memh + (off << 1)); 227 228 msk = ~(0x1 << shift) & 0xf; 229 v = (msk << 32) | (((u_int64_t)val) << (shift * 8)); 230 231 *p = val; 232 } else { 233 volatile u_int8_t *p; 234 235 p = (u_int8_t *)(memh + off); 236 *p = val; 237 } 238 wbflush(); 239 } 240 241 void 242 tc_mem_write_2(v, memh, off, val) 243 void *v; 244 bus_mem_handle_t memh; 245 bus_mem_size_t off; 246 u_int16_t val; 247 { 248 249 if ((memh & TC_SPACE_SPARSE) != 0) { 250 volatile u_int64_t *p, v; 251 u_int64_t shift, msk; 252 253 shift = off & 0x2; 254 off &= 0x3; 255 256 p = (u_int64_t *)(memh + (off << 1)); 257 258 msk = ~(0x3 << shift) & 0xf; 259 v = (msk << 32) | (((u_int64_t)val) << (shift * 8)); 260 261 *p = val; 262 } else { 263 volatile u_int16_t *p; 264 265 p = (u_int16_t *)(memh + off); 266 *p = val; 267 } 268 wbflush(); 269 } 270 271 void 272 tc_mem_write_4(v, memh, off, val) 273 void *v; 274 bus_mem_handle_t memh; 275 bus_mem_size_t off; 276 u_int32_t val; 277 { 278 volatile u_int32_t *p; 279 280 if ((memh & TC_SPACE_SPARSE) != 0) 281 /* Nothing special to do for 4-byte sparse space accesses */ 282 p = (u_int32_t *)(memh + (off << 1)); 283 else 284 p = (u_int32_t *)(memh + off); 285 *p = val; 286 wbflush(); 287 } 288 289 void 290 tc_mem_write_8(v, memh, off, val) 291 void *v; 292 bus_mem_handle_t memh; 293 bus_mem_size_t off; 294 u_int64_t val; 295 { 296 volatile u_int64_t *p; 297 298 if ((memh & TC_SPACE_SPARSE) != 0) 299 panic("tc_mem_read_8 not implemented for sparse space"); 300 301 p = (u_int64_t *)(memh + off); 302 *p = val; 303 wbflush(); 304 } 305 306 /* XXX DOES NOT BELONG */ 307 vm_offset_t 308 tc_XXX_dmamap(addr) 309 void *addr; 310 { 311 312 return (vtophys(addr)); 313 } 314
Indexes created Mon Sep 29 21:09:56 GMT 2025