acpi_wakecode.S revision 1.4.2.1
1 1.4.2.1 wrstuden /* $NetBSD: acpi_wakecode.S,v 1.4.2.1 2008/06/23 04:30:05 wrstuden Exp $ */ 2 1.2 jmcneill 3 1.2 jmcneill /*- 4 1.2 jmcneill * Copyright (c) 2007 Joerg Sonnenberger <joerg (at) netbsd.org> 5 1.2 jmcneill * 6 1.2 jmcneill * Copyright (c) 2002 The NetBSD Foundation, Inc. 7 1.2 jmcneill * All rights reserved. 8 1.2 jmcneill * 9 1.2 jmcneill * This code is derived from software contributed to The NetBSD Foundation 10 1.2 jmcneill * by Takuya SHIOZAKI. 11 1.2 jmcneill * 12 1.2 jmcneill * Redistribution and use in source and binary forms, with or without 13 1.2 jmcneill * modification, are permitted provided that the following conditions 14 1.2 jmcneill * are met: 15 1.2 jmcneill * 1. Redistributions of source code must retain the above copyright 16 1.2 jmcneill * notice, this list of conditions and the following disclaimer. 17 1.2 jmcneill * 2. Redistributions in binary form must reproduce the above copyright 18 1.2 jmcneill * notice, this list of conditions and the following disclaimer in the 19 1.2 jmcneill * documentation and/or other materials provided with the distribution. 20 1.2 jmcneill * 21 1.2 jmcneill * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 22 1.2 jmcneill * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 23 1.2 jmcneill * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 24 1.2 jmcneill * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 25 1.2 jmcneill * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 26 1.2 jmcneill * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 27 1.2 jmcneill * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 28 1.2 jmcneill * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 29 1.2 jmcneill * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 30 1.2 jmcneill * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 31 1.2 jmcneill * POSSIBILITY OF SUCH DAMAGE. 32 1.2 jmcneill */ 33 1.2 jmcneill 34 1.2 jmcneill 35 1.2 jmcneill /* 36 1.2 jmcneill * This code is derived from FreeBSD. Original copyrights: 37 1.2 jmcneill * 38 1.2 jmcneill * Copyright (c) 2001 Takanori Watanabe <takawata (at) jp.freebsd.org> 39 1.2 jmcneill * Copyright (c) 2001 Mitsuru IWASAKI <iwasaki (at) jp.freebsd.org> 40 1.2 jmcneill * All rights reserved. 41 1.2 jmcneill * 42 1.2 jmcneill * Redistribution and use in source and binary forms, with or without 43 1.2 jmcneill * modification, are permitted provided that the following conditions 44 1.2 jmcneill * are met: 45 1.2 jmcneill * 1. Redistributions of source code must retain the above copyright 46 1.2 jmcneill * notice, this list of conditions and the following disclaimer. 47 1.2 jmcneill * 2. Redistributions in binary form must reproduce the above copyright 48 1.2 jmcneill * notice, this list of conditions and the following disclaimer in the 49 1.2 jmcneill * documentation and/or other materials provided with the distribution. 50 1.2 jmcneill * 51 1.2 jmcneill * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 52 1.2 jmcneill * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 53 1.2 jmcneill * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 54 1.2 jmcneill * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 55 1.2 jmcneill * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 56 1.2 jmcneill * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 57 1.2 jmcneill * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 58 1.2 jmcneill * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 59 1.2 jmcneill * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 60 1.2 jmcneill * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 61 1.2 jmcneill * SUCH DAMAGE. 62 1.2 jmcneill * 63 1.2 jmcneill * FreeBSD: src/sys/i386/acpica/acpi_wakecode.S,v 1.1 2001/07/20 06:07:31 takawata Exp 64 1.2 jmcneill */ 65 1.2 jmcneill 66 1.2 jmcneill #define _LOCORE 67 1.2 jmcneill 68 1.2 jmcneill #include <machine/psl.h> 69 1.3 joerg #include <machine/segments.h> 70 1.2 jmcneill #include <machine/specialreg.h> 71 1.2 jmcneill 72 1.2 jmcneill #define ACPI_WAKEUP_ADDR 0x3000 73 1.2 jmcneill 74 1.2 jmcneill .text 75 1.2 jmcneill .code16 76 1.2 jmcneill .org 0 /* ACPI spec says: cs==(phys>>8), ip==(phys&0x000F) */ 77 1.2 jmcneill .globl wakeup_16 78 1.2 jmcneill wakeup_16: 79 1.2 jmcneill nop 80 1.2 jmcneill cli 81 1.2 jmcneill cld 82 1.2 jmcneill 83 1.2 jmcneill /* Set up segment registers for real mode */ 84 1.2 jmcneill movw %cs,%ax 85 1.2 jmcneill movw %ax,%ds 86 1.2 jmcneill movw %ax,%ss 87 1.2 jmcneill 88 1.2 jmcneill /* Small call stack */ 89 1.2 jmcneill mov $0x1000,%sp 90 1.2 jmcneill 91 1.2 jmcneill /* Clear flags */ 92 1.2 jmcneill pushl $0 93 1.2 jmcneill popfl 94 1.2 jmcneill 95 1.2 jmcneill /* Only beep on reset if machdep.acpi_beep_on_reset=1 */ 96 1.2 jmcneill cmpb $1,WAKEUP_beep_on_reset 97 1.2 jmcneill jne 1f 98 1.2 jmcneill movb $0xc0,%al 99 1.2 jmcneill outb %al,$0x42 100 1.2 jmcneill movb $0x04,%al 101 1.2 jmcneill outb %al,$0x42 102 1.2 jmcneill inb $0x61,%al 103 1.2 jmcneill orb $0x3,%al 104 1.2 jmcneill outb %al,$0x61 105 1.2 jmcneill 1: 106 1.2 jmcneill 107 1.2 jmcneill /* Only reset the VBIOS if machdep.acpi_vbios_reset=1 */ 108 1.2 jmcneill cmpb $1,WAKEUP_vbios_reset 109 1.2 jmcneill jne 1f 110 1.2 jmcneill 111 1.2 jmcneill /* Kick the VBIOS. */ 112 1.2 jmcneill lcall $0xc000,$3 113 1.2 jmcneill 114 1.2 jmcneill /* Reset registers in case the VBIOS changed them. */ 115 1.2 jmcneill movw %cs,%ax 116 1.2 jmcneill movw %ax,%ds 117 1.2 jmcneill movw %ax,%ss 118 1.2 jmcneill 1: 119 1.2 jmcneill 120 1.2 jmcneill /* Disable beep again if machdep.acpi_beep_on_reset=1 */ 121 1.2 jmcneill cmpb $1,WAKEUP_beep_on_reset 122 1.2 jmcneill jne 1f 123 1.2 jmcneill inb $0x61,%al 124 1.2 jmcneill andb $0xfc,%al 125 1.2 jmcneill outb %al,$0x61 126 1.2 jmcneill 1: 127 1.2 jmcneill 128 1.2 jmcneill /* Load temporary 32bit GDT */ 129 1.2 jmcneill data32 addr32 lgdt tmp_gdt 130 1.2 jmcneill 131 1.2 jmcneill /* Enable protected mode w/o paging */ 132 1.2 jmcneill mov %cr0,%eax 133 1.2 jmcneill orl $(CR0_PE),%eax 134 1.2 jmcneill mov %eax,%cr0 135 1.2 jmcneill 136 1.2 jmcneill wakeup_sw32: 137 1.2 jmcneill /* 138 1.2 jmcneill * Switch to protected mode by intersegmental jump. 139 1.2 jmcneill * Target and everything else has to compensate for the new origin 140 1.2 jmcneill * as this is using the flat memory model now. 141 1.2 jmcneill */ 142 1.2 jmcneill 143 1.2 jmcneill ljmpl $0x8,$wakeup_32 + ACPI_WAKEUP_ADDR 144 1.2 jmcneill 145 1.2 jmcneill .code32 146 1.2 jmcneill .align 16 147 1.2 jmcneill wakeup_32: 148 1.2 jmcneill /* 149 1.2 jmcneill * Switched to protected mode w/o paging 150 1.2 jmcneill */ 151 1.2 jmcneill 152 1.2 jmcneill nop 153 1.2 jmcneill /* Set up segment registers and initial stack for protected mode */ 154 1.2 jmcneill movw $0x10, %ax 155 1.2 jmcneill movw %ax,%ds 156 1.2 jmcneill movw %ax,%ss 157 1.2 jmcneill 158 1.2 jmcneill movl $(ACPI_WAKEUP_ADDR + 4096),%esp 159 1.2 jmcneill 160 1.2 jmcneill /* First, reset the PSL. */ 161 1.2 jmcneill pushl $PSL_MBO 162 1.2 jmcneill popfl 163 1.2 jmcneill 164 1.2 jmcneill /* Enable PAE and potentially PSE */ 165 1.2 jmcneill movl $(CR4_PAE|CR4_OSFXSR|CR4_OSXMMEXCPT|CR4_PSE),%eax 166 1.2 jmcneill movl %eax,%cr4 167 1.2 jmcneill 168 1.4.2.1 wrstuden /* 169 1.4.2.1 wrstuden * First switch to Long Mode. Do not restore the original 170 1.4.2.1 wrstuden * MSR EFER value directly, as enabling the NX bit without 171 1.4.2.1 wrstuden * paging will result in a GPF on AMD CPUs. 172 1.4.2.1 wrstuden * 173 1.4.2.1 wrstuden * Load the correct MSR EFER value now to not depend on the 174 1.4.2.1 wrstuden * data segment register directly after switching to Long Mode. 175 1.4.2.1 wrstuden * After this point, no instruction is allowed to clobber %ebx. 176 1.4.2.1 wrstuden */ 177 1.4.2.1 wrstuden movl WAKEUP_efer + ACPI_WAKEUP_ADDR,%ebx 178 1.2 jmcneill movl $MSR_EFER,%ecx 179 1.2 jmcneill rdmsr 180 1.4.2.1 wrstuden orl $EFER_LME, %eax 181 1.2 jmcneill wrmsr 182 1.2 jmcneill 183 1.2 jmcneill /* Load temporary PML4, code will switch to full PML4 later */ 184 1.2 jmcneill movl WAKEUP_r_cr3 + ACPI_WAKEUP_ADDR,%eax 185 1.2 jmcneill movl %eax,%cr3 186 1.2 jmcneill 187 1.2 jmcneill /* Enable paging */ 188 1.2 jmcneill movl %cr0,%eax 189 1.2 jmcneill orl $(CR0_PE|CR0_PG|CR0_NE|CR0_TS|CR0_MP|CR0_WP),%eax 190 1.2 jmcneill movl %eax,%cr0 191 1.2 jmcneill /* Flush prefetch queue */ 192 1.2 jmcneill jmp 1f 193 1.2 jmcneill 1: 194 1.2 jmcneill /* Switch to temporary 64bit GDT */ 195 1.2 jmcneill lgdt tmp_gdt64 + ACPI_WAKEUP_ADDR 196 1.2 jmcneill 197 1.2 jmcneill /* Switch to long mode using intersegmental jump. */ 198 1.2 jmcneill ljmp $0x8, $wakeup_64 + ACPI_WAKEUP_ADDR 199 1.2 jmcneill 200 1.2 jmcneill .code64 201 1.2 jmcneill wakeup_64: 202 1.2 jmcneill 203 1.4.2.1 wrstuden /* 204 1.4.2.1 wrstuden * Load the normal system value of MSR EFER. This includes 205 1.4.2.1 wrstuden * enabling the SYSCALL extension and NXE (if supported). 206 1.4.2.1 wrstuden */ 207 1.4.2.1 wrstuden movl %ebx, %eax 208 1.4.2.1 wrstuden movl $MSR_EFER,%ecx 209 1.4.2.1 wrstuden wrmsr 210 1.4.2.1 wrstuden 211 1.3 joerg /* Reload data segment with default value */ 212 1.2 jmcneill movw $GSEL(GDATA_SEL, SEL_KPL),%ax 213 1.2 jmcneill movw %ax,%ds 214 1.2 jmcneill 215 1.3 joerg movq WAKEUP_curcpu + ACPI_WAKEUP_ADDR,%r8 216 1.2 jmcneill movq WAKEUP_restorecpu + ACPI_WAKEUP_ADDR,%rbx 217 1.2 jmcneill 218 1.2 jmcneill /* Continue with wakeup in the high-level wakeup code */ 219 1.2 jmcneill jmp *%rbx 220 1.2 jmcneill 221 1.2 jmcneill .align 8 222 1.2 jmcneill tmp_gdt: 223 1.2 jmcneill .word 0xffff 224 1.2 jmcneill .long tmp_gdtable + ACPI_WAKEUP_ADDR 225 1.2 jmcneill 226 1.2 jmcneill .align 8, 0 227 1.2 jmcneill tmp_gdtable: 228 1.2 jmcneill /* null */ 229 1.2 jmcneill .word 0, 0 230 1.2 jmcneill .byte 0, 0, 0, 0 231 1.2 jmcneill /* code */ 232 1.2 jmcneill .word 0xffff, 0 233 1.2 jmcneill .byte 0, 0x9f, 0xcf, 0 234 1.2 jmcneill /* data */ 235 1.2 jmcneill .word 0xffff, 0 236 1.2 jmcneill .byte 0, 0x93, 0xcf, 0 237 1.2 jmcneill 238 1.2 jmcneill tmp_gdt64: 239 1.2 jmcneill .word 0xffff 240 1.2 jmcneill .long tmp_gdtable64 + ACPI_WAKEUP_ADDR 241 1.2 jmcneill 242 1.2 jmcneill tmp_gdtable64: 243 1.2 jmcneill .quad 0x0000000000000000 244 1.2 jmcneill .quad 0x00af9a000000ffff 245 1.2 jmcneill .quad 0x00cf92000000ffff 246 1.2 jmcneill 247 1.2 jmcneill .align 16, 0 248 1.2 jmcneill .global WAKEUP_r_cr3 249 1.2 jmcneill WAKEUP_r_cr3: .quad 0 250 1.2 jmcneill 251 1.2 jmcneill .global WAKEUP_restorecpu 252 1.2 jmcneill WAKEUP_restorecpu: .quad 0 253 1.2 jmcneill 254 1.2 jmcneill .global WAKEUP_vbios_reset 255 1.2 jmcneill WAKEUP_vbios_reset: .byte 0 256 1.2 jmcneill .global WAKEUP_beep_on_reset 257 1.2 jmcneill WAKEUP_beep_on_reset: .byte 0 258 1.3 joerg 259 1.3 joerg .global WAKEUP_curcpu 260 1.3 joerg WAKEUP_curcpu: .quad 0 261 1.4.2.1 wrstuden .global WAKEUP_efer 262 1.4.2.1 wrstuden WAKEUP_efer: .long 0 263
Indexes created Thu Oct 02 14:10:14 GMT 2025