1 1.1 fvdl /* $NetBSD: fpu.h,v 1.1 2003/04/26 18:39:40 fvdl Exp $ */ 2 1.1 fvdl 3 1.1 fvdl #ifndef _AMD64_FPU_H_ 4 1.1 fvdl #define _AMD64_FPU_H_ 5 1.1 fvdl 6 1.1 fvdl /* 7 1.1 fvdl * NetBSD/amd64 only uses the extended save/restore format used 8 1.1 fvdl * by fxsave/fsrestore, to always deal with the SSE registers, 9 1.1 fvdl * which are part of the ABI to pass floating point values. 10 1.1 fvdl * Must be stored in memory on a 16-byte boundary. 11 1.1 fvdl */ 12 1.1 fvdl 13 1.1 fvdl struct fxsave64 { 14 1.1 fvdl u_int16_t fx_fcw; 15 1.1 fvdl u_int16_t fx_fsw; 16 1.1 fvdl u_int8_t fx_ftw; 17 1.1 fvdl u_int8_t fx_unused1; 18 1.1 fvdl u_int16_t fx_fop; 19 1.1 fvdl u_int64_t fx_rip; 20 1.1 fvdl u_int64_t fx_rdp; 21 1.1 fvdl u_int32_t fx_mxcsr; 22 1.1 fvdl u_int32_t fx_mxcsr_mask; 23 1.1 fvdl u_int64_t fx_st[8][2]; /* 8 normal FP regs */ 24 1.1 fvdl u_int64_t fx_xmm[16][2]; /* 16 SSE2 registers */ 25 1.1 fvdl u_int8_t fx_unused3[96]; 26 1.1 fvdl } __attribute__((packed)); 27 1.1 fvdl 28 1.1 fvdl struct savefpu { 29 1.1 fvdl struct fxsave64 fp_fxsave; /* see above */ 30 1.1 fvdl u_int16_t fp_ex_sw; /* saved status from last exception */ 31 1.1 fvdl u_int16_t fp_ex_tw; /* saved tag from last exception */ 32 1.1 fvdl }; 33 1.1 fvdl 34 1.1 fvdl #ifdef _KERNEL 35 1.1 fvdl 36 1.1 fvdl /* 37 1.1 fvdl * This one only used for backward compat coredumping. 38 1.1 fvdl */ 39 1.1 fvdl struct oldfsave { 40 1.1 fvdl u_int16_t fs_control; 41 1.1 fvdl u_int16_t fs_unused0; 42 1.1 fvdl u_int16_t fs_status; 43 1.1 fvdl u_int16_t fs_unused1; 44 1.1 fvdl u_int16_t fs_tag; 45 1.1 fvdl u_int16_t fs_unused2; 46 1.1 fvdl u_int32_t fs_ipoff; 47 1.1 fvdl u_int16_t fs_ipsel; 48 1.1 fvdl u_int16_t fs_op; 49 1.1 fvdl u_int32_t fs_opoff; 50 1.1 fvdl u_int16_t fs_opsel; 51 1.1 fvdl } __attribute__ ((packed)); 52 1.1 fvdl 53 1.1 fvdl #endif 54 1.1 fvdl 55 1.1 fvdl 56 1.1 fvdl /* 57 1.1 fvdl * The i387 defaults to Intel extended precision mode and round to nearest, 58 1.1 fvdl * with all exceptions masked. 59 1.1 fvdl */ 60 1.1 fvdl #define __INITIAL_NPXCW__ 0x037f 61 1.1 fvdl #define __INITIAL_MXCSR__ 0x1f80 62 1.1 fvdl #define __INITIAL_MXCSR_MASK__ 0xffbf 63 1.1 fvdl 64 1.1 fvdl /* NetBSD uses IEEE double precision. */ 65 1.1 fvdl #define __NetBSD_NPXCW__ 0x127f 66 1.1 fvdl /* Linux just uses the default control word. */ 67 1.1 fvdl #define __Linux_NPXCW__ 0x037f 68 1.1 fvdl 69 1.1 fvdl /* 70 1.1 fvdl * The standard control word from finit is 0x37F, giving: 71 1.1 fvdl * round to nearest 72 1.1 fvdl * 64-bit precision 73 1.1 fvdl * all exceptions masked. 74 1.1 fvdl * 75 1.1 fvdl * Now we want: 76 1.1 fvdl * affine mode (if we decide to support 287's) 77 1.1 fvdl * round to nearest 78 1.1 fvdl * 53-bit precision 79 1.1 fvdl * all exceptions masked. 80 1.1 fvdl * 81 1.1 fvdl * 64-bit precision often gives bad results with high level languages 82 1.1 fvdl * because it makes the results of calculations depend on whether 83 1.1 fvdl * intermediate values are stored in memory or in FPU registers. 84 1.1 fvdl */ 85 1.1 fvdl 86 1.1 fvdl #ifdef _KERNEL 87 1.1 fvdl /* 88 1.1 fvdl * XXX 89 1.1 fvdl */ 90 1.1 fvdl struct trapframe; 91 1.1 fvdl struct cpu_info; 92 1.1 fvdl 93 1.1 fvdl void fpuinit(struct cpu_info *); 94 1.1 fvdl void fpudrop(void); 95 1.1 fvdl void fpusave(struct lwp *); 96 1.1 fvdl void fpudiscard(struct lwp *); 97 1.1 fvdl void fputrap(struct trapframe *); 98 1.1 fvdl void fpusave_lwp(struct lwp *, int); 99 1.1 fvdl void fpusave_cpu(struct cpu_info *, int); 100 1.1 fvdl 101 1.1 fvdl #endif 102 1.1 fvdl 103 1.1 fvdl #endif /* _AMD64_FPU_H_ */ 104