frameasm.h revision 1.24
1 /* $NetBSD: frameasm.h,v 1.24 2018/01/07 12:42:46 maxv Exp $ */ 2 3 #ifndef _AMD64_MACHINE_FRAMEASM_H 4 #define _AMD64_MACHINE_FRAMEASM_H 5 6 #ifdef _KERNEL_OPT 7 #include "opt_xen.h" 8 #endif 9 10 /* 11 * Macros to define pushing/popping frames for interrupts, traps 12 * and system calls. Currently all the same; will diverge later. 13 */ 14 15 #ifdef XEN 16 #define HYPERVISOR_iret hypercall_page + (__HYPERVISOR_iret * 32) 17 /* Xen do not need swapgs, done by hypervisor */ 18 #define swapgs 19 #define iretq pushq $0 ; jmp HYPERVISOR_iret 20 #define XEN_ONLY2(x,y) x,y 21 #define NOT_XEN(x) 22 23 #define CLI(temp_reg) \ 24 movq CPUVAR(VCPU),%r ## temp_reg ; \ 25 movb $1,EVTCHN_UPCALL_MASK(%r ## temp_reg); 26 27 #define STI(temp_reg) \ 28 movq CPUVAR(VCPU),%r ## temp_reg ; \ 29 movb $0,EVTCHN_UPCALL_MASK(%r ## temp_reg); 30 31 #else /* XEN */ 32 #define XEN_ONLY2(x,y) 33 #define NOT_XEN(x) x 34 #define CLI(temp_reg) cli 35 #define STI(temp_reg) sti 36 #endif /* XEN */ 37 38 #define HP_NAME_CLAC 1 39 #define HP_NAME_STAC 2 40 41 #define HOTPATCH(name, size) \ 42 123: ; \ 43 .section .rodata.hotpatch, "a" ; \ 44 .byte name ; \ 45 .byte size ; \ 46 .quad 123b ; \ 47 .previous 48 49 #define SMAP_ENABLE \ 50 HOTPATCH(HP_NAME_CLAC, 3) ; \ 51 .byte 0x0F, 0x1F, 0x00 ; \ 52 53 #define SMAP_DISABLE \ 54 HOTPATCH(HP_NAME_STAC, 3) ; \ 55 .byte 0x0F, 0x1F, 0x00 ; \ 56 57 #define SWAPGS NOT_XEN(swapgs) 58 59 /* 60 * These are used on interrupt or trap entry or exit. 61 */ 62 #define INTR_SAVE_GPRS \ 63 movq %rdi,TF_RDI(%rsp) ; \ 64 movq %rsi,TF_RSI(%rsp) ; \ 65 movq %rdx,TF_RDX(%rsp) ; \ 66 movq %rcx,TF_RCX(%rsp) ; \ 67 movq %r8,TF_R8(%rsp) ; \ 68 movq %r9,TF_R9(%rsp) ; \ 69 movq %r10,TF_R10(%rsp) ; \ 70 movq %r11,TF_R11(%rsp) ; \ 71 movq %r12,TF_R12(%rsp) ; \ 72 movq %r13,TF_R13(%rsp) ; \ 73 movq %r14,TF_R14(%rsp) ; \ 74 movq %r15,TF_R15(%rsp) ; \ 75 movq %rbp,TF_RBP(%rsp) ; \ 76 movq %rbx,TF_RBX(%rsp) ; \ 77 movq %rax,TF_RAX(%rsp) 78 79 #define INTR_RESTORE_GPRS \ 80 movq TF_RDI(%rsp),%rdi ; \ 81 movq TF_RSI(%rsp),%rsi ; \ 82 movq TF_RDX(%rsp),%rdx ; \ 83 movq TF_RCX(%rsp),%rcx ; \ 84 movq TF_R8(%rsp),%r8 ; \ 85 movq TF_R9(%rsp),%r9 ; \ 86 movq TF_R10(%rsp),%r10 ; \ 87 movq TF_R11(%rsp),%r11 ; \ 88 movq TF_R12(%rsp),%r12 ; \ 89 movq TF_R13(%rsp),%r13 ; \ 90 movq TF_R14(%rsp),%r14 ; \ 91 movq TF_R15(%rsp),%r15 ; \ 92 movq TF_RBP(%rsp),%rbp ; \ 93 movq TF_RBX(%rsp),%rbx ; \ 94 movq TF_RAX(%rsp),%rax 95 96 #define INTRENTRY_L(kernel_trap, usertrap) \ 97 subq $TF_REGSIZE,%rsp ; \ 98 INTR_SAVE_GPRS ; \ 99 cld ; \ 100 SMAP_ENABLE ; \ 101 testb $SEL_UPL,TF_CS(%rsp) ; \ 102 je kernel_trap ; \ 103 usertrap ; \ 104 SWAPGS ; \ 105 movw %gs,TF_GS(%rsp) ; \ 106 movw %fs,TF_FS(%rsp) ; \ 107 movw %es,TF_ES(%rsp) ; \ 108 movw %ds,TF_DS(%rsp) 109 110 #define INTRENTRY \ 111 INTRENTRY_L(98f,) ; \ 112 98: 113 114 #define INTRFASTEXIT \ 115 jmp intrfastexit 116 117 #define INTR_RECURSE_HWFRAME \ 118 movq %rsp,%r10 ; \ 119 movl %ss,%r11d ; \ 120 pushq %r11 ; \ 121 pushq %r10 ; \ 122 pushfq ; \ 123 movl %cs,%r11d ; \ 124 pushq %r11 ; \ 125 /* XEN: We must fixup CS, as even kernel mode runs at CPL 3 */ \ 126 XEN_ONLY2(andb $0xfc,(%rsp);) \ 127 pushq %r13 ; 128 129 #define DO_DEFERRED_SWITCH \ 130 cmpl $0, CPUVAR(WANT_PMAPLOAD) ; \ 131 jz 1f ; \ 132 call _C_LABEL(do_pmap_load) ; \ 133 1: 134 135 #define CHECK_DEFERRED_SWITCH \ 136 cmpl $0, CPUVAR(WANT_PMAPLOAD) 137 138 #define CHECK_ASTPENDING(reg) cmpl $0, L_MD_ASTPENDING(reg) 139 #define CLEAR_ASTPENDING(reg) movl $0, L_MD_ASTPENDING(reg) 140 141 #endif /* _AMD64_MACHINE_FRAMEASM_H */ 142
Indexes created Mon Sep 29 21:09:56 GMT 2025