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ahscreg.h revision 1.1 
      1 /*
      2  * Copyright (c) 1994 Christian E. Hopps
      3  * Copyright (c) 1982, 1990 The Regents of the University of California.
      4  * All rights reserved.
      5  *
      6  * Redistribution and use in source and binary forms, with or without
      7  * modification, are permitted provided that the following conditions
      8  * are met:
      9  * 1. Redistributions of source code must retain the above copyright
     10  *    notice, this list of conditions and the following disclaimer.
     11  * 2. Redistributions in binary form must reproduce the above copyright
     12  *    notice, this list of conditions and the following disclaimer in the
     13  *    documentation and/or other materials provided with the distribution.
     14  * 3. All advertising materials mentioning features or use of this software
     15  *    must display the following acknowledgement:
     16  *	This product includes software developed by the University of
     17  *	California, Berkeley and its contributors.
     18  * 4. Neither the name of the University nor the names of its contributors
     19  *    may be used to endorse or promote products derived from this software
     20  *    without specific prior written permission.
     21  *
     22  * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
     23  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
     24  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
     25  * ARE DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
     26  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
     27  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
     28  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
     29  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
     30  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
     31  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
     32  * SUCH DAMAGE.
     33  *
     34  *	@(#)dmareg.h
     35  *	$Id: ahscreg.h,v 1.1 1994/05/08 05:52:55 chopps Exp $
     36  */
     37 #ifndef _AMIGA_DEV_AHSCREG_H_
     38 #define _AMIGA_DEV_AHSCREG_H_
     39 
     40 /*
     41  * Hardware layout of the A3000 SDMAC. This also contains the
     42  * registers for the sbic chip, but in favor of separating DMA and
     43  * scsi, the scsi-driver doesn't make use of this dependency
     44  */
     45 
     46 #define v_char		volatile char
     47 #define	v_int		volatile int
     48 #define vu_char		volatile u_char
     49 #define vu_short	volatile u_short
     50 #define vu_int		volatile u_int
     51 
     52 struct sdmac {
     53 	short		pad0;
     54 	vu_short DAWR;		/* DACK Width Register WO */
     55 	vu_int   WTC;		/* Word Transfer Count Register RW */
     56 	short		pad1;
     57 	vu_short CNTR;		/* Control Register RW */
     58 	vu_int   ACR;		/* Address Count Register RW */
     59 	short		pad2;
     60 	vu_short ST_DMA;	/* Start DMA Transfers RW-Strobe */
     61 	short		pad3;
     62 	vu_short FLUSH;		/* Flush FIFO RW-Strobe */
     63 	short		pad4;
     64 	vu_short CINT;		/* Clear Interrupts RW-Strobe */
     65 	short		pad5;
     66 	vu_short ISTR;		/* Interrupt Status Register RO */
     67 	int		pad6[7];
     68 	short		pad7;
     69 	vu_short SP_DMA;	/* Stop DMA Transfers RW-Strobe */
     70 	char		pad8;
     71 	vu_char  SASR;		/* sbic asr */
     72 	char		pad9;
     73 	vu_char  SCMD;		/* sbic data */
     74 };
     75 
     76 /*
     77  * value to go into DAWR
     78  */
     79 #define DAWR_AHSC	3	/* according to A3000T service-manual */
     80 
     81 /*
     82  * bits defined for CNTR
     83  */
     84 #define CNTR_TCEN	(1<<5)	/* Terminal Count Enable */
     85 #define CNTR_PREST	(1<<4)	/* Perp Reset (not implemented :-((( ) */
     86 #define CNTR_PDMD	(1<<3)  /* Perp Device Mode Select (1=SCSI,0=XT/AT) */
     87 #define CNTR_INTEN	(1<<2)	/* Interrupt Enable */
     88 #define CNTR_DDIR	(1<<1)	/* Device Direction. 1==rd host, wr perp */
     89 #define CNTR_IO_DX	(1<<0)	/* IORDY & CSX1 Polarity Select */
     90 
     91 /*
     92  * bits defined for ISTR
     93  */
     94 #define ISTR_INTX	(1<<8)	/* XT/AT Interrupt pending */
     95 #define ISTR_INT_F	(1<<7)	/* Interrupt Follow */
     96 #define ISTR_INTS	(1<<6)	/* SCSI Peripheral Interrupt */
     97 #define ISTR_E_INT	(1<<5)	/* End-Of-Process Interrupt */
     98 #define ISTR_INT_P	(1<<4)	/* Interrupt Pending */
     99 #define ISTR_UE_INT	(1<<3)	/* Under-Run FIFO Error Interrupt */
    100 #define ISTR_OE_INT	(1<<2)	/* Over-Run FIFO Error Interrupt */
    101 #define ISTR_FF_FLG	(1<<1)	/* FIFO-Full Flag */
    102 #define ISTR_FE_FLG	(1<<0)	/* FIFO-Empty Flag */
    103 
    104 #endif /* _AMIGA_DEV_AHSCREG_H_ */
    105