bzivsc.c revision 1.8
1 /* $NetBSD: bzivsc.c,v 1.8 1999/09/30 22:59:52 thorpej Exp $ */ 2 3 /* 4 * Copyright (c) 1997 Michael L. Hitch 5 * Copyright (c) 1982, 1990 The Regents of the University of California. 6 * All rights reserved. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 3. All advertising materials mentioning features or use of this software 17 * must display the following acknowledgement: 18 * This product contains software written by Michael L. Hitch for 19 * the NetBSD project. 20 * 4. Neither the name of the University nor the names of its contributors 21 * may be used to endorse or promote products derived from this software 22 * without specific prior written permission. 23 * 24 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 25 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 26 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 27 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 28 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 29 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 30 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 31 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 32 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 33 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 34 * SUCH DAMAGE. 35 * 36 */ 37 38 #include <sys/types.h> 39 #include <sys/param.h> 40 #include <sys/systm.h> 41 #include <sys/kernel.h> 42 #include <sys/errno.h> 43 #include <sys/ioctl.h> 44 #include <sys/device.h> 45 #include <sys/buf.h> 46 #include <sys/proc.h> 47 #include <sys/user.h> 48 #include <sys/queue.h> 49 50 #include <dev/scsipi/scsi_all.h> 51 #include <dev/scsipi/scsipi_all.h> 52 #include <dev/scsipi/scsiconf.h> 53 #include <dev/scsipi/scsi_message.h> 54 55 #include <machine/cpu.h> 56 #include <machine/param.h> 57 58 #include <dev/ic/ncr53c9xreg.h> 59 #include <dev/ic/ncr53c9xvar.h> 60 61 #include <amiga/amiga/isr.h> 62 #include <amiga/dev/bzivscvar.h> 63 #include <amiga/dev/zbusvar.h> 64 65 void bzivscattach __P((struct device *, struct device *, void *)); 66 int bzivscmatch __P((struct device *, struct cfdata *, void *)); 67 68 /* Linkup to the rest of the kernel */ 69 struct cfattach bzivsc_ca = { 70 sizeof(struct bzivsc_softc), bzivscmatch, bzivscattach 71 }; 72 73 struct scsipi_device bzivsc_dev = { 74 NULL, /* Use default error handler */ 75 NULL, /* have a queue, served by this */ 76 NULL, /* have no async handler */ 77 NULL, /* Use default 'done' routine */ 78 }; 79 80 /* 81 * Functions and the switch for the MI code. 82 */ 83 u_char bzivsc_read_reg __P((struct ncr53c9x_softc *, int)); 84 void bzivsc_write_reg __P((struct ncr53c9x_softc *, int, u_char)); 85 int bzivsc_dma_isintr __P((struct ncr53c9x_softc *)); 86 void bzivsc_dma_reset __P((struct ncr53c9x_softc *)); 87 int bzivsc_dma_intr __P((struct ncr53c9x_softc *)); 88 int bzivsc_dma_setup __P((struct ncr53c9x_softc *, caddr_t *, 89 size_t *, int, size_t *)); 90 void bzivsc_dma_go __P((struct ncr53c9x_softc *)); 91 void bzivsc_dma_stop __P((struct ncr53c9x_softc *)); 92 int bzivsc_dma_isactive __P((struct ncr53c9x_softc *)); 93 94 struct ncr53c9x_glue bzivsc_glue = { 95 bzivsc_read_reg, 96 bzivsc_write_reg, 97 bzivsc_dma_isintr, 98 bzivsc_dma_reset, 99 bzivsc_dma_intr, 100 bzivsc_dma_setup, 101 bzivsc_dma_go, 102 bzivsc_dma_stop, 103 bzivsc_dma_isactive, 104 0, 105 }; 106 107 /* Maximum DMA transfer length to reduce impact on high-speed serial input */ 108 u_long bzivsc_max_dma = 1024; 109 extern int ser_open_speed; 110 111 u_long bzivsc_cnt_pio = 0; /* number of PIO transfers */ 112 u_long bzivsc_cnt_dma = 0; /* number of DMA transfers */ 113 u_long bzivsc_cnt_dma2 = 0; /* number of DMA transfers broken up */ 114 u_long bzivsc_cnt_dma3 = 0; /* number of pages combined */ 115 116 #ifdef DEBUG 117 struct { 118 u_char hardbits; 119 u_char status; 120 u_char xx; 121 u_char yy; 122 } bzivsc_trace[128]; 123 int bzivsc_trace_ptr = 0; 124 int bzivsc_trace_enable = 1; 125 void bzivsc_dump __P((void)); 126 #endif 127 128 /* 129 * if we are a Phase5 Blizzard 12x0-IV 130 */ 131 int 132 bzivscmatch(parent, cf, aux) 133 struct device *parent; 134 struct cfdata *cf; 135 void *aux; 136 { 137 struct zbus_args *zap; 138 volatile u_char *regs; 139 140 zap = aux; 141 if (zap->manid != 0x2140) 142 return(0); /* It's not Phase 5 */ 143 if (zap->prodid != 11 && zap->prodid != 17) 144 return(0); /* Not Blizzard 12x0 */ 145 if (!is_a1200()) 146 return(0); /* And not A1200 */ 147 regs = &((volatile u_char *)zap->va)[0x8000]; 148 if (badaddr((caddr_t)regs)) 149 return(0); 150 regs[NCR_CFG1 * 4] = 0; 151 regs[NCR_CFG1 * 4] = NCRCFG1_PARENB | 7; 152 delay(5); 153 if (regs[NCR_CFG1 * 4] != (NCRCFG1_PARENB | 7)) 154 return(0); 155 return(1); 156 } 157 158 /* 159 * Attach this instance, and then all the sub-devices 160 */ 161 void 162 bzivscattach(parent, self, aux) 163 struct device *parent, *self; 164 void *aux; 165 { 166 struct bzivsc_softc *bsc = (void *)self; 167 struct ncr53c9x_softc *sc = &bsc->sc_ncr53c9x; 168 struct zbus_args *zap; 169 extern u_long scsi_nosync; 170 extern int shift_nosync; 171 extern int ncr53c9x_debug; 172 173 /* 174 * Set up the glue for MI code early; we use some of it here. 175 */ 176 sc->sc_glue = &bzivsc_glue; 177 178 /* 179 * Save the regs 180 */ 181 zap = aux; 182 bsc->sc_reg = &((volatile u_char *)zap->va)[0x8000]; 183 bsc->sc_dmabase = &bsc->sc_reg[0x8000]; 184 185 sc->sc_freq = 40; /* Clocked at 40Mhz */ 186 187 printf(": address %p", bsc->sc_reg); 188 189 sc->sc_id = 7; 190 191 /* 192 * It is necessary to try to load the 2nd config register here, 193 * to find out what rev the FAS chip is, else the ncr53c9x_reset 194 * will not set up the defaults correctly. 195 */ 196 sc->sc_cfg1 = sc->sc_id | NCRCFG1_PARENB; 197 sc->sc_cfg2 = NCRCFG2_SCSI2 | NCRCFG2_FE; 198 sc->sc_cfg3 = 0x08 /*FCLK*/ | NCRESPCFG3_FSCSI | NCRESPCFG3_CDB; 199 sc->sc_rev = NCR_VARIANT_FAS216; 200 201 /* 202 * This is the value used to start sync negotiations 203 * Note that the NCR register "SYNCTP" is programmed 204 * in "clocks per byte", and has a minimum value of 4. 205 * The SCSI period used in negotiation is one-fourth 206 * of the time (in nanoseconds) needed to transfer one byte. 207 * Since the chip's clock is given in MHz, we have the following 208 * formula: 4 * period = (1000 / freq) * 4 209 */ 210 sc->sc_minsync = 1000 / sc->sc_freq; 211 212 /* 213 * get flags from -I argument and set cf_flags. 214 * NOTE: low 8 bits are to disable disconnect, and the next 215 * 8 bits are to disable sync. 216 */ 217 sc->sc_dev.dv_cfdata->cf_flags |= (scsi_nosync >> shift_nosync) 218 & 0xffff; 219 shift_nosync += 16; 220 221 /* Use next 16 bits of -I argument to set ncr53c9x_debug flags */ 222 ncr53c9x_debug |= (scsi_nosync >> shift_nosync) & 0xffff; 223 shift_nosync += 16; 224 225 #if 1 226 if (((scsi_nosync >> shift_nosync) & 0xff00) == 0xff00) 227 sc->sc_minsync = 0; 228 #endif 229 230 /* Really no limit, but since we want to fit into the TCR... */ 231 sc->sc_maxxfer = 64 * 1024; 232 233 /* 234 * Configure interrupts. 235 */ 236 bsc->sc_isr.isr_intr = (int (*)(void *))ncr53c9x_intr; 237 bsc->sc_isr.isr_arg = sc; 238 bsc->sc_isr.isr_ipl = 2; 239 add_isr(&bsc->sc_isr); 240 241 /* 242 * Now try to attach all the sub-devices 243 */ 244 sc->sc_adapter.scsipi_cmd = ncr53c9x_scsi_cmd; 245 sc->sc_adapter.scsipi_minphys = minphys; 246 ncr53c9x_attach(sc, &bzivsc_dev); 247 } 248 249 /* 250 * Glue functions. 251 */ 252 253 u_char 254 bzivsc_read_reg(sc, reg) 255 struct ncr53c9x_softc *sc; 256 int reg; 257 { 258 struct bzivsc_softc *bsc = (struct bzivsc_softc *)sc; 259 260 return bsc->sc_reg[reg * 4]; 261 } 262 263 void 264 bzivsc_write_reg(sc, reg, val) 265 struct ncr53c9x_softc *sc; 266 int reg; 267 u_char val; 268 { 269 struct bzivsc_softc *bsc = (struct bzivsc_softc *)sc; 270 u_char v = val; 271 272 bsc->sc_reg[reg * 4] = v; 273 #ifdef DEBUG 274 if (bzivsc_trace_enable/* && sc->sc_nexus && sc->sc_nexus->xs->xs_control & XS_CTL_POLL */ && 275 reg == NCR_CMD/* && bsc->sc_active*/) { 276 bzivsc_trace[(bzivsc_trace_ptr - 1) & 127].yy = v; 277 /* printf(" cmd %x", v);*/ 278 } 279 #endif 280 } 281 282 int 283 bzivsc_dma_isintr(sc) 284 struct ncr53c9x_softc *sc; 285 { 286 struct bzivsc_softc *bsc = (struct bzivsc_softc *)sc; 287 288 if ((bsc->sc_reg[NCR_STAT * 4] & NCRSTAT_INT) == 0) 289 return 0; 290 291 #ifdef DEBUG 292 if (/*sc->sc_nexus && sc->sc_nexus->xs->xs_control & XS_CTL_POLL &&*/ bzivsc_trace_enable) { 293 bzivsc_trace[bzivsc_trace_ptr].status = bsc->sc_reg[NCR_STAT * 4]; 294 bzivsc_trace[bzivsc_trace_ptr].xx = bsc->sc_reg[NCR_CMD * 4]; 295 bzivsc_trace[bzivsc_trace_ptr].yy = bsc->sc_active; 296 bzivsc_trace_ptr = (bzivsc_trace_ptr + 1) & 127; 297 } 298 #endif 299 return 1; 300 } 301 302 void 303 bzivsc_dma_reset(sc) 304 struct ncr53c9x_softc *sc; 305 { 306 struct bzivsc_softc *bsc = (struct bzivsc_softc *)sc; 307 308 bsc->sc_active = 0; 309 } 310 311 int 312 bzivsc_dma_intr(sc) 313 struct ncr53c9x_softc *sc; 314 { 315 register struct bzivsc_softc *bsc = (struct bzivsc_softc *)sc; 316 register int cnt; 317 318 NCR_DMA(("bzivsc_dma_intr: cnt %d int %x stat %x fifo %d ", 319 bsc->sc_dmasize, sc->sc_espintr, sc->sc_espstat, 320 bsc->sc_reg[NCR_FFLAG * 4] & NCRFIFO_FF)); 321 if (bsc->sc_active == 0) { 322 printf("bzivsc_intr--inactive DMA\n"); 323 return -1; 324 } 325 326 /* update sc_dmaaddr and sc_pdmalen */ 327 cnt = bsc->sc_reg[NCR_TCL * 4]; 328 cnt += bsc->sc_reg[NCR_TCM * 4] << 8; 329 cnt += bsc->sc_reg[NCR_TCH * 4] << 16; 330 if (!bsc->sc_datain) { 331 cnt += bsc->sc_reg[NCR_FFLAG * 4] & NCRFIFO_FF; 332 bsc->sc_reg[NCR_CMD * 4] = NCRCMD_FLUSH; 333 } 334 cnt = bsc->sc_dmasize - cnt; /* number of bytes transferred */ 335 NCR_DMA(("DMA xferred %d\n", cnt)); 336 if (bsc->sc_xfr_align) { 337 bcopy(bsc->sc_alignbuf, *bsc->sc_dmaaddr, cnt); 338 bsc->sc_xfr_align = 0; 339 } 340 *bsc->sc_dmaaddr += cnt; 341 *bsc->sc_pdmalen -= cnt; 342 bsc->sc_active = 0; 343 return 0; 344 } 345 346 int 347 bzivsc_dma_setup(sc, addr, len, datain, dmasize) 348 struct ncr53c9x_softc *sc; 349 caddr_t *addr; 350 size_t *len; 351 int datain; 352 size_t *dmasize; 353 { 354 struct bzivsc_softc *bsc = (struct bzivsc_softc *)sc; 355 paddr_t pa; 356 u_char *ptr; 357 size_t xfer; 358 359 bsc->sc_dmaaddr = addr; 360 bsc->sc_pdmalen = len; 361 bsc->sc_datain = datain; 362 bsc->sc_dmasize = *dmasize; 363 /* 364 * DMA can be nasty for high-speed serial input, so limit the 365 * size of this DMA operation if the serial port is running at 366 * a high speed (higher than 19200 for now - should be adjusted 367 * based on cpu type and speed?). 368 * XXX - add serial speed check XXX 369 */ 370 if (ser_open_speed > 19200 && bzivsc_max_dma != 0 && 371 bsc->sc_dmasize > bzivsc_max_dma) 372 bsc->sc_dmasize = bzivsc_max_dma; 373 ptr = *addr; /* Kernel virtual address */ 374 pa = kvtop(ptr); /* Physical address of DMA */ 375 xfer = min(bsc->sc_dmasize, NBPG - (pa & (NBPG - 1))); 376 bsc->sc_xfr_align = 0; 377 /* 378 * If output and unaligned, stuff odd byte into FIFO 379 */ 380 if (datain == 0 && (int)ptr & 1) { 381 NCR_DMA(("bzivsc_dma_setup: align byte written to fifo\n")); 382 pa++; 383 xfer--; /* XXXX CHECK THIS !!!! XXXX */ 384 bsc->sc_reg[NCR_FIFO * 4] = *ptr++; 385 } 386 /* 387 * If unaligned address, read unaligned bytes into alignment buffer 388 */ 389 else if ((int)ptr & 1) { 390 pa = kvtop((caddr_t)&bsc->sc_alignbuf); 391 xfer = bsc->sc_dmasize = min(xfer, sizeof (bsc->sc_alignbuf)); 392 NCR_DMA(("bzivsc_dma_setup: align read by %d bytes\n", xfer)); 393 bsc->sc_xfr_align = 1; 394 } 395 ++bzivsc_cnt_dma; /* number of DMA operations */ 396 397 while (xfer < bsc->sc_dmasize) { 398 if ((pa + xfer) != kvtop(*addr + xfer)) 399 break; 400 if ((bsc->sc_dmasize - xfer) < NBPG) 401 xfer = bsc->sc_dmasize; 402 else 403 xfer += NBPG; 404 ++bzivsc_cnt_dma3; 405 } 406 if (xfer != *len) 407 ++bzivsc_cnt_dma2; 408 409 bsc->sc_dmasize = xfer; 410 *dmasize = bsc->sc_dmasize; 411 bsc->sc_pa = pa; 412 #if defined(M68040) || defined(M68060) 413 if (mmutype == MMU_68040) { 414 if (bsc->sc_xfr_align) { 415 dma_cachectl(bsc->sc_alignbuf, 416 sizeof(bsc->sc_alignbuf)); 417 } 418 else 419 dma_cachectl(*bsc->sc_dmaaddr, bsc->sc_dmasize); 420 } 421 #endif 422 423 pa >>= 1; 424 if (!bsc->sc_datain) 425 pa |= 0x80000000; 426 bsc->sc_dmabase[0x8000] = (u_int8_t)(pa >> 24); 427 bsc->sc_dmabase[0] = (u_int8_t)(pa >> 24); 428 bsc->sc_dmabase[0] = (u_int8_t)(pa >> 16); 429 bsc->sc_dmabase[0] = (u_int8_t)(pa >> 8); 430 bsc->sc_dmabase[0] = (u_int8_t)(pa); 431 bsc->sc_active = 1; 432 return 0; 433 } 434 435 void 436 bzivsc_dma_go(sc) 437 struct ncr53c9x_softc *sc; 438 { 439 } 440 441 void 442 bzivsc_dma_stop(sc) 443 struct ncr53c9x_softc *sc; 444 { 445 } 446 447 int 448 bzivsc_dma_isactive(sc) 449 struct ncr53c9x_softc *sc; 450 { 451 struct bzivsc_softc *bsc = (struct bzivsc_softc *)sc; 452 453 return bsc->sc_active; 454 } 455 456 #ifdef DEBUG 457 void 458 bzivsc_dump() 459 { 460 int i; 461 462 i = bzivsc_trace_ptr; 463 printf("bzivsc_trace dump: ptr %x\n", bzivsc_trace_ptr); 464 do { 465 if (bzivsc_trace[i].hardbits == 0) { 466 i = (i + 1) & 127; 467 continue; 468 } 469 printf("%02x%02x%02x%02x(", bzivsc_trace[i].hardbits, 470 bzivsc_trace[i].status, bzivsc_trace[i].xx, bzivsc_trace[i].yy); 471 if (bzivsc_trace[i].status & NCRSTAT_INT) 472 printf("NCRINT/"); 473 if (bzivsc_trace[i].status & NCRSTAT_TC) 474 printf("NCRTC/"); 475 switch(bzivsc_trace[i].status & NCRSTAT_PHASE) { 476 case 0: 477 printf("dataout"); break; 478 case 1: 479 printf("datain"); break; 480 case 2: 481 printf("cmdout"); break; 482 case 3: 483 printf("status"); break; 484 case 6: 485 printf("msgout"); break; 486 case 7: 487 printf("msgin"); break; 488 default: 489 printf("phase%d?", bzivsc_trace[i].status & NCRSTAT_PHASE); 490 } 491 printf(") "); 492 i = (i + 1) & 127; 493 } while (i != bzivsc_trace_ptr); 494 printf("\n"); 495 } 496 #endif 497
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