bzsc.c revision 1.16
1 /* $NetBSD: bzsc.c,v 1.16 1997/08/27 11:23:04 bouyer Exp $ */ 2 3 /* 4 * Copyright (c) 1995 Daniel Widenfalk 5 * Copyright (c) 1994 Christian E. Hopps 6 * Copyright (c) 1982, 1990 The Regents of the University of California. 7 * All rights reserved. 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions 11 * are met: 12 * 1. Redistributions of source code must retain the above copyright 13 * notice, this list of conditions and the following disclaimer. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 3. All advertising materials mentioning features or use of this software 18 * must display the following acknowledgement: 19 * This product includes software developed by the University of 20 * California, Berkeley and its contributors. 21 * 4. Neither the name of the University nor the names of its contributors 22 * may be used to endorse or promote products derived from this software 23 * without specific prior written permission. 24 * 25 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 26 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 27 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 28 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 29 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 30 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 31 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 32 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 33 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 34 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 35 * SUCH DAMAGE. 36 * 37 * @(#)dma.c 38 */ 39 40 #include <sys/param.h> 41 #include <sys/systm.h> 42 #include <sys/kernel.h> 43 #include <sys/device.h> 44 #include <dev/scsipi/scsi_all.h> 45 #include <dev/scsipi/scsipi_all.h> 46 #include <dev/scsipi/scsiconf.h> 47 #include <vm/vm.h> 48 #include <vm/vm_kern.h> 49 #include <vm/vm_page.h> 50 #include <machine/pmap.h> 51 #include <amiga/amiga/custom.h> 52 #include <amiga/amiga/cc.h> 53 #include <amiga/amiga/device.h> 54 #include <amiga/amiga/isr.h> 55 #include <amiga/dev/sfasreg.h> 56 #include <amiga/dev/sfasvar.h> 57 #include <amiga/dev/zbusvar.h> 58 #include <amiga/dev/bzscreg.h> 59 #include <amiga/dev/bzscvar.h> 60 61 void bzscattach __P((struct device *, struct device *, void *)); 62 int bzscmatch __P((struct device *, struct cfdata *, void *)); 63 64 struct scsipi_adapter bzsc_scsiswitch = { 65 sfas_scsicmd, 66 sfas_minphys, 67 0, /* no lun support */ 68 0, /* no lun support */ 69 }; 70 71 struct scsipi_device bzsc_scsidev = { 72 NULL, /* use default error handler */ 73 NULL, /* do not have a start functio */ 74 NULL, /* have no async handler */ 75 NULL, /* Use default done routine */ 76 }; 77 78 struct cfattach bzsc_ca = { 79 sizeof(struct bzsc_softc), bzscmatch, bzscattach 80 }; 81 82 struct cfdriver bzsc_cd = { 83 NULL, "bzsc", DV_DULL, NULL, 0 84 }; 85 86 int bzsc_intr __P((void *)); 87 void bzsc_set_dma_adr __P((struct sfas_softc *sc, vm_offset_t ptr, int mode)); 88 void bzsc_set_dma_tc __P((struct sfas_softc *sc, unsigned int len)); 89 int bzsc_setup_dma __P((struct sfas_softc *sc, vm_offset_t ptr, int len, 90 int mode)); 91 int bzsc_build_dma_chain __P((struct sfas_softc *sc, 92 struct sfas_dma_chain *chain, void *p, int l)); 93 int bzsc_need_bump __P((struct sfas_softc *sc, vm_offset_t ptr, int len)); 94 void bzsc_led_dummy __P((struct sfas_softc *sc, int mode)); 95 96 /* 97 * if we are an Advanced Systems & Software FastlaneZ3 98 */ 99 int 100 bzscmatch(pdp, cfp, auxp) 101 struct device *pdp; 102 struct cfdata *cfp; 103 void *auxp; 104 { 105 struct zbus_args *zap; 106 vu_char *ta; 107 108 if (!is_a1200()) 109 return(0); 110 111 zap = auxp; 112 if (zap->manid != 0x2140 || zap->prodid != 11) 113 return(0); 114 115 ta = (vu_char *)(((char *)zap->va)+0x10010); 116 if (badbaddr((caddr_t)ta)) 117 return(0); 118 119 *ta = 0; 120 *ta = 1; 121 DELAY(5); 122 if (*ta != 1) 123 return(0); 124 125 return(1); 126 } 127 128 void 129 bzscattach(pdp, dp, auxp) 130 struct device *pdp; 131 struct device *dp; 132 void *auxp; 133 { 134 struct bzsc_softc *sc; 135 struct zbus_args *zap; 136 bzsc_regmap_p rp; 137 vu_char *fas; 138 139 zap = auxp; 140 fas = (vu_char *)(((char *)zap->va)+0x10000); 141 142 sc = (struct bzsc_softc *)dp; 143 rp = &sc->sc_regmap; 144 145 rp->FAS216.sfas_tc_low = &fas[0x00]; 146 rp->FAS216.sfas_tc_mid = &fas[0x02]; 147 rp->FAS216.sfas_fifo = &fas[0x04]; 148 rp->FAS216.sfas_command = &fas[0x06]; 149 rp->FAS216.sfas_dest_id = &fas[0x08]; 150 rp->FAS216.sfas_timeout = &fas[0x0A]; 151 rp->FAS216.sfas_syncper = &fas[0x0C]; 152 rp->FAS216.sfas_syncoff = &fas[0x0E]; 153 rp->FAS216.sfas_config1 = &fas[0x10]; 154 rp->FAS216.sfas_clkconv = &fas[0x12]; 155 rp->FAS216.sfas_test = &fas[0x14]; 156 rp->FAS216.sfas_config2 = &fas[0x16]; 157 rp->FAS216.sfas_config3 = &fas[0x18]; 158 rp->FAS216.sfas_tc_high = &fas[0x1C]; 159 rp->FAS216.sfas_fifo_bot = &fas[0x1E]; 160 rp->cclkaddr = &fas[0x21]; 161 rp->epowaddr = &fas[0x31]; 162 163 sc->sc_softc.sc_fas = (sfas_regmap_p)rp; 164 sc->sc_softc.sc_spec = 0; 165 166 sc->sc_softc.sc_led = bzsc_led_dummy; 167 168 sc->sc_softc.sc_setup_dma = bzsc_setup_dma; 169 sc->sc_softc.sc_build_dma_chain = bzsc_build_dma_chain; 170 sc->sc_softc.sc_need_bump = bzsc_need_bump; 171 172 sc->sc_softc.sc_clock_freq = 40; /* BlizzardII 1230 runs at 40MHz? */ 173 sc->sc_softc.sc_timeout = 250; /* Set default timeout to 250ms */ 174 sc->sc_softc.sc_config_flags = 0; 175 sc->sc_softc.sc_host_id = 7; 176 177 sc->sc_softc.sc_bump_sz = NBPG; 178 sc->sc_softc.sc_bump_pa = 0x0; 179 180 sfasinitialize((struct sfas_softc *)sc); 181 182 sc->sc_softc.sc_link.scsipi_scsi.channel = SCSI_CHANNEL_ONLY_ONE; 183 sc->sc_softc.sc_link.adapter_softc = sc; 184 sc->sc_softc.sc_link.scsipi_scsi.adapter_target = sc->sc_softc.sc_host_id; 185 sc->sc_softc.sc_link.adapter = &bzsc_scsiswitch; 186 sc->sc_softc.sc_link.device = &bzsc_scsidev; 187 sc->sc_softc.sc_link.openings = 1; 188 sc->sc_softc.sc_link.scsipi_scsi.max_target = 7; 189 sc->sc_softc.sc_link.type = BUS_SCSI; 190 191 printf("\n"); 192 193 sc->sc_softc.sc_isr.isr_intr = bzsc_intr; 194 sc->sc_softc.sc_isr.isr_arg = &sc->sc_softc; 195 sc->sc_softc.sc_isr.isr_ipl = 2; 196 add_isr(&sc->sc_softc.sc_isr); 197 198 /* attach all scsi units on us */ 199 config_found(dp, &sc->sc_softc.sc_link, scsiprint); 200 } 201 202 int 203 bzsc_intr(arg) 204 void *arg; 205 { 206 struct sfas_softc *dev = arg; 207 bzsc_regmap_p rp; 208 int quickints; 209 210 rp = (bzsc_regmap_p)dev->sc_fas; 211 212 if (!(*rp->FAS216.sfas_status & SFAS_STAT_INTERRUPT_PENDING)) 213 return(0); 214 215 quickints = 16; 216 do { 217 dev->sc_status = *rp->FAS216.sfas_status; 218 dev->sc_interrupt = *rp->FAS216.sfas_interrupt; 219 220 if (dev->sc_interrupt & SFAS_INT_RESELECTED) { 221 dev->sc_resel[0] = *rp->FAS216.sfas_fifo; 222 dev->sc_resel[1] = *rp->FAS216.sfas_fifo; 223 } 224 sfasintr(dev); 225 } while((*rp->FAS216.sfas_status & SFAS_STAT_INTERRUPT_PENDING) && 226 --quickints); 227 228 return(1); 229 } 230 231 /* --------- */ 232 void 233 bzsc_set_dma_adr(sc, ptr, mode) 234 struct sfas_softc *sc; 235 vm_offset_t ptr; 236 int mode; 237 { 238 bzsc_regmap_p rp; 239 unsigned long p; 240 241 rp = (bzsc_regmap_p)sc->sc_fas; 242 243 p = ((unsigned long)ptr)>>1; 244 245 if (mode == SFAS_DMA_WRITE) 246 p |= BZSC_DMA_WRITE; 247 else 248 p |= BZSC_DMA_READ; 249 250 *rp->epowaddr = (u_char)(p>>24) & 0xFF; 251 *rp->cclkaddr = (u_char)(p>>16) & 0xFF; 252 *rp->cclkaddr = (u_char)(p>> 8) & 0xFF; 253 *rp->cclkaddr = (u_char)(p ) & 0xFF; 254 } 255 256 /* Set DMA transfer counter */ 257 void 258 bzsc_set_dma_tc(sc, len) 259 struct sfas_softc *sc; 260 unsigned int len; 261 { 262 *sc->sc_fas->sfas_tc_low = len; len >>= 8; 263 *sc->sc_fas->sfas_tc_mid = len; len >>= 8; 264 *sc->sc_fas->sfas_tc_high = len; 265 } 266 267 /* Initialize DMA for transfer */ 268 int 269 bzsc_setup_dma(sc, ptr, len, mode) 270 struct sfas_softc *sc; 271 vm_offset_t ptr; 272 int len; 273 int mode; 274 { 275 int retval; 276 277 retval = 0; 278 279 switch(mode) { 280 case SFAS_DMA_READ: 281 case SFAS_DMA_WRITE: 282 bzsc_set_dma_adr(sc, ptr, mode); 283 bzsc_set_dma_tc(sc, len); 284 break; 285 case SFAS_DMA_CLEAR: 286 default: 287 retval = (*sc->sc_fas->sfas_tc_high << 16) | 288 (*sc->sc_fas->sfas_tc_mid << 8) | 289 *sc->sc_fas->sfas_tc_low; 290 291 bzsc_set_dma_tc(sc, 0); 292 break; 293 } 294 295 return(retval); 296 } 297 298 /* Check if address and len is ok for DMA transfer */ 299 int 300 bzsc_need_bump(sc, ptr, len) 301 struct sfas_softc *sc; 302 vm_offset_t ptr; 303 int len; 304 { 305 int p; 306 307 p = (int)ptr & 0x03; 308 309 if (p) { 310 p = 4-p; 311 312 if (len < 256) 313 p = len; 314 } 315 316 return(p); 317 } 318 319 /* Interrupt driven routines */ 320 int 321 bzsc_build_dma_chain(sc, chain, p, l) 322 struct sfas_softc *sc; 323 struct sfas_dma_chain *chain; 324 void *p; 325 int l; 326 { 327 int n; 328 329 if (!l) 330 return(0); 331 332 #define set_link(n, p, l, f)\ 333 do { chain[n].ptr = (p); chain[n].len = (l); chain[n++].flg = (f); } while(0) 334 335 n = 0; 336 337 if (l < 512) 338 set_link(n, (vm_offset_t)p, l, SFAS_CHAIN_BUMP); 339 else if ( 340 #if defined(M68040) || defined(M68060) 341 ((mmutype == MMU_68040) && ((vm_offset_t)p >= 0xFFFC0000)) && 342 #endif 343 ((vm_offset_t)p >= 0xFF000000)) { 344 int len; 345 346 while(l) { 347 len = ((l > sc->sc_bump_sz) ? sc->sc_bump_sz : l); 348 349 set_link(n, (vm_offset_t)p, len, SFAS_CHAIN_BUMP); 350 351 p += len; 352 l -= len; 353 } 354 } else { 355 char *ptr; 356 vm_offset_t pa, lastpa; 357 int len, prelen, max_t; 358 359 ptr = p; 360 len = l; 361 362 pa = kvtop(ptr); 363 prelen = ((int)ptr & 0x03); 364 365 if (prelen) { 366 prelen = 4-prelen; 367 set_link(n, (vm_offset_t)ptr, prelen, SFAS_CHAIN_BUMP); 368 ptr += prelen; 369 len -= prelen; 370 } 371 372 lastpa = 0; 373 while(len > 3) { 374 pa = kvtop(ptr); 375 max_t = NBPG - (pa & PGOFSET); 376 if (max_t > len) 377 max_t = len; 378 379 max_t &= ~3; 380 381 if (lastpa == pa) 382 sc->sc_chain[n-1].len += max_t; 383 else 384 set_link(n, pa, max_t, SFAS_CHAIN_DMA); 385 386 lastpa = pa+max_t; 387 388 ptr += max_t; 389 len -= max_t; 390 } 391 392 if (len) 393 set_link(n, (vm_offset_t)ptr, len, SFAS_CHAIN_BUMP); 394 } 395 396 return(n); 397 } 398 399 /* Turn on led */ 400 void bzsc_led_dummy(sc, mode) 401 struct sfas_softc *sc; 402 int mode; 403 { 404 } 405
Indexes created Tue Sep 30 20:09:53 GMT 2025