bzsc.c revision 1.17
1 /* $NetBSD: bzsc.c,v 1.17 1997/10/04 04:01:17 mhitch Exp $ */ 2 3 /* 4 * Copyright (c) 1997 Michael L. Hitch 5 * Copyright (c) 1995 Daniel Widenfalk 6 * Copyright (c) 1994 Christian E. Hopps 7 * Copyright (c) 1982, 1990 The Regents of the University of California. 8 * All rights reserved. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 3. All advertising materials mentioning features or use of this software 19 * must display the following acknowledgement: 20 * This product includes software developed by Daniel Widenfalk 21 * and Michael L. Hitch. 22 * 4. Neither the name of the University nor the names of its contributors 23 * may be used to endorse or promote products derived from this software 24 * without specific prior written permission. 25 * 26 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 27 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 28 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 29 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 30 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 31 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 32 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 33 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 34 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 35 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 36 * SUCH DAMAGE. 37 */ 38 39 /* 40 * Initial amiga Blizzard 1230-II driver by Daniel Widenfalk. Conversion to 41 * 53c9x MI driver and Blizzard IV by Michael L. Hitch (mhitch (at) montana.edu). 42 */ 43 44 #include <sys/types.h> 45 #include <sys/param.h> 46 #include <sys/systm.h> 47 #include <sys/kernel.h> 48 #include <sys/errno.h> 49 #include <sys/ioctl.h> 50 #include <sys/device.h> 51 #include <sys/buf.h> 52 #include <sys/proc.h> 53 #include <sys/user.h> 54 #include <sys/queue.h> 55 56 #include <dev/scsipi/scsi_all.h> 57 #include <dev/scsipi/scsipi_all.h> 58 #include <dev/scsipi/scsiconf.h> 59 #include <dev/scsipi/scsi_message.h> 60 61 #include <machine/cpu.h> 62 #include <machine/param.h> 63 64 #include <dev/ic/ncr53c9xreg.h> 65 #include <dev/ic/ncr53c9xvar.h> 66 67 #include <amiga/amiga/isr.h> 68 #include <amiga/dev/bzscvar.h> 69 #include <amiga/dev/zbusvar.h> 70 71 void bzscattach __P((struct device *, struct device *, void *)); 72 int bzscmatch __P((struct device *, struct cfdata *, void *)); 73 74 /* Linkup to the rest of the kernel */ 75 struct cfattach bzsc_ca = { 76 sizeof(struct bzsc_softc), bzscmatch, bzscattach 77 }; 78 79 struct cfdriver bzsc_cd = { 80 NULL, "bzsc", DV_DULL 81 }; 82 83 struct scsipi_adapter bzsc_switch = { 84 ncr53c9x_scsi_cmd, 85 minphys, /* no max at this level; handled by DMA code */ 86 NULL, 87 NULL, 88 }; 89 90 struct scsipi_device bzsc_dev = { 91 NULL, /* Use default error handler */ 92 NULL, /* have a queue, served by this */ 93 NULL, /* have no async handler */ 94 NULL, /* Use default 'done' routine */ 95 }; 96 97 /* 98 * Functions and the switch for the MI code. 99 */ 100 u_char bzsc_read_reg __P((struct ncr53c9x_softc *, int)); 101 void bzsc_write_reg __P((struct ncr53c9x_softc *, int, u_char)); 102 int bzsc_dma_isintr __P((struct ncr53c9x_softc *)); 103 void bzsc_dma_reset __P((struct ncr53c9x_softc *)); 104 int bzsc_dma_intr __P((struct ncr53c9x_softc *)); 105 int bzsc_dma_setup __P((struct ncr53c9x_softc *, caddr_t *, 106 size_t *, int, size_t *)); 107 void bzsc_dma_go __P((struct ncr53c9x_softc *)); 108 void bzsc_dma_stop __P((struct ncr53c9x_softc *)); 109 int bzsc_dma_isactive __P((struct ncr53c9x_softc *)); 110 111 struct ncr53c9x_glue bzsc_glue = { 112 bzsc_read_reg, 113 bzsc_write_reg, 114 bzsc_dma_isintr, 115 bzsc_dma_reset, 116 bzsc_dma_intr, 117 bzsc_dma_setup, 118 bzsc_dma_go, 119 bzsc_dma_stop, 120 bzsc_dma_isactive, 121 0, 122 }; 123 124 /* Maximum DMA transfer length to reduce impact on high-speed serial input */ 125 u_long bzsc_max_dma = 1024; 126 extern int ser_open_speed; 127 128 u_long bzsc_cnt_pio = 0; /* number of PIO transfers */ 129 u_long bzsc_cnt_dma = 0; /* number of DMA transfers */ 130 u_long bzsc_cnt_dma2 = 0; /* number of DMA transfers broken up */ 131 u_long bzsc_cnt_dma3 = 0; /* number of pages combined */ 132 133 #ifdef DEBUG 134 struct { 135 u_char hardbits; 136 u_char status; 137 u_char xx; 138 u_char yy; 139 } bzsc_trace[128]; 140 int bzsc_trace_ptr = 0; 141 int bzsc_trace_enable = 1; 142 void bzsc_dump __P((void)); 143 #endif 144 145 /* 146 * if we are a Phase5 Blizzard 12x0 II or IV 147 */ 148 int 149 bzscmatch(parent, cf, aux) 150 struct device *parent; 151 struct cfdata *cf; 152 void *aux; 153 { 154 struct zbus_args *zap; 155 volatile u_char *regs; 156 157 zap = aux; 158 if (zap->manid != 0x2140) 159 return(0); /* It's not Phase 5 */ 160 if (zap->prodid != 11 && zap->prodid != 17) 161 return(0); /* Not Blizzard 12x0 */ 162 if (!is_a1200()) 163 return(0); /* And not A1200 */ 164 regs = &((volatile u_char *)zap->va)[0x8000]; 165 if (zap->prodid == 11) { 166 /* 167 * 12x0 II is product ID 11, but some IV may have the 168 * same product ID. Check for IV first, then II. 169 */ 170 if (!badaddr((caddr_t)regs)) { 171 regs[NCR_CFG1 * 4] = 0; 172 regs[NCR_CFG1 * 4] = NCRCFG1_PARENB | 7; 173 delay(5); 174 if (regs[NCR_CFG1 * 4] == (NCRCFG1_PARENB | 7)) 175 return(1); /* 12x0 IV */ 176 } 177 regs = &((volatile u_char *)zap->va)[0x10000]; 178 } 179 if (badaddr((caddr_t)regs)) 180 return(0); 181 regs[NCR_CFG1 * 4] = 0; 182 regs[NCR_CFG1 * 4] = NCRCFG1_PARENB | 7; 183 delay(5); 184 if (regs[NCR_CFG1 * 4] != (NCRCFG1_PARENB | 7)) 185 return(0); 186 return(1); 187 } 188 189 /* 190 * Attach this instance, and then all the sub-devices 191 */ 192 void 193 bzscattach(parent, self, aux) 194 struct device *parent, *self; 195 void *aux; 196 { 197 struct bzsc_softc *bsc = (void *)self; 198 struct ncr53c9x_softc *sc = &bsc->sc_ncr53c9x; 199 struct zbus_args *zap; 200 extern u_long scsi_nosync; 201 extern int shift_nosync; 202 extern int ncr53c9x_debug; 203 volatile u_char *regs; 204 205 /* 206 * Set up the glue for MI code early; we use some of it here. 207 */ 208 sc->sc_glue = &bzsc_glue; 209 210 /* 211 * Save the regs 212 */ 213 zap = aux; 214 regs = &((volatile u_char *)zap->va)[0x8000]; 215 bsc->sc_dmabase = ®s[0x8000]; 216 if (zap->prodid == 11) { 217 if (!badaddr((caddr_t)regs)) { 218 regs[NCR_CFG1 * 4] = 0; 219 regs[NCR_CFG1 * 4] = NCRCFG1_PARENB | 7; 220 delay(5); 221 if (regs[NCR_CFG1 * 4] != (NCRCFG1_PARENB | 7)) { 222 regs = &((volatile u_char *)zap->va)[0x10000]; 223 bsc->sc_dmabase = ®s[0x21]; 224 } 225 } else { 226 regs = &((volatile u_char *)zap->va)[0x10000]; 227 bsc->sc_dmabase = ®s[0x21]; 228 } 229 } 230 bsc->sc_reg = regs; 231 232 sc->sc_freq = 40; /* Clocked at 40Mhz */ 233 234 printf(": address %p", bsc->sc_reg); 235 236 sc->sc_id = 7; 237 238 /* 239 * It is necessary to try to load the 2nd config register here, 240 * to find out what rev the FAS chip is, else the ncr53c9x_reset 241 * will not set up the defaults correctly. 242 */ 243 sc->sc_cfg1 = sc->sc_id | NCRCFG1_PARENB; 244 sc->sc_cfg2 = NCRCFG2_SCSI2 | NCRCFG2_FE; 245 sc->sc_cfg3 = 0x08 /*FCLK*/ | NCRESPCFG3_FSCSI | NCRESPCFG3_CDB; 246 sc->sc_rev = NCR_VARIANT_FAS216; 247 248 /* 249 * This is the value used to start sync negotiations 250 * Note that the NCR register "SYNCTP" is programmed 251 * in "clocks per byte", and has a minimum value of 4. 252 * The SCSI period used in negotiation is one-fourth 253 * of the time (in nanoseconds) needed to transfer one byte. 254 * Since the chip's clock is given in MHz, we have the following 255 * formula: 4 * period = (1000 / freq) * 4 256 */ 257 sc->sc_minsync = 1000 / sc->sc_freq; 258 259 /* 260 * get flags from -I argument and set cf_flags. 261 * NOTE: low 8 bits are to disable disconnect, and the next 262 * 8 bits are to disable sync. 263 */ 264 sc->sc_dev.dv_cfdata->cf_flags |= (scsi_nosync >> shift_nosync) 265 & 0xffff; 266 shift_nosync += 16; 267 268 /* Use next 16 bits of -I argument to set ncr53c9x_debug flags */ 269 ncr53c9x_debug |= (scsi_nosync >> shift_nosync) & 0xffff; 270 shift_nosync += 16; 271 272 #if 1 273 if (((scsi_nosync >> shift_nosync) & 0xff00) == 0xff00) 274 sc->sc_minsync = 0; 275 #endif 276 277 /* Really no limit, but since we want to fit into the TCR... */ 278 sc->sc_maxxfer = 64 * 1024; 279 280 /* 281 * Configure interrupts. 282 */ 283 bsc->sc_isr.isr_intr = (int (*)(void *))ncr53c9x_intr; 284 bsc->sc_isr.isr_arg = sc; 285 bsc->sc_isr.isr_ipl = 2; 286 add_isr(&bsc->sc_isr); 287 288 /* 289 * Now try to attach all the sub-devices 290 */ 291 ncr53c9x_attach(sc, &bzsc_switch, &bzsc_dev); 292 } 293 294 /* 295 * Glue functions. 296 */ 297 298 u_char 299 bzsc_read_reg(sc, reg) 300 struct ncr53c9x_softc *sc; 301 int reg; 302 { 303 struct bzsc_softc *bsc = (struct bzsc_softc *)sc; 304 305 return bsc->sc_reg[reg * 2]; 306 } 307 308 void 309 bzsc_write_reg(sc, reg, val) 310 struct ncr53c9x_softc *sc; 311 int reg; 312 u_char val; 313 { 314 struct bzsc_softc *bsc = (struct bzsc_softc *)sc; 315 u_char v = val; 316 317 bsc->sc_reg[reg * 2] = v; 318 #ifdef DEBUG 319 if (bzsc_trace_enable/* && sc->sc_nexus && sc->sc_nexus->xs->flags & SCSI_POLL*/ && 320 reg == NCR_CMD/* && bsc->sc_active*/) { 321 bzsc_trace[(bzsc_trace_ptr - 1) & 127].yy = v; 322 /* printf(" cmd %x", v);*/ 323 } 324 #endif 325 } 326 327 int 328 bzsc_dma_isintr(sc) 329 struct ncr53c9x_softc *sc; 330 { 331 struct bzsc_softc *bsc = (struct bzsc_softc *)sc; 332 333 if ((bsc->sc_reg[NCR_STAT * 2] & NCRSTAT_INT) == 0) 334 return 0; 335 336 #ifdef DEBUG 337 if (/*sc->sc_nexus && sc->sc_nexus->xs->flags & SCSI_POLL &&*/ bzsc_trace_enable) { 338 bzsc_trace[bzsc_trace_ptr].status = bsc->sc_reg[NCR_STAT * 2]; 339 bzsc_trace[bzsc_trace_ptr].xx = bsc->sc_reg[NCR_CMD * 2]; 340 bzsc_trace[bzsc_trace_ptr].yy = bsc->sc_active; 341 bzsc_trace_ptr = (bzsc_trace_ptr + 1) & 127; 342 } 343 #endif 344 return 1; 345 } 346 347 void 348 bzsc_dma_reset(sc) 349 struct ncr53c9x_softc *sc; 350 { 351 struct bzsc_softc *bsc = (struct bzsc_softc *)sc; 352 353 bsc->sc_active = 0; 354 } 355 356 int 357 bzsc_dma_intr(sc) 358 struct ncr53c9x_softc *sc; 359 { 360 register struct bzsc_softc *bsc = (struct bzsc_softc *)sc; 361 register int cnt; 362 363 NCR_DMA(("bzsc_dma_intr: cnt %d int %x stat %x fifo %d ", 364 bsc->sc_dmasize, sc->sc_espintr, sc->sc_espstat, 365 bsc->sc_reg[NCR_FFLAG * 2] & NCRFIFO_FF)); 366 if (bsc->sc_active == 0) { 367 printf("bzsc_intr--inactive DMA\n"); 368 return -1; 369 } 370 371 /* update sc_dmaaddr and sc_pdmalen */ 372 cnt = bsc->sc_reg[NCR_TCL * 2]; 373 cnt += bsc->sc_reg[NCR_TCM * 2] << 8; 374 cnt += bsc->sc_reg[NCR_TCH * 2] << 16; 375 if (!bsc->sc_datain) { 376 cnt += bsc->sc_reg[NCR_FFLAG * 2] & NCRFIFO_FF; 377 bsc->sc_reg[NCR_CMD * 2] = NCRCMD_FLUSH; 378 } 379 cnt = bsc->sc_dmasize - cnt; /* number of bytes transferred */ 380 NCR_DMA(("DMA xferred %d\n", cnt)); 381 if (bsc->sc_xfr_align) { 382 bcopy(bsc->sc_alignbuf, *bsc->sc_dmaaddr, cnt); 383 bsc->sc_xfr_align = 0; 384 } 385 *bsc->sc_dmaaddr += cnt; 386 *bsc->sc_pdmalen -= cnt; 387 bsc->sc_active = 0; 388 return 0; 389 } 390 391 int 392 bzsc_dma_setup(sc, addr, len, datain, dmasize) 393 struct ncr53c9x_softc *sc; 394 caddr_t *addr; 395 size_t *len; 396 int datain; 397 size_t *dmasize; 398 { 399 struct bzsc_softc *bsc = (struct bzsc_softc *)sc; 400 vm_offset_t pa; 401 u_char *ptr; 402 size_t xfer; 403 404 bsc->sc_dmaaddr = addr; 405 bsc->sc_pdmalen = len; 406 bsc->sc_datain = datain; 407 bsc->sc_dmasize = *dmasize; 408 /* 409 * DMA can be nasty for high-speed serial input, so limit the 410 * size of this DMA operation if the serial port is running at 411 * a high speed (higher than 19200 for now - should be adjusted 412 * based on cpu type and speed?). 413 * XXX - add serial speed check XXX 414 */ 415 if (ser_open_speed > 19200 && bzsc_max_dma != 0 && 416 bsc->sc_dmasize > bzsc_max_dma) 417 bsc->sc_dmasize = bzsc_max_dma; 418 ptr = *addr; /* Kernel virtual address */ 419 pa = kvtop(ptr); /* Physical address of DMA */ 420 xfer = min(bsc->sc_dmasize, NBPG - (pa & (NBPG - 1))); 421 bsc->sc_xfr_align = 0; 422 /* 423 * If output and unaligned, stuff odd byte into FIFO 424 */ 425 if (datain == 0 && (int)ptr & 1) { 426 NCR_DMA(("bzsc_dma_setup: align byte written to fifo\n")); 427 pa++; 428 xfer--; /* XXXX CHECK THIS !!!! XXXX */ 429 bsc->sc_reg[NCR_FIFO * 2] = *ptr++; 430 } 431 /* 432 * If unaligned address, read unaligned bytes into alignment buffer 433 */ 434 else if ((int)ptr & 1) { 435 pa = kvtop((caddr_t)&bsc->sc_alignbuf); 436 xfer = bsc->sc_dmasize = min(xfer, sizeof (bsc->sc_alignbuf)); 437 NCR_DMA(("bzsc_dma_setup: align read by %d bytes\n", xfer)); 438 bsc->sc_xfr_align = 1; 439 } 440 ++bzsc_cnt_dma; /* number of DMA operations */ 441 442 while (xfer < bsc->sc_dmasize) { 443 if ((pa + xfer) != kvtop(*addr + xfer)) 444 break; 445 if ((bsc->sc_dmasize - xfer) < NBPG) 446 xfer = bsc->sc_dmasize; 447 else 448 xfer += NBPG; 449 ++bzsc_cnt_dma3; 450 } 451 if (xfer != *len) 452 ++bzsc_cnt_dma2; 453 454 bsc->sc_dmasize = xfer; 455 *dmasize = bsc->sc_dmasize; 456 bsc->sc_pa = pa; 457 #if defined(M68040) || defined(M68060) 458 if (mmutype == MMU_68040) { 459 if (bsc->sc_xfr_align) { 460 dma_cachectl(bsc->sc_alignbuf, 461 sizeof(bsc->sc_alignbuf)); 462 } 463 else 464 dma_cachectl(*bsc->sc_dmaaddr, bsc->sc_dmasize); 465 } 466 #endif 467 468 pa = pa >> 1; 469 if (!bsc->sc_datain) 470 pa |= 0x80000000; 471 if ((u_long)bsc->sc_dmabase & 1) 472 bsc->sc_dmabase[0x10] = (u_int8_t)(pa >> 24); 473 else { 474 bsc->sc_dmabase[0x8000] = (u_int8_t)(pa >> 24); 475 bsc->sc_dmabase[0] = (u_int8_t)(pa >> 24); 476 } 477 bsc->sc_dmabase[0] = (u_int8_t)(pa >> 16); 478 bsc->sc_dmabase[0] = (u_int8_t)(pa >> 8); 479 bsc->sc_dmabase[0] = (u_int8_t)(pa); 480 bsc->sc_active = 1; 481 return 0; 482 } 483 484 void 485 bzsc_dma_go(sc) 486 struct ncr53c9x_softc *sc; 487 { 488 } 489 490 void 491 bzsc_dma_stop(sc) 492 struct ncr53c9x_softc *sc; 493 { 494 } 495 496 int 497 bzsc_dma_isactive(sc) 498 struct ncr53c9x_softc *sc; 499 { 500 struct bzsc_softc *bsc = (struct bzsc_softc *)sc; 501 502 return bsc->sc_active; 503 } 504 505 #ifdef DEBUG 506 void 507 bzsc_dump() 508 { 509 int i; 510 511 i = bzsc_trace_ptr; 512 printf("bzsc_trace dump: ptr %x\n", bzsc_trace_ptr); 513 do { 514 if (bzsc_trace[i].hardbits == 0) { 515 i = (i + 1) & 127; 516 continue; 517 } 518 printf("%02x%02x%02x%02x(", bzsc_trace[i].hardbits, 519 bzsc_trace[i].status, bzsc_trace[i].xx, bzsc_trace[i].yy); 520 if (bzsc_trace[i].status & NCRSTAT_INT) 521 printf("NCRINT/"); 522 if (bzsc_trace[i].status & NCRSTAT_TC) 523 printf("NCRTC/"); 524 switch(bzsc_trace[i].status & NCRSTAT_PHASE) { 525 case 0: 526 printf("dataout"); break; 527 case 1: 528 printf("datain"); break; 529 case 2: 530 printf("cmdout"); break; 531 case 3: 532 printf("status"); break; 533 case 6: 534 printf("msgout"); break; 535 case 7: 536 printf("msgin"); break; 537 default: 538 printf("phase%d?", bzsc_trace[i].status & NCRSTAT_PHASE); 539 } 540 printf(") "); 541 i = (i + 1) & 127; 542 } while (i != bzsc_trace_ptr); 543 printf("\n"); 544 } 545 #endif 546
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