bzsc.c revision 1.18
1 /* $NetBSD: bzsc.c,v 1.18 1997/10/10 04:53:39 mhitch Exp $ */ 2 3 /* 4 * Copyright (c) 1995 Daniel Widenfalk 5 * Copyright (c) 1994 Christian E. Hopps 6 * Copyright (c) 1982, 1990 The Regents of the University of California. 7 * All rights reserved. 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions 11 * are met: 12 * 1. Redistributions of source code must retain the above copyright 13 * notice, this list of conditions and the following disclaimer. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 3. All advertising materials mentioning features or use of this software 18 * must display the following acknowledgement: 19 * This product includes software developed by the University of 20 * California, Berkeley and its contributors. 21 * 4. Neither the name of the University nor the names of its contributors 22 * may be used to endorse or promote products derived from this software 23 * without specific prior written permission. 24 * 25 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 26 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 27 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 28 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 29 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 30 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 31 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 32 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 33 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 34 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 35 * SUCH DAMAGE. 36 * 37 * @(#)dma.c 38 */ 39 40 #include <sys/param.h> 41 #include <sys/systm.h> 42 #include <sys/kernel.h> 43 #include <sys/device.h> 44 #include <scsi/scsi_all.h> 45 #include <scsi/scsiconf.h> 46 #include <vm/vm.h> 47 #include <vm/vm_kern.h> 48 #include <vm/vm_page.h> 49 #include <machine/pmap.h> 50 #include <amiga/amiga/custom.h> 51 #include <amiga/amiga/cc.h> 52 #include <amiga/amiga/device.h> 53 #include <amiga/amiga/isr.h> 54 #include <amiga/dev/sfasreg.h> 55 #include <amiga/dev/sfasvar.h> 56 #include <amiga/dev/zbusvar.h> 57 #include <amiga/dev/bzscreg.h> 58 #include <amiga/dev/bzscvar.h> 59 60 void bzscattach __P((struct device *, struct device *, void *)); 61 int bzscmatch __P((struct device *, struct cfdata *, void *)); 62 63 struct scsi_adapter bzsc_scsiswitch = { 64 sfas_scsicmd, 65 sfas_minphys, 66 0, /* no lun support */ 67 0, /* no lun support */ 68 }; 69 70 struct scsi_device bzsc_scsidev = { 71 NULL, /* use default error handler */ 72 NULL, /* do not have a start functio */ 73 NULL, /* have no async handler */ 74 NULL, /* Use default done routine */ 75 }; 76 77 struct cfattach bzsc_ca = { 78 sizeof(struct bzsc_softc), bzscmatch, bzscattach 79 }; 80 81 struct cfdriver bzsc_cd = { 82 NULL, "bzsc", DV_DULL, NULL, 0 83 }; 84 85 int bzsc_intr __P((void *)); 86 void bzsc_set_dma_adr __P((struct sfas_softc *sc, vm_offset_t ptr, int mode)); 87 void bzsc_set_dma_tc __P((struct sfas_softc *sc, unsigned int len)); 88 int bzsc_setup_dma __P((struct sfas_softc *sc, vm_offset_t ptr, int len, 89 int mode)); 90 int bzsc_build_dma_chain __P((struct sfas_softc *sc, 91 struct sfas_dma_chain *chain, void *p, int l)); 92 int bzsc_need_bump __P((struct sfas_softc *sc, vm_offset_t ptr, int len)); 93 void bzsc_led_dummy __P((struct sfas_softc *sc, int mode)); 94 95 /* 96 * if we are an Advanced Systems & Software FastlaneZ3 97 */ 98 int 99 bzscmatch(pdp, cfp, auxp) 100 struct device *pdp; 101 struct cfdata *cfp; 102 void *auxp; 103 { 104 struct zbus_args *zap; 105 vu_char *ta; 106 107 if (!is_a1200()) 108 return(0); 109 110 zap = auxp; 111 if (zap->manid != 0x2140 || zap->prodid != 11) 112 return(0); 113 114 ta = (vu_char *)(((char *)zap->va)+0x10010); 115 if (badbaddr((caddr_t)ta)) 116 return(0); 117 118 *ta = 0; 119 *ta = 1; 120 DELAY(5); 121 if (*ta != 1) 122 return(0); 123 124 return(1); 125 } 126 127 void 128 bzscattach(pdp, dp, auxp) 129 struct device *pdp; 130 struct device *dp; 131 void *auxp; 132 { 133 struct bzsc_softc *sc; 134 struct zbus_args *zap; 135 bzsc_regmap_p rp; 136 vu_char *fas; 137 138 zap = auxp; 139 fas = (vu_char *)(((char *)zap->va)+0x10000); 140 141 sc = (struct bzsc_softc *)dp; 142 rp = &sc->sc_regmap; 143 144 rp->FAS216.sfas_tc_low = &fas[0x00]; 145 rp->FAS216.sfas_tc_mid = &fas[0x02]; 146 rp->FAS216.sfas_fifo = &fas[0x04]; 147 rp->FAS216.sfas_command = &fas[0x06]; 148 rp->FAS216.sfas_dest_id = &fas[0x08]; 149 rp->FAS216.sfas_timeout = &fas[0x0A]; 150 rp->FAS216.sfas_syncper = &fas[0x0C]; 151 rp->FAS216.sfas_syncoff = &fas[0x0E]; 152 rp->FAS216.sfas_config1 = &fas[0x10]; 153 rp->FAS216.sfas_clkconv = &fas[0x12]; 154 rp->FAS216.sfas_test = &fas[0x14]; 155 rp->FAS216.sfas_config2 = &fas[0x16]; 156 rp->FAS216.sfas_config3 = &fas[0x18]; 157 rp->FAS216.sfas_tc_high = &fas[0x1C]; 158 rp->FAS216.sfas_fifo_bot = &fas[0x1E]; 159 rp->cclkaddr = &fas[0x21]; 160 rp->epowaddr = &fas[0x31]; 161 162 sc->sc_softc.sc_fas = (sfas_regmap_p)rp; 163 sc->sc_softc.sc_spec = 0; 164 165 sc->sc_softc.sc_led = bzsc_led_dummy; 166 167 sc->sc_softc.sc_setup_dma = bzsc_setup_dma; 168 sc->sc_softc.sc_build_dma_chain = bzsc_build_dma_chain; 169 sc->sc_softc.sc_need_bump = bzsc_need_bump; 170 171 sc->sc_softc.sc_clock_freq = 40; /* BlizzardII 1230 runs at 40MHz? */ 172 sc->sc_softc.sc_timeout = 250; /* Set default timeout to 250ms */ 173 sc->sc_softc.sc_config_flags = 0; 174 sc->sc_softc.sc_host_id = 7; 175 176 sc->sc_softc.sc_bump_sz = NBPG; 177 sc->sc_softc.sc_bump_pa = 0x0; 178 179 sfasinitialize((struct sfas_softc *)sc); 180 181 sc->sc_softc.sc_link.channel = SCSI_CHANNEL_ONLY_ONE; 182 sc->sc_softc.sc_link.adapter_softc = sc; 183 sc->sc_softc.sc_link.adapter_target = sc->sc_softc.sc_host_id; 184 sc->sc_softc.sc_link.adapter = &bzsc_scsiswitch; 185 sc->sc_softc.sc_link.device = &bzsc_scsidev; 186 sc->sc_softc.sc_link.openings = 1; 187 sc->sc_softc.sc_link.max_target = 7; 188 189 printf("\n"); 190 191 sc->sc_softc.sc_isr.isr_intr = bzsc_intr; 192 sc->sc_softc.sc_isr.isr_arg = &sc->sc_softc; 193 sc->sc_softc.sc_isr.isr_ipl = 2; 194 add_isr(&sc->sc_softc.sc_isr); 195 196 /* attach all scsi units on us */ 197 config_found(dp, &sc->sc_softc.sc_link, scsiprint); 198 } 199 200 int 201 bzsc_intr(arg) 202 void *arg; 203 { 204 struct sfas_softc *dev = arg; 205 bzsc_regmap_p rp; 206 int quickints; 207 208 rp = (bzsc_regmap_p)dev->sc_fas; 209 210 if (!(*rp->FAS216.sfas_status & SFAS_STAT_INTERRUPT_PENDING)) 211 return(0); 212 213 quickints = 16; 214 do { 215 dev->sc_status = *rp->FAS216.sfas_status; 216 dev->sc_interrupt = *rp->FAS216.sfas_interrupt; 217 218 if (dev->sc_interrupt & SFAS_INT_RESELECTED) { 219 dev->sc_resel[0] = *rp->FAS216.sfas_fifo; 220 dev->sc_resel[1] = *rp->FAS216.sfas_fifo; 221 } 222 sfasintr(dev); 223 } while((*rp->FAS216.sfas_status & SFAS_STAT_INTERRUPT_PENDING) && 224 --quickints); 225 226 return(1); 227 } 228 229 /* --------- */ 230 void 231 bzsc_set_dma_adr(sc, ptr, mode) 232 struct sfas_softc *sc; 233 vm_offset_t ptr; 234 int mode; 235 { 236 bzsc_regmap_p rp; 237 unsigned long p; 238 239 rp = (bzsc_regmap_p)sc->sc_fas; 240 241 p = ((unsigned long)ptr)>>1; 242 243 if (mode == SFAS_DMA_WRITE) 244 p |= BZSC_DMA_WRITE; 245 else 246 p |= BZSC_DMA_READ; 247 248 *rp->epowaddr = (u_char)(p>>24) & 0xFF; 249 *rp->cclkaddr = (u_char)(p>>16) & 0xFF; 250 *rp->cclkaddr = (u_char)(p>> 8) & 0xFF; 251 *rp->cclkaddr = (u_char)(p ) & 0xFF; 252 } 253 254 /* Set DMA transfer counter */ 255 void 256 bzsc_set_dma_tc(sc, len) 257 struct sfas_softc *sc; 258 unsigned int len; 259 { 260 *sc->sc_fas->sfas_tc_low = len; len >>= 8; 261 *sc->sc_fas->sfas_tc_mid = len; len >>= 8; 262 *sc->sc_fas->sfas_tc_high = len; 263 } 264 265 /* Initialize DMA for transfer */ 266 int 267 bzsc_setup_dma(sc, ptr, len, mode) 268 struct sfas_softc *sc; 269 vm_offset_t ptr; 270 int len; 271 int mode; 272 { 273 int retval; 274 275 retval = 0; 276 277 switch(mode) { 278 case SFAS_DMA_READ: 279 case SFAS_DMA_WRITE: 280 bzsc_set_dma_adr(sc, ptr, mode); 281 bzsc_set_dma_tc(sc, len); 282 break; 283 case SFAS_DMA_CLEAR: 284 default: 285 retval = (*sc->sc_fas->sfas_tc_high << 16) | 286 (*sc->sc_fas->sfas_tc_mid << 8) | 287 *sc->sc_fas->sfas_tc_low; 288 289 bzsc_set_dma_tc(sc, 0); 290 break; 291 } 292 293 return(retval); 294 } 295 296 /* Check if address and len is ok for DMA transfer */ 297 int 298 bzsc_need_bump(sc, ptr, len) 299 struct sfas_softc *sc; 300 vm_offset_t ptr; 301 int len; 302 { 303 int p; 304 305 p = (int)ptr & 0x03; 306 307 if (p) { 308 p = 4-p; 309 310 if (len < 256) 311 p = len; 312 } 313 314 return(p); 315 } 316 317 /* Interrupt driven routines */ 318 int 319 bzsc_build_dma_chain(sc, chain, p, l) 320 struct sfas_softc *sc; 321 struct sfas_dma_chain *chain; 322 void *p; 323 int l; 324 { 325 int n; 326 327 if (!l) 328 return(0); 329 330 #define set_link(n, p, l, f)\ 331 do { chain[n].ptr = (p); chain[n].len = (l); chain[n++].flg = (f); } while(0) 332 333 n = 0; 334 335 if (l < 512) 336 set_link(n, (vm_offset_t)p, l, SFAS_CHAIN_BUMP); 337 else if ( 338 #if defined(M68040) || defined(M68060) 339 ((mmutype == MMU_68040) && ((vm_offset_t)p >= 0xFFFC0000)) && 340 #endif 341 ((vm_offset_t)p >= 0xFF000000)) { 342 int len; 343 344 while(l) { 345 len = ((l > sc->sc_bump_sz) ? sc->sc_bump_sz : l); 346 347 set_link(n, (vm_offset_t)p, len, SFAS_CHAIN_BUMP); 348 349 p += len; 350 l -= len; 351 } 352 } else { 353 char *ptr; 354 vm_offset_t pa, lastpa; 355 int len, prelen, max_t; 356 357 ptr = p; 358 len = l; 359 360 pa = kvtop(ptr); 361 prelen = ((int)ptr & 0x03); 362 363 if (prelen) { 364 prelen = 4-prelen; 365 set_link(n, (vm_offset_t)ptr, prelen, SFAS_CHAIN_BUMP); 366 ptr += prelen; 367 len -= prelen; 368 } 369 370 lastpa = 0; 371 while(len > 3) { 372 pa = kvtop(ptr); 373 max_t = NBPG - (pa & PGOFSET); 374 if (max_t > len) 375 max_t = len; 376 377 max_t &= ~3; 378 379 if (lastpa == pa) 380 sc->sc_chain[n-1].len += max_t; 381 else 382 set_link(n, pa, max_t, SFAS_CHAIN_DMA); 383 384 lastpa = pa+max_t; 385 386 ptr += max_t; 387 len -= max_t; 388 } 389 390 if (len) 391 set_link(n, (vm_offset_t)ptr, len, SFAS_CHAIN_BUMP); 392 } 393 394 return(n); 395 } 396 397 /* Turn on led */ 398 void bzsc_led_dummy(sc, mode) 399 struct sfas_softc *sc; 400 int mode; 401 { 402 } 403
Indexes created Tue Sep 30 17:09:57 GMT 2025