bzsc.c revision 1.9
1 /* $NetBSD: bzsc.c,v 1.9 1996/07/01 08:00:02 is Exp $ */ 2 3 /* 4 * Copyright (c) 1995 Daniel Widenfalk 5 * Copyright (c) 1994 Christian E. Hopps 6 * Copyright (c) 1982, 1990 The Regents of the University of California. 7 * All rights reserved. 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions 11 * are met: 12 * 1. Redistributions of source code must retain the above copyright 13 * notice, this list of conditions and the following disclaimer. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 3. All advertising materials mentioning features or use of this software 18 * must display the following acknowledgement: 19 * This product includes software developed by the University of 20 * California, Berkeley and its contributors. 21 * 4. Neither the name of the University nor the names of its contributors 22 * may be used to endorse or promote products derived from this software 23 * without specific prior written permission. 24 * 25 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 26 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 27 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 28 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 29 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 30 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 31 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 32 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 33 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 34 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 35 * SUCH DAMAGE. 36 * 37 * @(#)dma.c 38 */ 39 40 #include <sys/param.h> 41 #include <sys/systm.h> 42 #include <sys/kernel.h> 43 #include <sys/device.h> 44 #include <scsi/scsi_all.h> 45 #include <scsi/scsiconf.h> 46 #include <vm/vm.h> 47 #include <vm/vm_kern.h> 48 #include <vm/vm_page.h> 49 #include <machine/pmap.h> 50 #include <amiga/amiga/custom.h> 51 #include <amiga/amiga/cc.h> 52 #include <amiga/amiga/device.h> 53 #include <amiga/amiga/isr.h> 54 #include <amiga/dev/sfasreg.h> 55 #include <amiga/dev/sfasvar.h> 56 #include <amiga/dev/zbusvar.h> 57 #include <amiga/dev/bzscreg.h> 58 #include <amiga/dev/bzscvar.h> 59 60 int bzscprint __P((void *auxp, char *)); 61 void bzscattach __P((struct device *, struct device *, void *)); 62 int bzscmatch __P((struct device *, void *, void *)); 63 64 struct scsi_adapter bzsc_scsiswitch = { 65 sfas_scsicmd, 66 sfas_minphys, 67 0, /* no lun support */ 68 0, /* no lun support */ 69 }; 70 71 struct scsi_device bzsc_scsidev = { 72 NULL, /* use default error handler */ 73 NULL, /* do not have a start functio */ 74 NULL, /* have no async handler */ 75 NULL, /* Use default done routine */ 76 }; 77 78 struct cfattach bzsc_ca = { 79 sizeof(struct bzsc_softc), bzscmatch, bzscattach 80 }; 81 82 struct cfdriver bzsc_cd = { 83 NULL, "bzsc", DV_DULL, NULL, 0 84 }; 85 86 int bzsc_intr __P((void *)); 87 void bzsc_set_dma_adr __P((struct sfas_softc *sc, vm_offset_t ptr, int mode)); 88 void bzsc_set_dma_tc __P((struct sfas_softc *sc, unsigned int len)); 89 int bzsc_setup_dma __P((struct sfas_softc *sc, vm_offset_t ptr, int len, 90 int mode)); 91 int bzsc_build_dma_chain __P((struct sfas_softc *sc, 92 struct sfas_dma_chain *chain, void *p, int l)); 93 int bzsc_need_bump __P((struct sfas_softc *sc, vm_offset_t ptr, int len)); 94 void bzsc_led_dummy __P((struct sfas_softc *sc, int mode)); 95 96 /* 97 * if we are an Advanced Systems & Software FastlaneZ3 98 */ 99 int 100 bzscmatch(pdp, match, auxp) 101 struct device *pdp; 102 void *match, *auxp; 103 { 104 struct zbus_args *zap; 105 vu_char *ta; 106 107 if (!is_a1200()) 108 return(0); 109 110 zap = auxp; 111 if (zap->manid != 0x2140 || zap->prodid != 11) 112 return(0); 113 114 ta = (vu_char *)(((char *)zap->va)+0x10010); 115 if (badbaddr((caddr_t)ta)) 116 return(0); 117 118 *ta = 0; 119 *ta = 1; 120 DELAY(5); 121 if (*ta != 1) 122 return(0); 123 124 return(1); 125 } 126 127 void 128 bzscattach(pdp, dp, auxp) 129 struct device *pdp; 130 struct device *dp; 131 void *auxp; 132 { 133 struct bzsc_softc *sc; 134 struct zbus_args *zap; 135 bzsc_regmap_p rp; 136 vu_char *fas; 137 138 zap = auxp; 139 fas = (vu_char *)(((char *)zap->va)+0x10000); 140 141 sc = (struct bzsc_softc *)dp; 142 rp = &sc->sc_regmap; 143 144 rp->FAS216.sfas_tc_low = &fas[0x00]; 145 rp->FAS216.sfas_tc_mid = &fas[0x02]; 146 rp->FAS216.sfas_fifo = &fas[0x04]; 147 rp->FAS216.sfas_command = &fas[0x06]; 148 rp->FAS216.sfas_dest_id = &fas[0x08]; 149 rp->FAS216.sfas_timeout = &fas[0x0A]; 150 rp->FAS216.sfas_syncper = &fas[0x0C]; 151 rp->FAS216.sfas_syncoff = &fas[0x0E]; 152 rp->FAS216.sfas_config1 = &fas[0x10]; 153 rp->FAS216.sfas_clkconv = &fas[0x12]; 154 rp->FAS216.sfas_test = &fas[0x14]; 155 rp->FAS216.sfas_config2 = &fas[0x16]; 156 rp->FAS216.sfas_config3 = &fas[0x18]; 157 rp->FAS216.sfas_tc_high = &fas[0x1C]; 158 rp->FAS216.sfas_fifo_bot = &fas[0x1E]; 159 rp->cclkaddr = &fas[0x21]; 160 rp->epowaddr = &fas[0x31]; 161 162 sc->sc_softc.sc_fas = (sfas_regmap_p)rp; 163 sc->sc_softc.sc_spec = 0; 164 165 sc->sc_softc.sc_led = bzsc_led_dummy; 166 167 sc->sc_softc.sc_setup_dma = bzsc_setup_dma; 168 sc->sc_softc.sc_build_dma_chain = bzsc_build_dma_chain; 169 sc->sc_softc.sc_need_bump = bzsc_need_bump; 170 171 sc->sc_softc.sc_clock_freq = 40; /* BlizzardII 1230 runs at 40MHz? */ 172 sc->sc_softc.sc_timeout = 250; /* Set default timeout to 250ms */ 173 sc->sc_softc.sc_config_flags = 0; 174 sc->sc_softc.sc_host_id = 7; 175 176 sc->sc_softc.sc_bump_sz = NBPG; 177 sc->sc_softc.sc_bump_pa = 0x0; 178 179 sfasinitialize((struct sfas_softc *)sc); 180 181 sc->sc_softc.sc_link.adapter_softc = sc; 182 sc->sc_softc.sc_link.adapter_target = sc->sc_softc.sc_host_id; 183 sc->sc_softc.sc_link.adapter = &bzsc_scsiswitch; 184 sc->sc_softc.sc_link.device = &bzsc_scsidev; 185 sc->sc_softc.sc_link.openings = 1; 186 187 printf("\n"); 188 189 sc->sc_softc.sc_isr.isr_intr = bzsc_intr; 190 sc->sc_softc.sc_isr.isr_arg = &sc->sc_softc; 191 sc->sc_softc.sc_isr.isr_ipl = 2; 192 add_isr(&sc->sc_softc.sc_isr); 193 194 /* attach all scsi units on us */ 195 config_found(dp, &sc->sc_softc.sc_link, bzscprint); 196 } 197 198 /* print diag if pnp is NULL else just extra */ 199 int 200 bzscprint(auxp, pnp) 201 void *auxp; 202 char *pnp; 203 { 204 if (pnp == NULL) 205 return(UNCONF); 206 207 return(QUIET); 208 } 209 210 int 211 bzsc_intr(arg) 212 void *arg; 213 { 214 struct sfas_softc *dev = arg; 215 bzsc_regmap_p rp; 216 int quickints; 217 218 rp = (bzsc_regmap_p)dev->sc_fas; 219 220 if (!(*rp->FAS216.sfas_status & SFAS_STAT_INTERRUPT_PENDING)) 221 return(0); 222 223 quickints = 16; 224 do { 225 dev->sc_status = *rp->FAS216.sfas_status; 226 dev->sc_interrupt = *rp->FAS216.sfas_interrupt; 227 228 if (dev->sc_interrupt & SFAS_INT_RESELECTED) { 229 dev->sc_resel[0] = *rp->FAS216.sfas_fifo; 230 dev->sc_resel[1] = *rp->FAS216.sfas_fifo; 231 } 232 sfasintr(dev); 233 } while((*rp->FAS216.sfas_status & SFAS_STAT_INTERRUPT_PENDING) && 234 --quickints); 235 236 return(1); 237 } 238 239 /* --------- */ 240 void 241 bzsc_set_dma_adr(sc, ptr, mode) 242 struct sfas_softc *sc; 243 vm_offset_t ptr; 244 int mode; 245 { 246 bzsc_regmap_p rp; 247 unsigned long p; 248 249 rp = (bzsc_regmap_p)sc->sc_fas; 250 251 p = ((unsigned long)ptr)>>1; 252 253 if (mode == SFAS_DMA_WRITE) 254 p |= BZSC_DMA_WRITE; 255 else 256 p |= BZSC_DMA_READ; 257 258 *rp->epowaddr = (u_char)(p>>24) & 0xFF; 259 *rp->cclkaddr = (u_char)(p>>16) & 0xFF; 260 *rp->cclkaddr = (u_char)(p>> 8) & 0xFF; 261 *rp->cclkaddr = (u_char)(p ) & 0xFF; 262 } 263 264 /* Set DMA transfer counter */ 265 void 266 bzsc_set_dma_tc(sc, len) 267 struct sfas_softc *sc; 268 unsigned int len; 269 { 270 *sc->sc_fas->sfas_tc_low = len; len >>= 8; 271 *sc->sc_fas->sfas_tc_mid = len; len >>= 8; 272 *sc->sc_fas->sfas_tc_high = len; 273 } 274 275 /* Initialize DMA for transfer */ 276 int 277 bzsc_setup_dma(sc, ptr, len, mode) 278 struct sfas_softc *sc; 279 vm_offset_t ptr; 280 int len; 281 int mode; 282 { 283 int retval; 284 285 retval = 0; 286 287 switch(mode) { 288 case SFAS_DMA_READ: 289 case SFAS_DMA_WRITE: 290 bzsc_set_dma_adr(sc, ptr, mode); 291 bzsc_set_dma_tc(sc, len); 292 break; 293 case SFAS_DMA_CLEAR: 294 default: 295 retval = (*sc->sc_fas->sfas_tc_high << 16) | 296 (*sc->sc_fas->sfas_tc_mid << 8) | 297 *sc->sc_fas->sfas_tc_low; 298 299 bzsc_set_dma_tc(sc, 0); 300 break; 301 } 302 303 return(retval); 304 } 305 306 /* Check if address and len is ok for DMA transfer */ 307 int 308 bzsc_need_bump(sc, ptr, len) 309 struct sfas_softc *sc; 310 vm_offset_t ptr; 311 int len; 312 { 313 int p; 314 315 p = (int)ptr & 0x03; 316 317 if (p) { 318 p = 4-p; 319 320 if (len < 256) 321 p = len; 322 } 323 324 return(p); 325 } 326 327 /* Interrupt driven routines */ 328 int 329 bzsc_build_dma_chain(sc, chain, p, l) 330 struct sfas_softc *sc; 331 struct sfas_dma_chain *chain; 332 void *p; 333 int l; 334 { 335 int n; 336 337 if (!l) 338 return(0); 339 340 #define set_link(n, p, l, f)\ 341 do { chain[n].ptr = (p); chain[n].len = (l); chain[n++].flg = (f); } while(0) 342 343 n = 0; 344 345 if (l < 512) 346 set_link(n, (vm_offset_t)p, l, SFAS_CHAIN_BUMP); 347 else if ( 348 #if defined(M68040) || defined(M68060) 349 ((mmutype == MMU_68040) && ((vm_offset_t)p >= 0xFFFC0000)) && 350 #endif 351 ((vm_offset_t)p >= 0xFF000000)) { 352 int len; 353 354 while(l) { 355 len = ((l > sc->sc_bump_sz) ? sc->sc_bump_sz : l); 356 357 set_link(n, (vm_offset_t)p, len, SFAS_CHAIN_BUMP); 358 359 p += len; 360 l -= len; 361 } 362 } else { 363 char *ptr; 364 vm_offset_t pa, lastpa; 365 int len, prelen, max_t; 366 367 ptr = p; 368 len = l; 369 370 pa = kvtop(ptr); 371 prelen = ((int)ptr & 0x03); 372 373 if (prelen) { 374 prelen = 4-prelen; 375 set_link(n, (vm_offset_t)ptr, prelen, SFAS_CHAIN_BUMP); 376 ptr += prelen; 377 len -= prelen; 378 } 379 380 lastpa = 0; 381 while(len > 3) { 382 pa = kvtop(ptr); 383 max_t = NBPG - (pa & PGOFSET); 384 if (max_t > len) 385 max_t = len; 386 387 max_t &= ~3; 388 389 if (lastpa == pa) 390 sc->sc_chain[n-1].len += max_t; 391 else 392 set_link(n, pa, max_t, SFAS_CHAIN_DMA); 393 394 lastpa = pa+max_t; 395 396 ptr += max_t; 397 len -= max_t; 398 } 399 400 if (len) 401 set_link(n, (vm_offset_t)ptr, len, SFAS_CHAIN_BUMP); 402 } 403 404 return(n); 405 } 406 407 /* Turn on led */ 408 void bzsc_led_dummy(sc, mode) 409 struct sfas_softc *sc; 410 int mode; 411 { 412 } 413
Indexes created Tue Sep 30 20:09:53 GMT 2025