bztzsc.c revision 1.4
1 /* $NetBSD: bztzsc.c,v 1.4 1997/08/27 11:23:05 bouyer Exp $ */ 2 3 /* 4 * Copyright (c) 1996 Ignatios Souvatzis 5 * Copyright (c) 1982, 1990 The Regents of the University of California. 6 * All rights reserved. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 3. All advertising materials mentioning features or use of this software 17 * must display the following acknowledgement: 18 * This product contains software written by Ignatios Souvatzis for 19 * the NetBSD project. 20 * 4. Neither the name of the University nor the names of its contributors 21 * may be used to endorse or promote products derived from this software 22 * without specific prior written permission. 23 * 24 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 25 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 26 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 27 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 28 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 29 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 30 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 31 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 32 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 33 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 34 * SUCH DAMAGE. 35 * 36 */ 37 38 #include <sys/param.h> 39 #include <sys/systm.h> 40 #include <sys/kernel.h> 41 #include <sys/device.h> 42 #include <dev/scsipi/scsi_all.h> 43 #include <dev/scsipi/scsipi_all.h> 44 #include <dev/scsipi/scsiconf.h> 45 #include <vm/vm.h> 46 #include <vm/vm_kern.h> 47 #include <vm/vm_page.h> 48 #include <machine/pmap.h> 49 #include <amiga/amiga/custom.h> 50 #include <amiga/amiga/cc.h> 51 #include <amiga/amiga/device.h> 52 #include <amiga/amiga/isr.h> 53 #include <amiga/dev/sfasreg.h> 54 #include <amiga/dev/sfasvar.h> 55 #include <amiga/dev/zbusvar.h> 56 #include <amiga/dev/bztzscreg.h> 57 #include <amiga/dev/bztzscvar.h> 58 59 void bztzscattach __P((struct device *, struct device *, void *)); 60 int bztzscmatch __P((struct device *, struct cfdata *, void *)); 61 62 struct scsipi_adapter bztzsc_scsiswitch = { 63 sfas_scsicmd, 64 sfas_minphys, 65 0, /* no lun support */ 66 0, /* no lun support */ 67 }; 68 69 struct scsipi_device bztzsc_scsidev = { 70 NULL, /* use default error handler */ 71 NULL, /* do not have a start functio */ 72 NULL, /* have no async handler */ 73 NULL, /* Use default done routine */ 74 }; 75 76 struct cfattach bztzsc_ca = { 77 sizeof(struct bztzsc_softc), bztzscmatch, bztzscattach 78 }; 79 80 struct cfdriver bztzsc_cd = { 81 NULL, "bztzsc", DV_DULL, NULL, 0 82 }; 83 84 int bztzsc_intr __P((void *)); 85 void bztzsc_set_dma_tc __P((struct sfas_softc *sc, unsigned int len)); 86 int bztzsc_setup_dma __P((struct sfas_softc *sc, vm_offset_t ptr, int len, 87 int mode)); 88 int bztzsc_build_dma_chain __P((struct sfas_softc *sc, 89 struct sfas_dma_chain *chain, void *p, int l)); 90 int bztzsc_need_bump __P((struct sfas_softc *sc, vm_offset_t ptr, int len)); 91 void bztzsc_led __P((struct sfas_softc *sc, int mode)); 92 93 /* 94 * If we are an Phase 5 Devices Blizzard-2060 SCSI option: 95 */ 96 int 97 bztzscmatch(pdp, cfp, auxp) 98 struct device *pdp; 99 struct cfdata *cfp; 100 void *auxp; 101 { 102 struct zbus_args *zap; 103 volatile u_int8_t *ta; 104 105 zap = auxp; 106 107 if (zap->manid != 0x2140) /* Phase V ? */ 108 return(0); 109 110 111 if (zap->prodid != 24) /* is it B2060? */ 112 return 0; 113 114 ta = (vu_char *)(((char *)zap->va) + 0x1ff00 + 0x20); 115 116 if (badbaddr((caddr_t)ta)) 117 return(0); 118 119 *ta = 0; 120 *ta = 1; 121 DELAY(5); 122 if (*ta != 1) 123 return(0); 124 125 return(1); 126 } 127 128 u_int32_t bztzsc_flags = 0; 129 130 void 131 bztzscattach(pdp, dp, auxp) 132 struct device *pdp; 133 struct device *dp; 134 void *auxp; 135 { 136 struct bztzsc_softc *sc; 137 struct zbus_args *zap; 138 bztzsc_regmap_p rp; 139 vu_char *fas; 140 141 zap = auxp; 142 143 fas = &((vu_char *)zap->va)[0x1ff00]; 144 145 sc = (struct bztzsc_softc *)dp; 146 rp = &sc->sc_regmap; 147 148 rp->FAS216.sfas_tc_low = &fas[0x00]; 149 rp->FAS216.sfas_tc_mid = &fas[0x04]; 150 rp->FAS216.sfas_fifo = &fas[0x08]; 151 rp->FAS216.sfas_command = &fas[0x0C]; 152 rp->FAS216.sfas_dest_id = &fas[0x10]; 153 rp->FAS216.sfas_timeout = &fas[0x14]; 154 rp->FAS216.sfas_syncper = &fas[0x18]; 155 rp->FAS216.sfas_syncoff = &fas[0x1C]; 156 rp->FAS216.sfas_config1 = &fas[0x20]; 157 rp->FAS216.sfas_clkconv = &fas[0x24]; 158 rp->FAS216.sfas_test = &fas[0x28]; 159 rp->FAS216.sfas_config2 = &fas[0x2C]; 160 rp->FAS216.sfas_config3 = &fas[0x30]; 161 rp->FAS216.sfas_tc_high = &fas[0x38]; 162 rp->FAS216.sfas_fifo_bot = &fas[0x3C]; 163 164 rp->hardbits = &fas[0xe0]; 165 rp->addrport = &fas[0xf0]; 166 167 sc->sc_softc.sc_fas = (sfas_regmap_p)rp; 168 169 sc->sc_softc.sc_led = bztzsc_led; 170 171 sc->sc_softc.sc_setup_dma = bztzsc_setup_dma; 172 sc->sc_softc.sc_build_dma_chain = bztzsc_build_dma_chain; 173 sc->sc_softc.sc_need_bump = bztzsc_need_bump; 174 175 sc->sc_softc.sc_clock_freq = 40; /* Phase5 SCSI all run at 40MHz */ 176 sc->sc_softc.sc_timeout = 250; /* Set default timeout to 250ms */ 177 178 sc->sc_softc.sc_config_flags = bztzsc_flags; /* for the moment */ 179 180 sc->sc_softc.sc_host_id = 7; /* Should check the jumpers */ 181 182 sc->sc_softc.sc_bump_sz = NBPG; /* XXX should be the VM pagesize */ 183 sc->sc_softc.sc_bump_pa = 0x0; 184 185 sfasinitialize((struct sfas_softc *)sc); 186 187 sc->sc_softc.sc_link.adapter_softc = sc; 188 sc->sc_softc.sc_link.scsipi_scsi.adapter_target = sc->sc_softc.sc_host_id; 189 sc->sc_softc.sc_link.adapter = &bztzsc_scsiswitch; 190 sc->sc_softc.sc_link.device = &bztzsc_scsidev; 191 sc->sc_softc.sc_link.openings = 1; 192 sc->sc_softc.sc_link.scsipi_scsi.max_target = 7; 193 sc->sc_softc.sc_link.type = BUS_SCSI; 194 195 sc->sc_softc.sc_isr.isr_intr = bztzsc_intr; 196 sc->sc_softc.sc_isr.isr_arg = &sc->sc_softc; 197 sc->sc_softc.sc_isr.isr_ipl = 2; 198 add_isr(&sc->sc_softc.sc_isr); 199 200 /* We don't want interrupt until we're initialized! */ 201 202 printf("\n"); 203 204 /* attach all scsi units on us */ 205 config_found(dp, &sc->sc_softc.sc_link, scsiprint); 206 } 207 208 int 209 bztzsc_intr(arg) 210 void *arg; 211 { 212 struct sfas_softc *dev = arg; 213 bztzsc_regmap_p rp; 214 int quickints; 215 216 rp = (bztzsc_regmap_p)dev->sc_fas; 217 218 if (*rp->FAS216.sfas_status & SFAS_STAT_INTERRUPT_PENDING) { 219 quickints = 16; 220 do { 221 dev->sc_status = *rp->FAS216.sfas_status; 222 dev->sc_interrupt = *rp->FAS216.sfas_interrupt; 223 224 if (dev->sc_interrupt & SFAS_INT_RESELECTED) { 225 dev->sc_resel[0] = *rp->FAS216.sfas_fifo; 226 dev->sc_resel[1] = *rp->FAS216.sfas_fifo; 227 } 228 sfasintr(dev); 229 230 } while((*rp->FAS216.sfas_status & SFAS_STAT_INTERRUPT_PENDING) 231 && --quickints); 232 233 return(1); 234 } 235 return(0); 236 } 237 238 /* Set DMA transfer counter */ 239 void 240 bztzsc_set_dma_tc(sc, len) 241 struct sfas_softc *sc; 242 unsigned int len; 243 { 244 *sc->sc_fas->sfas_tc_low = len; len >>= 8; 245 *sc->sc_fas->sfas_tc_mid = len; len >>= 8; 246 *sc->sc_fas->sfas_tc_high = len; 247 } 248 249 /* Initialize DMA for transfer */ 250 int 251 bztzsc_setup_dma(sc, ptr, len, mode) 252 struct sfas_softc *sc; 253 vm_offset_t ptr; 254 int len; 255 int mode; 256 { 257 int retval; 258 u_int32_t d; 259 bztzsc_regmap_p rp; 260 261 retval = 0; 262 263 switch(mode) { 264 265 case SFAS_DMA_READ: 266 case SFAS_DMA_WRITE: 267 268 rp = (bztzsc_regmap_p)sc->sc_fas; 269 270 d = (u_int32_t)ptr; 271 d >>= 1; 272 273 if (mode == SFAS_DMA_WRITE) 274 d |= (1L << 31); 275 276 rp->addrport[12] = (u_int8_t)d; 277 __asm __volatile("nop"); 278 279 d >>= 8; 280 rp->addrport[8] = (u_int8_t)d; 281 __asm __volatile("nop"); 282 283 d >>= 8; 284 rp->addrport[4] = (u_int8_t)d; 285 __asm __volatile("nop"); 286 287 d >>= 8; 288 rp->addrport[0] = (u_int8_t)d; 289 __asm __volatile("nop"); 290 291 bztzsc_set_dma_tc(sc, len); 292 break; 293 294 case SFAS_DMA_CLEAR: 295 default: 296 retval = (*sc->sc_fas->sfas_tc_high << 16) | 297 (*sc->sc_fas->sfas_tc_mid << 8) | 298 *sc->sc_fas->sfas_tc_low; 299 300 bztzsc_set_dma_tc(sc, 0); 301 break; 302 } 303 304 return(retval); 305 } 306 307 /* Check if address and len is ok for DMA transfer */ 308 int 309 bztzsc_need_bump(sc, ptr, len) 310 struct sfas_softc *sc; 311 vm_offset_t ptr; 312 int len; 313 { 314 int p; 315 316 p = (int)ptr & 0x03; 317 318 if (p) { 319 p = 4-p; 320 321 if (len < 256) 322 p = len; 323 } 324 return(p); 325 } 326 327 /* Interrupt driven routines */ 328 /* XXX some of this is voodoo might be remnants intended for the Fastlane. */ 329 int 330 bztzsc_build_dma_chain(sc, chain, p, l) 331 struct sfas_softc *sc; 332 struct sfas_dma_chain *chain; 333 void *p; 334 int l; 335 { 336 vm_offset_t pa, lastpa; 337 char *ptr; 338 int len, prelen, max_t, n; 339 340 if (l == 0) 341 return(0); 342 343 #define set_link(n, p, l, f)\ 344 do { chain[n].ptr = (p); chain[n].len = (l); chain[n++].flg = (f); } while(0) 345 346 n = 0; 347 348 if (l < 512) 349 set_link(n, (vm_offset_t)p, l, SFAS_CHAIN_BUMP); 350 else if ((p >= (void *)0xFF000000) 351 #if defined(M68040) || defined(M68060) 352 && ((mmutype == MMU_68040) && (p >= (void *)0xFFFC0000)) 353 #endif 354 ) { 355 while(l != 0) { 356 len = ((l > sc->sc_bump_sz) ? sc->sc_bump_sz : l); 357 358 set_link(n, (vm_offset_t)p, len, SFAS_CHAIN_BUMP); 359 360 p += len; 361 l -= len; 362 } 363 } else { 364 ptr = p; 365 len = l; 366 367 pa = kvtop(ptr); 368 prelen = ((int)ptr & 0x03); 369 370 if (prelen) { 371 prelen = 4-prelen; 372 set_link(n, (vm_offset_t)ptr, prelen, SFAS_CHAIN_BUMP); 373 ptr += prelen; 374 len -= prelen; 375 } 376 377 lastpa = 0; 378 while(len > 3) { 379 pa = kvtop(ptr); 380 max_t = NBPG - (pa & PGOFSET); 381 if (max_t > len) 382 max_t = len; 383 384 max_t &= ~3; 385 386 if (lastpa == pa) 387 sc->sc_chain[n-1].len += max_t; 388 else 389 set_link(n, pa, max_t, SFAS_CHAIN_DMA); 390 391 lastpa = pa+max_t; 392 393 ptr += max_t; 394 len -= max_t; 395 } 396 397 if (len) 398 set_link(n, (vm_offset_t)ptr, len, SFAS_CHAIN_BUMP); 399 } 400 401 return(n); 402 } 403 404 /* real one for 2060 */ 405 void 406 bztzsc_led(sc, mode) 407 struct sfas_softc *sc; 408 int mode; 409 { 410 bztzsc_regmap_p rp; 411 412 rp = (bztzsc_regmap_p)sc->sc_fas; 413 414 if (mode) 415 *rp->hardbits = 0x00; /* Led on, Int on */ 416 else 417 *rp->hardbits = 0x02; /* Led off, Int on */ 418 } 419
Indexes created Thu Oct 02 01:09:59 GMT 2025