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cbiisc.c revision 1.1.4.1
      1  1.1.4.1  mellon /*	$NetBSD: cbiisc.c,v 1.1.4.1 1997/10/24 03:05:02 mellon Exp $	*/
      2      1.1  mhitch 
      3      1.1  mhitch /*
      4      1.1  mhitch  * Copyright (c) 1997 Michael L. Hitch
      5      1.1  mhitch  * Copyright (c) 1982, 1990 The Regents of the University of California.
      6      1.1  mhitch  * All rights reserved.
      7      1.1  mhitch  *
      8      1.1  mhitch  * Redistribution and use in source and binary forms, with or without
      9      1.1  mhitch  * modification, are permitted provided that the following conditions
     10      1.1  mhitch  * are met:
     11      1.1  mhitch  * 1. Redistributions of source code must retain the above copyright
     12      1.1  mhitch  *    notice, this list of conditions and the following disclaimer.
     13      1.1  mhitch  * 2. Redistributions in binary form must reproduce the above copyright
     14      1.1  mhitch  *    notice, this list of conditions and the following disclaimer in the
     15      1.1  mhitch  *    documentation and/or other materials provided with the distribution.
     16      1.1  mhitch  * 3. All advertising materials mentioning features or use of this software
     17      1.1  mhitch  *    must display the following acknowledgement:
     18      1.1  mhitch  *	This product contains software written by Michael L. Hitch for
     19      1.1  mhitch  *	the NetBSD project.
     20      1.1  mhitch  * 4. Neither the name of the University nor the names of its contributors
     21      1.1  mhitch  *    may be used to endorse or promote products derived from this software
     22      1.1  mhitch  *    without specific prior written permission.
     23      1.1  mhitch  *
     24      1.1  mhitch  * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
     25      1.1  mhitch  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
     26      1.1  mhitch  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
     27      1.1  mhitch  * ARE DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
     28      1.1  mhitch  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
     29      1.1  mhitch  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
     30      1.1  mhitch  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
     31      1.1  mhitch  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
     32      1.1  mhitch  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
     33      1.1  mhitch  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
     34      1.1  mhitch  * SUCH DAMAGE.
     35      1.1  mhitch  *
     36      1.1  mhitch  */
     37      1.1  mhitch 
     38      1.1  mhitch #include <sys/types.h>
     39      1.1  mhitch #include <sys/param.h>
     40      1.1  mhitch #include <sys/systm.h>
     41      1.1  mhitch #include <sys/kernel.h>
     42      1.1  mhitch #include <sys/errno.h>
     43      1.1  mhitch #include <sys/ioctl.h>
     44      1.1  mhitch #include <sys/device.h>
     45      1.1  mhitch #include <sys/buf.h>
     46      1.1  mhitch #include <sys/proc.h>
     47      1.1  mhitch #include <sys/user.h>
     48      1.1  mhitch #include <sys/queue.h>
     49      1.1  mhitch 
     50      1.1  mhitch #include <dev/scsipi/scsi_all.h>
     51      1.1  mhitch #include <dev/scsipi/scsipi_all.h>
     52      1.1  mhitch #include <dev/scsipi/scsiconf.h>
     53      1.1  mhitch #include <dev/scsipi/scsi_message.h>
     54      1.1  mhitch 
     55      1.1  mhitch #include <machine/cpu.h>
     56      1.1  mhitch #include <machine/param.h>
     57      1.1  mhitch 
     58      1.1  mhitch #include <dev/ic/ncr53c9xreg.h>
     59      1.1  mhitch #include <dev/ic/ncr53c9xvar.h>
     60      1.1  mhitch 
     61      1.1  mhitch #include <amiga/amiga/isr.h>
     62      1.1  mhitch #include <amiga/dev/cbiiscvar.h>
     63      1.1  mhitch #include <amiga/dev/zbusvar.h>
     64      1.1  mhitch 
     65      1.1  mhitch void	cbiiscattach	__P((struct device *, struct device *, void *));
     66      1.1  mhitch int	cbiiscmatch	__P((struct device *, struct cfdata *, void *));
     67      1.1  mhitch 
     68      1.1  mhitch /* Linkup to the rest of the kernel */
     69      1.1  mhitch struct cfattach cbiisc_ca = {
     70      1.1  mhitch 	sizeof(struct cbiisc_softc), cbiiscmatch, cbiiscattach
     71      1.1  mhitch };
     72      1.1  mhitch 
     73      1.1  mhitch struct cfdriver cbiisc_cd = {
     74      1.1  mhitch 	NULL, "cbiisc", DV_DULL
     75      1.1  mhitch };
     76      1.1  mhitch 
     77      1.1  mhitch struct scsipi_adapter cbiisc_switch = {
     78      1.1  mhitch 	ncr53c9x_scsi_cmd,
     79      1.1  mhitch 	minphys,		/* no max at this level; handled by DMA code */
     80      1.1  mhitch 	NULL,
     81      1.1  mhitch 	NULL,
     82      1.1  mhitch };
     83      1.1  mhitch 
     84      1.1  mhitch struct scsipi_device cbiisc_dev = {
     85      1.1  mhitch 	NULL,			/* Use default error handler */
     86      1.1  mhitch 	NULL,			/* have a queue, served by this */
     87      1.1  mhitch 	NULL,			/* have no async handler */
     88      1.1  mhitch 	NULL,			/* Use default 'done' routine */
     89      1.1  mhitch };
     90      1.1  mhitch 
     91      1.1  mhitch /*
     92      1.1  mhitch  * Functions and the switch for the MI code.
     93      1.1  mhitch  */
     94      1.1  mhitch u_char	cbiisc_read_reg __P((struct ncr53c9x_softc *, int));
     95      1.1  mhitch void	cbiisc_write_reg __P((struct ncr53c9x_softc *, int, u_char));
     96      1.1  mhitch int	cbiisc_dma_isintr __P((struct ncr53c9x_softc *));
     97      1.1  mhitch void	cbiisc_dma_reset __P((struct ncr53c9x_softc *));
     98      1.1  mhitch int	cbiisc_dma_intr __P((struct ncr53c9x_softc *));
     99      1.1  mhitch int	cbiisc_dma_setup __P((struct ncr53c9x_softc *, caddr_t *,
    100      1.1  mhitch 	    size_t *, int, size_t *));
    101      1.1  mhitch void	cbiisc_dma_go __P((struct ncr53c9x_softc *));
    102      1.1  mhitch void	cbiisc_dma_stop __P((struct ncr53c9x_softc *));
    103      1.1  mhitch int	cbiisc_dma_isactive __P((struct ncr53c9x_softc *));
    104      1.1  mhitch 
    105      1.1  mhitch struct ncr53c9x_glue cbiisc_glue = {
    106      1.1  mhitch 	cbiisc_read_reg,
    107      1.1  mhitch 	cbiisc_write_reg,
    108      1.1  mhitch 	cbiisc_dma_isintr,
    109      1.1  mhitch 	cbiisc_dma_reset,
    110      1.1  mhitch 	cbiisc_dma_intr,
    111      1.1  mhitch 	cbiisc_dma_setup,
    112      1.1  mhitch 	cbiisc_dma_go,
    113      1.1  mhitch 	cbiisc_dma_stop,
    114      1.1  mhitch 	cbiisc_dma_isactive,
    115      1.1  mhitch 	0,
    116      1.1  mhitch };
    117      1.1  mhitch 
    118      1.1  mhitch /* Maximum DMA transfer length to reduce impact on high-speed serial input */
    119      1.1  mhitch u_long cbiisc_max_dma = 1024;
    120      1.1  mhitch extern int ser_open_speed;
    121      1.1  mhitch 
    122      1.1  mhitch u_long cbiisc_cnt_pio = 0;	/* number of PIO transfers */
    123      1.1  mhitch u_long cbiisc_cnt_dma = 0;	/* number of DMA transfers */
    124      1.1  mhitch u_long cbiisc_cnt_dma2 = 0;	/* number of DMA transfers broken up */
    125      1.1  mhitch u_long cbiisc_cnt_dma3 = 0;	/* number of pages combined */
    126      1.1  mhitch 
    127      1.1  mhitch #ifdef DEBUG
    128      1.1  mhitch struct {
    129      1.1  mhitch 	u_char hardbits;
    130      1.1  mhitch 	u_char status;
    131      1.1  mhitch 	u_char xx;
    132      1.1  mhitch 	u_char yy;
    133      1.1  mhitch } cbiisc_trace[128];
    134      1.1  mhitch int cbiisc_trace_ptr = 0;
    135      1.1  mhitch int cbiisc_trace_enable = 1;
    136      1.1  mhitch void cbiisc_dump __P((void));
    137      1.1  mhitch #endif
    138      1.1  mhitch 
    139      1.1  mhitch /*
    140      1.1  mhitch  * if we are a Phase5 CyberSCSI II
    141      1.1  mhitch  */
    142      1.1  mhitch int
    143      1.1  mhitch cbiiscmatch(parent, cf, aux)
    144      1.1  mhitch 	struct device *parent;
    145      1.1  mhitch 	struct cfdata *cf;
    146      1.1  mhitch 	void *aux;
    147      1.1  mhitch {
    148      1.1  mhitch 	struct zbus_args *zap;
    149      1.1  mhitch 	volatile u_char *regs;
    150      1.1  mhitch 
    151      1.1  mhitch 	zap = aux;
    152  1.1.4.1  mellon 	if (zap->manid != 0x2140 || zap->prodid != 25)
    153      1.1  mhitch 		return(0);
    154      1.1  mhitch 	regs = &((volatile u_char *)zap->va)[0x1ff03];
    155      1.1  mhitch 	if (badaddr((caddr_t)regs))
    156      1.1  mhitch 		return(0);
    157      1.1  mhitch 	regs[NCR_CFG1 * 4] = 0;
    158      1.1  mhitch 	regs[NCR_CFG1 * 4] = NCRCFG1_PARENB | 7;
    159      1.1  mhitch 	delay(5);
    160      1.1  mhitch 	if (regs[NCR_CFG1 * 4] != (NCRCFG1_PARENB | 7))
    161      1.1  mhitch 		return(0);
    162      1.1  mhitch 	return(1);
    163      1.1  mhitch }
    164      1.1  mhitch 
    165      1.1  mhitch /*
    166      1.1  mhitch  * Attach this instance, and then all the sub-devices
    167      1.1  mhitch  */
    168      1.1  mhitch void
    169      1.1  mhitch cbiiscattach(parent, self, aux)
    170      1.1  mhitch 	struct device *parent, *self;
    171      1.1  mhitch 	void *aux;
    172      1.1  mhitch {
    173      1.1  mhitch 	struct cbiisc_softc *csc = (void *)self;
    174      1.1  mhitch 	struct ncr53c9x_softc *sc = &csc->sc_ncr53c9x;
    175      1.1  mhitch 	struct zbus_args  *zap;
    176      1.1  mhitch 	extern u_long scsi_nosync;
    177      1.1  mhitch 	extern int shift_nosync;
    178      1.1  mhitch 	extern int ncr53c9x_debug;
    179      1.1  mhitch 
    180      1.1  mhitch 	/*
    181      1.1  mhitch 	 * Set up the glue for MI code early; we use some of it here.
    182      1.1  mhitch 	 */
    183      1.1  mhitch 	sc->sc_glue = &cbiisc_glue;
    184      1.1  mhitch 
    185      1.1  mhitch 	/*
    186      1.1  mhitch 	 * Save the regs
    187      1.1  mhitch 	 */
    188      1.1  mhitch 	zap = aux;
    189      1.1  mhitch 	csc->sc_reg = &((volatile u_char *)zap->va)[0x1ff03];
    190      1.1  mhitch 	csc->sc_dmabase = &csc->sc_reg[0x80];
    191      1.1  mhitch 
    192      1.1  mhitch 	sc->sc_freq = 40;		/* Clocked at 40Mhz */
    193      1.1  mhitch 
    194      1.1  mhitch 	printf(": address %p", csc->sc_reg);
    195      1.1  mhitch 
    196      1.1  mhitch 	sc->sc_id = 7;
    197      1.1  mhitch 
    198      1.1  mhitch 	/*
    199      1.1  mhitch 	 * It is necessary to try to load the 2nd config register here,
    200      1.1  mhitch 	 * to find out what rev the FAS chip is, else the ncr53c9x_reset
    201      1.1  mhitch 	 * will not set up the defaults correctly.
    202      1.1  mhitch 	 */
    203      1.1  mhitch 	sc->sc_cfg1 = sc->sc_id | NCRCFG1_PARENB;
    204      1.1  mhitch 	sc->sc_cfg2 = NCRCFG2_SCSI2 | NCRCFG2_FE;
    205      1.1  mhitch 	sc->sc_cfg3 = 0x08 /*FCLK*/ | NCRESPCFG3_FSCSI | NCRESPCFG3_CDB;
    206      1.1  mhitch 	sc->sc_rev = NCR_VARIANT_FAS216;
    207      1.1  mhitch 
    208      1.1  mhitch 	/*
    209      1.1  mhitch 	 * This is the value used to start sync negotiations
    210      1.1  mhitch 	 * Note that the NCR register "SYNCTP" is programmed
    211      1.1  mhitch 	 * in "clocks per byte", and has a minimum value of 4.
    212      1.1  mhitch 	 * The SCSI period used in negotiation is one-fourth
    213      1.1  mhitch 	 * of the time (in nanoseconds) needed to transfer one byte.
    214      1.1  mhitch 	 * Since the chip's clock is given in MHz, we have the following
    215      1.1  mhitch 	 * formula: 4 * period = (1000 / freq) * 4
    216      1.1  mhitch 	 */
    217      1.1  mhitch 	sc->sc_minsync = 1000 / sc->sc_freq;
    218      1.1  mhitch 
    219      1.1  mhitch 	/*
    220      1.1  mhitch 	 * get flags from -I argument and set cf_flags.
    221      1.1  mhitch 	 * NOTE: low 8 bits are to disable disconnect, and the next
    222      1.1  mhitch 	 *       8 bits are to disable sync.
    223      1.1  mhitch 	 */
    224      1.1  mhitch 	sc->sc_dev.dv_cfdata->cf_flags |= (scsi_nosync >> shift_nosync)
    225      1.1  mhitch 	    & 0xffff;
    226      1.1  mhitch 	shift_nosync += 16;
    227      1.1  mhitch 
    228      1.1  mhitch 	/* Use next 16 bits of -I argument to set ncr53c9x_debug flags */
    229      1.1  mhitch 	ncr53c9x_debug |= (scsi_nosync >> shift_nosync) & 0xffff;
    230      1.1  mhitch 	shift_nosync += 16;
    231      1.1  mhitch 
    232      1.1  mhitch #if 1
    233      1.1  mhitch 	if (((scsi_nosync >> shift_nosync) & 0xff00) == 0xff00)
    234      1.1  mhitch 		sc->sc_minsync = 0;
    235      1.1  mhitch #endif
    236      1.1  mhitch 
    237      1.1  mhitch 	/* Really no limit, but since we want to fit into the TCR... */
    238      1.1  mhitch 	sc->sc_maxxfer = 64 * 1024;
    239      1.1  mhitch 
    240      1.1  mhitch 	/*
    241      1.1  mhitch 	 * Configure interrupts.
    242      1.1  mhitch 	 */
    243      1.1  mhitch 	csc->sc_isr.isr_intr = (int (*)(void *))ncr53c9x_intr;
    244      1.1  mhitch 	csc->sc_isr.isr_arg  = sc;
    245      1.1  mhitch 	csc->sc_isr.isr_ipl  = 2;
    246      1.1  mhitch 	add_isr(&csc->sc_isr);
    247      1.1  mhitch 
    248      1.1  mhitch 	/*
    249      1.1  mhitch 	 * Now try to attach all the sub-devices
    250      1.1  mhitch 	 */
    251      1.1  mhitch 	ncr53c9x_attach(sc, &cbiisc_switch, &cbiisc_dev);
    252      1.1  mhitch }
    253      1.1  mhitch 
    254      1.1  mhitch /*
    255      1.1  mhitch  * Glue functions.
    256      1.1  mhitch  */
    257      1.1  mhitch 
    258      1.1  mhitch u_char
    259      1.1  mhitch cbiisc_read_reg(sc, reg)
    260      1.1  mhitch 	struct ncr53c9x_softc *sc;
    261      1.1  mhitch 	int reg;
    262      1.1  mhitch {
    263      1.1  mhitch 	struct cbiisc_softc *csc = (struct cbiisc_softc *)sc;
    264      1.1  mhitch 
    265      1.1  mhitch 	return csc->sc_reg[reg * 4];
    266      1.1  mhitch }
    267      1.1  mhitch 
    268      1.1  mhitch void
    269      1.1  mhitch cbiisc_write_reg(sc, reg, val)
    270      1.1  mhitch 	struct ncr53c9x_softc *sc;
    271      1.1  mhitch 	int reg;
    272      1.1  mhitch 	u_char val;
    273      1.1  mhitch {
    274      1.1  mhitch 	struct cbiisc_softc *csc = (struct cbiisc_softc *)sc;
    275      1.1  mhitch 	u_char v = val;
    276      1.1  mhitch 
    277      1.1  mhitch 	csc->sc_reg[reg * 4] = v;
    278      1.1  mhitch #ifdef DEBUG
    279      1.1  mhitch if (cbiisc_trace_enable/* && sc->sc_nexus && sc->sc_nexus->xs->flags & SCSI_POLL*/ &&
    280      1.1  mhitch   reg == NCR_CMD/* && csc->sc_active*/) {
    281      1.1  mhitch   cbiisc_trace[(cbiisc_trace_ptr - 1) & 127].yy = v;
    282      1.1  mhitch /*  printf(" cmd %x", v);*/
    283      1.1  mhitch }
    284      1.1  mhitch #endif
    285      1.1  mhitch }
    286      1.1  mhitch 
    287      1.1  mhitch int
    288      1.1  mhitch cbiisc_dma_isintr(sc)
    289      1.1  mhitch 	struct ncr53c9x_softc *sc;
    290      1.1  mhitch {
    291      1.1  mhitch 	struct cbiisc_softc *csc = (struct cbiisc_softc *)sc;
    292      1.1  mhitch 
    293      1.1  mhitch 	if ((csc->sc_reg[NCR_STAT * 4] & NCRSTAT_INT) == 0)
    294      1.1  mhitch 		return 0;
    295      1.1  mhitch 
    296      1.1  mhitch 	if (sc->sc_state == NCR_CONNECTED)
    297      1.1  mhitch 		csc->sc_reg[0x40] = CBIISC_PB_LED;
    298      1.1  mhitch 	else
    299      1.1  mhitch 		csc->sc_reg[0x40] = 0;
    300      1.1  mhitch 
    301      1.1  mhitch #ifdef DEBUG
    302      1.1  mhitch if (/*sc->sc_nexus && sc->sc_nexus->xs->flags & SCSI_POLL &&*/ cbiisc_trace_enable) {
    303      1.1  mhitch   cbiisc_trace[cbiisc_trace_ptr].status = csc->sc_reg[NCR_STAT * 4];
    304      1.1  mhitch   cbiisc_trace[cbiisc_trace_ptr].xx = csc->sc_reg[NCR_CMD * 4];
    305      1.1  mhitch   cbiisc_trace[cbiisc_trace_ptr].yy = csc->sc_active;
    306      1.1  mhitch   cbiisc_trace_ptr = (cbiisc_trace_ptr + 1) & 127;
    307      1.1  mhitch }
    308      1.1  mhitch #endif
    309      1.1  mhitch 	return 1;
    310      1.1  mhitch }
    311      1.1  mhitch 
    312      1.1  mhitch void
    313      1.1  mhitch cbiisc_dma_reset(sc)
    314      1.1  mhitch 	struct ncr53c9x_softc *sc;
    315      1.1  mhitch {
    316      1.1  mhitch 	struct cbiisc_softc *csc = (struct cbiisc_softc *)sc;
    317      1.1  mhitch 
    318      1.1  mhitch 	csc->sc_active = 0;
    319      1.1  mhitch }
    320      1.1  mhitch 
    321      1.1  mhitch int
    322      1.1  mhitch cbiisc_dma_intr(sc)
    323      1.1  mhitch 	struct ncr53c9x_softc *sc;
    324      1.1  mhitch {
    325      1.1  mhitch 	register struct cbiisc_softc *csc = (struct cbiisc_softc *)sc;
    326      1.1  mhitch 	register int	cnt;
    327      1.1  mhitch 
    328      1.1  mhitch 	NCR_DMA(("cbiisc_dma_intr: cnt %d int %x stat %x fifo %d ",
    329      1.1  mhitch 	    csc->sc_dmasize, sc->sc_espintr, sc->sc_espstat,
    330      1.1  mhitch 	    csc->sc_reg[NCR_FFLAG * 4] & NCRFIFO_FF));
    331      1.1  mhitch 	if (csc->sc_active == 0) {
    332      1.1  mhitch 		printf("cbiisc_intr--inactive DMA\n");
    333      1.1  mhitch 		return -1;
    334      1.1  mhitch 	}
    335      1.1  mhitch 
    336      1.1  mhitch 	/* update sc_dmaaddr and sc_pdmalen */
    337      1.1  mhitch 	cnt = csc->sc_reg[NCR_TCL * 4];
    338      1.1  mhitch 	cnt += csc->sc_reg[NCR_TCM * 4] << 8;
    339      1.1  mhitch 	cnt += csc->sc_reg[NCR_TCH * 4] << 16;
    340      1.1  mhitch 	if (!csc->sc_datain) {
    341      1.1  mhitch 		cnt += csc->sc_reg[NCR_FFLAG * 4] & NCRFIFO_FF;
    342      1.1  mhitch 		csc->sc_reg[NCR_CMD * 4] = NCRCMD_FLUSH;
    343      1.1  mhitch 	}
    344      1.1  mhitch 	cnt = csc->sc_dmasize - cnt;	/* number of bytes transferred */
    345      1.1  mhitch 	NCR_DMA(("DMA xferred %d\n", cnt));
    346      1.1  mhitch 	if (csc->sc_xfr_align) {
    347      1.1  mhitch 		bcopy(csc->sc_alignbuf, *csc->sc_dmaaddr, cnt);
    348      1.1  mhitch 		csc->sc_xfr_align = 0;
    349      1.1  mhitch 	}
    350      1.1  mhitch 	*csc->sc_dmaaddr += cnt;
    351      1.1  mhitch 	*csc->sc_pdmalen -= cnt;
    352      1.1  mhitch 	csc->sc_active = 0;
    353      1.1  mhitch 	return 0;
    354      1.1  mhitch }
    355      1.1  mhitch 
    356      1.1  mhitch int
    357      1.1  mhitch cbiisc_dma_setup(sc, addr, len, datain, dmasize)
    358      1.1  mhitch 	struct ncr53c9x_softc *sc;
    359      1.1  mhitch 	caddr_t *addr;
    360      1.1  mhitch 	size_t *len;
    361      1.1  mhitch 	int datain;
    362      1.1  mhitch 	size_t *dmasize;
    363      1.1  mhitch {
    364      1.1  mhitch 	struct cbiisc_softc *csc = (struct cbiisc_softc *)sc;
    365      1.1  mhitch 	vm_offset_t pa;
    366      1.1  mhitch 	u_char *ptr;
    367      1.1  mhitch 	size_t xfer;
    368      1.1  mhitch 
    369      1.1  mhitch 	csc->sc_dmaaddr = addr;
    370      1.1  mhitch 	csc->sc_pdmalen = len;
    371      1.1  mhitch 	csc->sc_datain = datain;
    372      1.1  mhitch 	csc->sc_dmasize = *dmasize;
    373      1.1  mhitch 	/*
    374      1.1  mhitch 	 * DMA can be nasty for high-speed serial input, so limit the
    375      1.1  mhitch 	 * size of this DMA operation if the serial port is running at
    376      1.1  mhitch 	 * a high speed (higher than 19200 for now - should be adjusted
    377      1.1  mhitch 	 * based on cpu type and speed?).
    378      1.1  mhitch 	 * XXX - add serial speed check XXX
    379      1.1  mhitch 	 */
    380      1.1  mhitch 	if (ser_open_speed > 19200 && cbiisc_max_dma != 0 &&
    381      1.1  mhitch 	    csc->sc_dmasize > cbiisc_max_dma)
    382      1.1  mhitch 		csc->sc_dmasize = cbiisc_max_dma;
    383      1.1  mhitch 	ptr = *addr;			/* Kernel virtual address */
    384      1.1  mhitch 	pa = kvtop(ptr);		/* Physical address of DMA */
    385      1.1  mhitch 	xfer = min(csc->sc_dmasize, NBPG - (pa & (NBPG - 1)));
    386      1.1  mhitch 	csc->sc_xfr_align = 0;
    387      1.1  mhitch 	/*
    388      1.1  mhitch 	 * If output and unaligned, stuff odd byte into FIFO
    389      1.1  mhitch 	 */
    390      1.1  mhitch 	if (datain == 0 && (int)ptr & 1) {
    391      1.1  mhitch 		NCR_DMA(("cbiisc_dma_setup: align byte written to fifo\n"));
    392      1.1  mhitch 		pa++;
    393      1.1  mhitch 		xfer--;			/* XXXX CHECK THIS !!!! XXXX */
    394      1.1  mhitch 		csc->sc_reg[NCR_FIFO * 4] = *ptr++;
    395      1.1  mhitch 	}
    396      1.1  mhitch 	/*
    397      1.1  mhitch 	 * If unaligned address, read unaligned bytes into alignment buffer
    398      1.1  mhitch 	 */
    399      1.1  mhitch 	else if ((int)ptr & 1) {
    400      1.1  mhitch 		pa = kvtop((caddr_t)&csc->sc_alignbuf);
    401      1.1  mhitch 		xfer = csc->sc_dmasize = min(xfer, sizeof (csc->sc_alignbuf));
    402      1.1  mhitch 		NCR_DMA(("cbiisc_dma_setup: align read by %d bytes\n", xfer));
    403      1.1  mhitch 		csc->sc_xfr_align = 1;
    404      1.1  mhitch 	}
    405      1.1  mhitch ++cbiisc_cnt_dma;		/* number of DMA operations */
    406      1.1  mhitch 
    407      1.1  mhitch 	while (xfer < csc->sc_dmasize) {
    408      1.1  mhitch 		if ((pa + xfer) != kvtop(*addr + xfer))
    409      1.1  mhitch 			break;
    410      1.1  mhitch 		if ((csc->sc_dmasize - xfer) < NBPG)
    411      1.1  mhitch 			xfer = csc->sc_dmasize;
    412      1.1  mhitch 		else
    413      1.1  mhitch 			xfer += NBPG;
    414      1.1  mhitch ++cbiisc_cnt_dma3;
    415      1.1  mhitch 	}
    416      1.1  mhitch if (xfer != *len)
    417      1.1  mhitch   ++cbiisc_cnt_dma2;
    418      1.1  mhitch 
    419      1.1  mhitch 	csc->sc_dmasize = xfer;
    420      1.1  mhitch 	*dmasize = csc->sc_dmasize;
    421      1.1  mhitch 	csc->sc_pa = pa;
    422      1.1  mhitch #if defined(M68040) || defined(M68060)
    423      1.1  mhitch 	if (mmutype == MMU_68040) {
    424      1.1  mhitch 		if (csc->sc_xfr_align) {
    425      1.1  mhitch 			dma_cachectl(csc->sc_alignbuf,
    426      1.1  mhitch 			    sizeof(csc->sc_alignbuf));
    427      1.1  mhitch 		}
    428      1.1  mhitch 		else
    429      1.1  mhitch 			dma_cachectl(*csc->sc_dmaaddr, csc->sc_dmasize);
    430      1.1  mhitch 	}
    431      1.1  mhitch #endif
    432      1.1  mhitch 
    433      1.1  mhitch 	if (csc->sc_datain)
    434      1.1  mhitch 		pa &= ~1;
    435      1.1  mhitch 	else
    436      1.1  mhitch 		pa |= 1;
    437      1.1  mhitch 	csc->sc_dmabase[0] = (u_int8_t)(pa >> 24);
    438      1.1  mhitch 	csc->sc_dmabase[4] = (u_int8_t)(pa >> 16);
    439      1.1  mhitch 	csc->sc_dmabase[8] = (u_int8_t)(pa >> 8);
    440      1.1  mhitch 	csc->sc_dmabase[12] = (u_int8_t)(pa);
    441      1.1  mhitch 	csc->sc_active = 1;
    442      1.1  mhitch 	return 0;
    443      1.1  mhitch }
    444      1.1  mhitch 
    445      1.1  mhitch void
    446      1.1  mhitch cbiisc_dma_go(sc)
    447      1.1  mhitch 	struct ncr53c9x_softc *sc;
    448      1.1  mhitch {
    449      1.1  mhitch }
    450      1.1  mhitch 
    451      1.1  mhitch void
    452      1.1  mhitch cbiisc_dma_stop(sc)
    453      1.1  mhitch 	struct ncr53c9x_softc *sc;
    454      1.1  mhitch {
    455      1.1  mhitch }
    456      1.1  mhitch 
    457      1.1  mhitch int
    458      1.1  mhitch cbiisc_dma_isactive(sc)
    459      1.1  mhitch 	struct ncr53c9x_softc *sc;
    460      1.1  mhitch {
    461      1.1  mhitch 	struct cbiisc_softc *csc = (struct cbiisc_softc *)sc;
    462      1.1  mhitch 
    463      1.1  mhitch 	return csc->sc_active;
    464      1.1  mhitch }
    465      1.1  mhitch 
    466      1.1  mhitch #ifdef DEBUG
    467      1.1  mhitch void
    468      1.1  mhitch cbiisc_dump()
    469      1.1  mhitch {
    470      1.1  mhitch 	int i;
    471      1.1  mhitch 
    472      1.1  mhitch 	i = cbiisc_trace_ptr;
    473      1.1  mhitch 	printf("cbiisc_trace dump: ptr %x\n", cbiisc_trace_ptr);
    474      1.1  mhitch 	do {
    475      1.1  mhitch 		if (cbiisc_trace[i].hardbits == 0) {
    476      1.1  mhitch 			i = (i + 1) & 127;
    477      1.1  mhitch 			continue;
    478      1.1  mhitch 		}
    479      1.1  mhitch 		printf("%02x%02x%02x%02x(", cbiisc_trace[i].hardbits,
    480      1.1  mhitch 		    cbiisc_trace[i].status, cbiisc_trace[i].xx, cbiisc_trace[i].yy);
    481      1.1  mhitch 		if (cbiisc_trace[i].status & NCRSTAT_INT)
    482      1.1  mhitch 			printf("NCRINT/");
    483      1.1  mhitch 		if (cbiisc_trace[i].status & NCRSTAT_TC)
    484      1.1  mhitch 			printf("NCRTC/");
    485      1.1  mhitch 		switch(cbiisc_trace[i].status & NCRSTAT_PHASE) {
    486      1.1  mhitch 		case 0:
    487      1.1  mhitch 			printf("dataout"); break;
    488      1.1  mhitch 		case 1:
    489      1.1  mhitch 			printf("datain"); break;
    490      1.1  mhitch 		case 2:
    491      1.1  mhitch 			printf("cmdout"); break;
    492      1.1  mhitch 		case 3:
    493      1.1  mhitch 			printf("status"); break;
    494      1.1  mhitch 		case 6:
    495      1.1  mhitch 			printf("msgout"); break;
    496      1.1  mhitch 		case 7:
    497      1.1  mhitch 			printf("msgin"); break;
    498      1.1  mhitch 		default:
    499      1.1  mhitch 			printf("phase%d?", cbiisc_trace[i].status & NCRSTAT_PHASE);
    500      1.1  mhitch 		}
    501      1.1  mhitch 		printf(") ");
    502      1.1  mhitch 		i = (i + 1) & 127;
    503      1.1  mhitch 	} while (i != cbiisc_trace_ptr);
    504      1.1  mhitch 	printf("\n");
    505      1.1  mhitch }
    506      1.1  mhitch #endif
    507