cbiisc.c revision 1.27 1 1.27 tsutsui /* $NetBSD: cbiisc.c,v 1.27 2008/04/13 04:55:52 tsutsui Exp $ */
2 1.1 mhitch
3 1.1 mhitch /*
4 1.1 mhitch * Copyright (c) 1997 Michael L. Hitch
5 1.1 mhitch * Copyright (c) 1982, 1990 The Regents of the University of California.
6 1.1 mhitch * All rights reserved.
7 1.1 mhitch *
8 1.1 mhitch * Redistribution and use in source and binary forms, with or without
9 1.1 mhitch * modification, are permitted provided that the following conditions
10 1.1 mhitch * are met:
11 1.1 mhitch * 1. Redistributions of source code must retain the above copyright
12 1.1 mhitch * notice, this list of conditions and the following disclaimer.
13 1.1 mhitch * 2. Redistributions in binary form must reproduce the above copyright
14 1.1 mhitch * notice, this list of conditions and the following disclaimer in the
15 1.1 mhitch * documentation and/or other materials provided with the distribution.
16 1.1 mhitch * 3. All advertising materials mentioning features or use of this software
17 1.1 mhitch * must display the following acknowledgement:
18 1.1 mhitch * This product contains software written by Michael L. Hitch for
19 1.1 mhitch * the NetBSD project.
20 1.1 mhitch * 4. Neither the name of the University nor the names of its contributors
21 1.1 mhitch * may be used to endorse or promote products derived from this software
22 1.1 mhitch * without specific prior written permission.
23 1.1 mhitch *
24 1.1 mhitch * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
25 1.1 mhitch * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
26 1.1 mhitch * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
27 1.1 mhitch * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
28 1.1 mhitch * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
29 1.1 mhitch * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
30 1.1 mhitch * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
31 1.1 mhitch * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
32 1.1 mhitch * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
33 1.1 mhitch * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
34 1.1 mhitch * SUCH DAMAGE.
35 1.1 mhitch *
36 1.1 mhitch */
37 1.13 aymeric
38 1.13 aymeric #include <sys/cdefs.h>
39 1.27 tsutsui __KERNEL_RCSID(0, "$NetBSD: cbiisc.c,v 1.27 2008/04/13 04:55:52 tsutsui Exp $");
40 1.1 mhitch
41 1.1 mhitch #include <sys/types.h>
42 1.1 mhitch #include <sys/param.h>
43 1.1 mhitch #include <sys/systm.h>
44 1.1 mhitch #include <sys/kernel.h>
45 1.1 mhitch #include <sys/errno.h>
46 1.1 mhitch #include <sys/ioctl.h>
47 1.1 mhitch #include <sys/device.h>
48 1.1 mhitch #include <sys/buf.h>
49 1.1 mhitch #include <sys/proc.h>
50 1.1 mhitch #include <sys/user.h>
51 1.1 mhitch #include <sys/queue.h>
52 1.1 mhitch
53 1.16 thorpej #include <uvm/uvm_extern.h>
54 1.16 thorpej
55 1.1 mhitch #include <dev/scsipi/scsi_all.h>
56 1.1 mhitch #include <dev/scsipi/scsipi_all.h>
57 1.1 mhitch #include <dev/scsipi/scsiconf.h>
58 1.1 mhitch #include <dev/scsipi/scsi_message.h>
59 1.1 mhitch
60 1.1 mhitch #include <machine/cpu.h>
61 1.1 mhitch #include <machine/param.h>
62 1.1 mhitch
63 1.1 mhitch #include <dev/ic/ncr53c9xreg.h>
64 1.1 mhitch #include <dev/ic/ncr53c9xvar.h>
65 1.1 mhitch
66 1.1 mhitch #include <amiga/amiga/isr.h>
67 1.1 mhitch #include <amiga/dev/cbiiscvar.h>
68 1.1 mhitch #include <amiga/dev/zbusvar.h>
69 1.1 mhitch
70 1.25 is #ifdef __powerpc__
71 1.25 is #define badaddr(a) badaddr_read(a, 2, NULL)
72 1.25 is #endif
73 1.25 is
74 1.27 tsutsui int cbiiscmatch(device_t, cfdata_t, void *);
75 1.27 tsutsui void cbiiscattach(device_t, device_t, void *);
76 1.1 mhitch
77 1.1 mhitch /* Linkup to the rest of the kernel */
78 1.27 tsutsui CFATTACH_DECL_NEW(cbiisc, sizeof(struct cbiisc_softc),
79 1.15 thorpej cbiiscmatch, cbiiscattach, NULL, NULL);
80 1.1 mhitch
81 1.1 mhitch /*
82 1.1 mhitch * Functions and the switch for the MI code.
83 1.1 mhitch */
84 1.27 tsutsui uint8_t cbiisc_read_reg(struct ncr53c9x_softc *, int);
85 1.27 tsutsui void cbiisc_write_reg(struct ncr53c9x_softc *, int, uint8_t);
86 1.12 aymeric int cbiisc_dma_isintr(struct ncr53c9x_softc *);
87 1.12 aymeric void cbiisc_dma_reset(struct ncr53c9x_softc *);
88 1.12 aymeric int cbiisc_dma_intr(struct ncr53c9x_softc *);
89 1.27 tsutsui int cbiisc_dma_setup(struct ncr53c9x_softc *, uint8_t **,
90 1.12 aymeric size_t *, int, size_t *);
91 1.12 aymeric void cbiisc_dma_go(struct ncr53c9x_softc *);
92 1.12 aymeric void cbiisc_dma_stop(struct ncr53c9x_softc *);
93 1.12 aymeric int cbiisc_dma_isactive(struct ncr53c9x_softc *);
94 1.1 mhitch
95 1.1 mhitch struct ncr53c9x_glue cbiisc_glue = {
96 1.1 mhitch cbiisc_read_reg,
97 1.1 mhitch cbiisc_write_reg,
98 1.1 mhitch cbiisc_dma_isintr,
99 1.1 mhitch cbiisc_dma_reset,
100 1.1 mhitch cbiisc_dma_intr,
101 1.1 mhitch cbiisc_dma_setup,
102 1.1 mhitch cbiisc_dma_go,
103 1.1 mhitch cbiisc_dma_stop,
104 1.1 mhitch cbiisc_dma_isactive,
105 1.27 tsutsui NULL,
106 1.1 mhitch };
107 1.1 mhitch
108 1.1 mhitch /* Maximum DMA transfer length to reduce impact on high-speed serial input */
109 1.1 mhitch u_long cbiisc_max_dma = 1024;
110 1.1 mhitch extern int ser_open_speed;
111 1.1 mhitch
112 1.1 mhitch u_long cbiisc_cnt_pio = 0; /* number of PIO transfers */
113 1.1 mhitch u_long cbiisc_cnt_dma = 0; /* number of DMA transfers */
114 1.1 mhitch u_long cbiisc_cnt_dma2 = 0; /* number of DMA transfers broken up */
115 1.1 mhitch u_long cbiisc_cnt_dma3 = 0; /* number of pages combined */
116 1.1 mhitch
117 1.1 mhitch #ifdef DEBUG
118 1.1 mhitch struct {
119 1.27 tsutsui uint8_t hardbits;
120 1.27 tsutsui uint8_t status;
121 1.27 tsutsui uint8_t xx;
122 1.27 tsutsui uint8_t yy;
123 1.1 mhitch } cbiisc_trace[128];
124 1.1 mhitch int cbiisc_trace_ptr = 0;
125 1.1 mhitch int cbiisc_trace_enable = 1;
126 1.12 aymeric void cbiisc_dump(void);
127 1.1 mhitch #endif
128 1.1 mhitch
129 1.1 mhitch /*
130 1.1 mhitch * if we are a Phase5 CyberSCSI II
131 1.1 mhitch */
132 1.1 mhitch int
133 1.27 tsutsui cbiiscmatch(device_t parent, cfdata_t cf, void *aux)
134 1.1 mhitch {
135 1.1 mhitch struct zbus_args *zap;
136 1.27 tsutsui volatile uint8_t *regs;
137 1.1 mhitch
138 1.1 mhitch zap = aux;
139 1.2 mhitch if (zap->manid != 0x2140 || zap->prodid != 25)
140 1.27 tsutsui return 0;
141 1.27 tsutsui regs = &((volatile uint8_t *)zap->va)[0x1ff03];
142 1.22 christos if (badaddr((void *)__UNVOLATILE(regs)))
143 1.27 tsutsui return 0;
144 1.1 mhitch regs[NCR_CFG1 * 4] = 0;
145 1.1 mhitch regs[NCR_CFG1 * 4] = NCRCFG1_PARENB | 7;
146 1.1 mhitch delay(5);
147 1.1 mhitch if (regs[NCR_CFG1 * 4] != (NCRCFG1_PARENB | 7))
148 1.27 tsutsui return 0;
149 1.27 tsutsui return 1;
150 1.1 mhitch }
151 1.1 mhitch
152 1.1 mhitch /*
153 1.1 mhitch * Attach this instance, and then all the sub-devices
154 1.1 mhitch */
155 1.1 mhitch void
156 1.27 tsutsui cbiiscattach(device_t parent, device_t self, void *aux)
157 1.1 mhitch {
158 1.27 tsutsui struct cbiisc_softc *csc = device_private(self);
159 1.1 mhitch struct ncr53c9x_softc *sc = &csc->sc_ncr53c9x;
160 1.1 mhitch struct zbus_args *zap;
161 1.1 mhitch extern u_long scsi_nosync;
162 1.1 mhitch extern int shift_nosync;
163 1.1 mhitch extern int ncr53c9x_debug;
164 1.1 mhitch
165 1.1 mhitch /*
166 1.1 mhitch * Set up the glue for MI code early; we use some of it here.
167 1.1 mhitch */
168 1.27 tsutsui sc->sc_dev = self;
169 1.1 mhitch sc->sc_glue = &cbiisc_glue;
170 1.1 mhitch
171 1.1 mhitch /*
172 1.1 mhitch * Save the regs
173 1.1 mhitch */
174 1.1 mhitch zap = aux;
175 1.27 tsutsui csc->sc_reg = &((volatile uint8_t *)zap->va)[0x1ff03];
176 1.1 mhitch csc->sc_dmabase = &csc->sc_reg[0x80];
177 1.1 mhitch
178 1.20 lukem sc->sc_freq = 40; /* Clocked at 40 MHz */
179 1.1 mhitch
180 1.27 tsutsui aprint_normal(": address %p", csc->sc_reg);
181 1.1 mhitch
182 1.1 mhitch sc->sc_id = 7;
183 1.1 mhitch
184 1.1 mhitch /*
185 1.1 mhitch * It is necessary to try to load the 2nd config register here,
186 1.1 mhitch * to find out what rev the FAS chip is, else the ncr53c9x_reset
187 1.1 mhitch * will not set up the defaults correctly.
188 1.1 mhitch */
189 1.1 mhitch sc->sc_cfg1 = sc->sc_id | NCRCFG1_PARENB;
190 1.1 mhitch sc->sc_cfg2 = NCRCFG2_SCSI2 | NCRCFG2_FE;
191 1.1 mhitch sc->sc_cfg3 = 0x08 /*FCLK*/ | NCRESPCFG3_FSCSI | NCRESPCFG3_CDB;
192 1.1 mhitch sc->sc_rev = NCR_VARIANT_FAS216;
193 1.1 mhitch
194 1.1 mhitch /*
195 1.1 mhitch * This is the value used to start sync negotiations
196 1.1 mhitch * Note that the NCR register "SYNCTP" is programmed
197 1.1 mhitch * in "clocks per byte", and has a minimum value of 4.
198 1.1 mhitch * The SCSI period used in negotiation is one-fourth
199 1.1 mhitch * of the time (in nanoseconds) needed to transfer one byte.
200 1.1 mhitch * Since the chip's clock is given in MHz, we have the following
201 1.1 mhitch * formula: 4 * period = (1000 / freq) * 4
202 1.1 mhitch */
203 1.1 mhitch sc->sc_minsync = 1000 / sc->sc_freq;
204 1.1 mhitch
205 1.1 mhitch /*
206 1.1 mhitch * get flags from -I argument and set cf_flags.
207 1.1 mhitch * NOTE: low 8 bits are to disable disconnect, and the next
208 1.1 mhitch * 8 bits are to disable sync.
209 1.1 mhitch */
210 1.27 tsutsui device_cfdata(self)->cf_flags |= (scsi_nosync >> shift_nosync)
211 1.1 mhitch & 0xffff;
212 1.1 mhitch shift_nosync += 16;
213 1.1 mhitch
214 1.1 mhitch /* Use next 16 bits of -I argument to set ncr53c9x_debug flags */
215 1.1 mhitch ncr53c9x_debug |= (scsi_nosync >> shift_nosync) & 0xffff;
216 1.1 mhitch shift_nosync += 16;
217 1.1 mhitch
218 1.1 mhitch #if 1
219 1.1 mhitch if (((scsi_nosync >> shift_nosync) & 0xff00) == 0xff00)
220 1.1 mhitch sc->sc_minsync = 0;
221 1.1 mhitch #endif
222 1.1 mhitch
223 1.1 mhitch /* Really no limit, but since we want to fit into the TCR... */
224 1.1 mhitch sc->sc_maxxfer = 64 * 1024;
225 1.1 mhitch
226 1.1 mhitch /*
227 1.1 mhitch * Configure interrupts.
228 1.1 mhitch */
229 1.10 tsutsui csc->sc_isr.isr_intr = ncr53c9x_intr;
230 1.1 mhitch csc->sc_isr.isr_arg = sc;
231 1.1 mhitch csc->sc_isr.isr_ipl = 2;
232 1.1 mhitch add_isr(&csc->sc_isr);
233 1.1 mhitch
234 1.1 mhitch /*
235 1.1 mhitch * Now try to attach all the sub-devices
236 1.1 mhitch */
237 1.11 bouyer sc->sc_adapter.adapt_request = ncr53c9x_scsipi_request;
238 1.11 bouyer sc->sc_adapter.adapt_minphys = minphys;
239 1.11 bouyer ncr53c9x_attach(sc);
240 1.1 mhitch }
241 1.1 mhitch
242 1.1 mhitch /*
243 1.1 mhitch * Glue functions.
244 1.1 mhitch */
245 1.1 mhitch
246 1.27 tsutsui uint8_t
247 1.12 aymeric cbiisc_read_reg(struct ncr53c9x_softc *sc, int reg)
248 1.1 mhitch {
249 1.1 mhitch struct cbiisc_softc *csc = (struct cbiisc_softc *)sc;
250 1.1 mhitch
251 1.1 mhitch return csc->sc_reg[reg * 4];
252 1.1 mhitch }
253 1.1 mhitch
254 1.1 mhitch void
255 1.27 tsutsui cbiisc_write_reg(struct ncr53c9x_softc *sc, int reg, uint8_t val)
256 1.1 mhitch {
257 1.1 mhitch struct cbiisc_softc *csc = (struct cbiisc_softc *)sc;
258 1.27 tsutsui uint8_t v = val;
259 1.1 mhitch
260 1.1 mhitch csc->sc_reg[reg * 4] = v;
261 1.1 mhitch #ifdef DEBUG
262 1.9 thorpej if (cbiisc_trace_enable/* && sc->sc_nexus && sc->sc_nexus->xs->xs_control & XS_CTL_POLL*/ &&
263 1.1 mhitch reg == NCR_CMD/* && csc->sc_active*/) {
264 1.1 mhitch cbiisc_trace[(cbiisc_trace_ptr - 1) & 127].yy = v;
265 1.1 mhitch /* printf(" cmd %x", v);*/
266 1.1 mhitch }
267 1.1 mhitch #endif
268 1.1 mhitch }
269 1.1 mhitch
270 1.1 mhitch int
271 1.12 aymeric cbiisc_dma_isintr(struct ncr53c9x_softc *sc)
272 1.1 mhitch {
273 1.1 mhitch struct cbiisc_softc *csc = (struct cbiisc_softc *)sc;
274 1.1 mhitch
275 1.1 mhitch if ((csc->sc_reg[NCR_STAT * 4] & NCRSTAT_INT) == 0)
276 1.1 mhitch return 0;
277 1.1 mhitch
278 1.1 mhitch if (sc->sc_state == NCR_CONNECTED)
279 1.1 mhitch csc->sc_reg[0x40] = CBIISC_PB_LED;
280 1.1 mhitch else
281 1.1 mhitch csc->sc_reg[0x40] = 0;
282 1.1 mhitch
283 1.1 mhitch #ifdef DEBUG
284 1.9 thorpej if (/*sc->sc_nexus && sc->sc_nexus->xs->xs_control & XS_CTL_POLL &&*/ cbiisc_trace_enable) {
285 1.1 mhitch cbiisc_trace[cbiisc_trace_ptr].status = csc->sc_reg[NCR_STAT * 4];
286 1.1 mhitch cbiisc_trace[cbiisc_trace_ptr].xx = csc->sc_reg[NCR_CMD * 4];
287 1.1 mhitch cbiisc_trace[cbiisc_trace_ptr].yy = csc->sc_active;
288 1.1 mhitch cbiisc_trace_ptr = (cbiisc_trace_ptr + 1) & 127;
289 1.1 mhitch }
290 1.1 mhitch #endif
291 1.1 mhitch return 1;
292 1.1 mhitch }
293 1.1 mhitch
294 1.1 mhitch void
295 1.12 aymeric cbiisc_dma_reset(struct ncr53c9x_softc *sc)
296 1.1 mhitch {
297 1.1 mhitch struct cbiisc_softc *csc = (struct cbiisc_softc *)sc;
298 1.1 mhitch
299 1.1 mhitch csc->sc_active = 0;
300 1.1 mhitch }
301 1.1 mhitch
302 1.1 mhitch int
303 1.12 aymeric cbiisc_dma_intr(struct ncr53c9x_softc *sc)
304 1.1 mhitch {
305 1.1 mhitch register struct cbiisc_softc *csc = (struct cbiisc_softc *)sc;
306 1.1 mhitch register int cnt;
307 1.1 mhitch
308 1.1 mhitch NCR_DMA(("cbiisc_dma_intr: cnt %d int %x stat %x fifo %d ",
309 1.1 mhitch csc->sc_dmasize, sc->sc_espintr, sc->sc_espstat,
310 1.1 mhitch csc->sc_reg[NCR_FFLAG * 4] & NCRFIFO_FF));
311 1.1 mhitch if (csc->sc_active == 0) {
312 1.1 mhitch printf("cbiisc_intr--inactive DMA\n");
313 1.1 mhitch return -1;
314 1.1 mhitch }
315 1.1 mhitch
316 1.1 mhitch /* update sc_dmaaddr and sc_pdmalen */
317 1.1 mhitch cnt = csc->sc_reg[NCR_TCL * 4];
318 1.1 mhitch cnt += csc->sc_reg[NCR_TCM * 4] << 8;
319 1.1 mhitch cnt += csc->sc_reg[NCR_TCH * 4] << 16;
320 1.1 mhitch if (!csc->sc_datain) {
321 1.1 mhitch cnt += csc->sc_reg[NCR_FFLAG * 4] & NCRFIFO_FF;
322 1.1 mhitch csc->sc_reg[NCR_CMD * 4] = NCRCMD_FLUSH;
323 1.1 mhitch }
324 1.1 mhitch cnt = csc->sc_dmasize - cnt; /* number of bytes transferred */
325 1.1 mhitch NCR_DMA(("DMA xferred %d\n", cnt));
326 1.1 mhitch if (csc->sc_xfr_align) {
327 1.27 tsutsui memcpy(*csc->sc_dmaaddr, csc->sc_alignbuf, cnt);
328 1.1 mhitch csc->sc_xfr_align = 0;
329 1.1 mhitch }
330 1.1 mhitch *csc->sc_dmaaddr += cnt;
331 1.1 mhitch *csc->sc_pdmalen -= cnt;
332 1.1 mhitch csc->sc_active = 0;
333 1.1 mhitch return 0;
334 1.1 mhitch }
335 1.1 mhitch
336 1.1 mhitch int
337 1.27 tsutsui cbiisc_dma_setup(struct ncr53c9x_softc *sc, uint8_t **addr, size_t *len,
338 1.12 aymeric int datain, size_t *dmasize)
339 1.1 mhitch {
340 1.1 mhitch struct cbiisc_softc *csc = (struct cbiisc_softc *)sc;
341 1.8 is paddr_t pa;
342 1.27 tsutsui uint8_t *ptr;
343 1.1 mhitch size_t xfer;
344 1.1 mhitch
345 1.27 tsutsui csc->sc_dmaaddr = addr;
346 1.1 mhitch csc->sc_pdmalen = len;
347 1.1 mhitch csc->sc_datain = datain;
348 1.1 mhitch csc->sc_dmasize = *dmasize;
349 1.1 mhitch /*
350 1.1 mhitch * DMA can be nasty for high-speed serial input, so limit the
351 1.1 mhitch * size of this DMA operation if the serial port is running at
352 1.1 mhitch * a high speed (higher than 19200 for now - should be adjusted
353 1.17 wiz * based on CPU type and speed?).
354 1.1 mhitch * XXX - add serial speed check XXX
355 1.1 mhitch */
356 1.1 mhitch if (ser_open_speed > 19200 && cbiisc_max_dma != 0 &&
357 1.1 mhitch csc->sc_dmasize > cbiisc_max_dma)
358 1.1 mhitch csc->sc_dmasize = cbiisc_max_dma;
359 1.1 mhitch ptr = *addr; /* Kernel virtual address */
360 1.1 mhitch pa = kvtop(ptr); /* Physical address of DMA */
361 1.16 thorpej xfer = min(csc->sc_dmasize, PAGE_SIZE - (pa & (PAGE_SIZE - 1)));
362 1.1 mhitch csc->sc_xfr_align = 0;
363 1.1 mhitch /*
364 1.1 mhitch * If output and unaligned, stuff odd byte into FIFO
365 1.1 mhitch */
366 1.1 mhitch if (datain == 0 && (int)ptr & 1) {
367 1.1 mhitch NCR_DMA(("cbiisc_dma_setup: align byte written to fifo\n"));
368 1.1 mhitch pa++;
369 1.1 mhitch xfer--; /* XXXX CHECK THIS !!!! XXXX */
370 1.1 mhitch csc->sc_reg[NCR_FIFO * 4] = *ptr++;
371 1.1 mhitch }
372 1.1 mhitch /*
373 1.1 mhitch * If unaligned address, read unaligned bytes into alignment buffer
374 1.1 mhitch */
375 1.1 mhitch else if ((int)ptr & 1) {
376 1.22 christos pa = kvtop((void *)&csc->sc_alignbuf);
377 1.27 tsutsui xfer = csc->sc_dmasize = min(xfer, sizeof(csc->sc_alignbuf));
378 1.1 mhitch NCR_DMA(("cbiisc_dma_setup: align read by %d bytes\n", xfer));
379 1.1 mhitch csc->sc_xfr_align = 1;
380 1.1 mhitch }
381 1.1 mhitch ++cbiisc_cnt_dma; /* number of DMA operations */
382 1.1 mhitch
383 1.1 mhitch while (xfer < csc->sc_dmasize) {
384 1.27 tsutsui if ((pa + xfer) != kvtop(*addr + xfer))
385 1.1 mhitch break;
386 1.16 thorpej if ((csc->sc_dmasize - xfer) < PAGE_SIZE)
387 1.1 mhitch xfer = csc->sc_dmasize;
388 1.1 mhitch else
389 1.16 thorpej xfer += PAGE_SIZE;
390 1.1 mhitch ++cbiisc_cnt_dma3;
391 1.1 mhitch }
392 1.1 mhitch if (xfer != *len)
393 1.1 mhitch ++cbiisc_cnt_dma2;
394 1.1 mhitch
395 1.1 mhitch csc->sc_dmasize = xfer;
396 1.1 mhitch *dmasize = csc->sc_dmasize;
397 1.1 mhitch csc->sc_pa = pa;
398 1.1 mhitch #if defined(M68040) || defined(M68060)
399 1.1 mhitch if (mmutype == MMU_68040) {
400 1.1 mhitch if (csc->sc_xfr_align) {
401 1.1 mhitch dma_cachectl(csc->sc_alignbuf,
402 1.1 mhitch sizeof(csc->sc_alignbuf));
403 1.1 mhitch }
404 1.1 mhitch else
405 1.1 mhitch dma_cachectl(*csc->sc_dmaaddr, csc->sc_dmasize);
406 1.1 mhitch }
407 1.1 mhitch #endif
408 1.1 mhitch
409 1.1 mhitch if (csc->sc_datain)
410 1.1 mhitch pa &= ~1;
411 1.1 mhitch else
412 1.1 mhitch pa |= 1;
413 1.27 tsutsui csc->sc_dmabase[0] = (uint8_t)(pa >> 24);
414 1.27 tsutsui csc->sc_dmabase[4] = (uint8_t)(pa >> 16);
415 1.27 tsutsui csc->sc_dmabase[8] = (uint8_t)(pa >> 8);
416 1.27 tsutsui csc->sc_dmabase[12] = (uint8_t)(pa);
417 1.1 mhitch csc->sc_active = 1;
418 1.1 mhitch return 0;
419 1.1 mhitch }
420 1.1 mhitch
421 1.1 mhitch void
422 1.12 aymeric cbiisc_dma_go(struct ncr53c9x_softc *sc)
423 1.1 mhitch {
424 1.1 mhitch }
425 1.1 mhitch
426 1.1 mhitch void
427 1.12 aymeric cbiisc_dma_stop(struct ncr53c9x_softc *sc)
428 1.1 mhitch {
429 1.1 mhitch }
430 1.1 mhitch
431 1.1 mhitch int
432 1.12 aymeric cbiisc_dma_isactive(struct ncr53c9x_softc *sc)
433 1.1 mhitch {
434 1.1 mhitch struct cbiisc_softc *csc = (struct cbiisc_softc *)sc;
435 1.1 mhitch
436 1.1 mhitch return csc->sc_active;
437 1.1 mhitch }
438 1.1 mhitch
439 1.1 mhitch #ifdef DEBUG
440 1.1 mhitch void
441 1.12 aymeric cbiisc_dump(void)
442 1.1 mhitch {
443 1.1 mhitch int i;
444 1.1 mhitch
445 1.1 mhitch i = cbiisc_trace_ptr;
446 1.1 mhitch printf("cbiisc_trace dump: ptr %x\n", cbiisc_trace_ptr);
447 1.1 mhitch do {
448 1.1 mhitch if (cbiisc_trace[i].hardbits == 0) {
449 1.1 mhitch i = (i + 1) & 127;
450 1.1 mhitch continue;
451 1.1 mhitch }
452 1.1 mhitch printf("%02x%02x%02x%02x(", cbiisc_trace[i].hardbits,
453 1.1 mhitch cbiisc_trace[i].status, cbiisc_trace[i].xx, cbiisc_trace[i].yy);
454 1.1 mhitch if (cbiisc_trace[i].status & NCRSTAT_INT)
455 1.1 mhitch printf("NCRINT/");
456 1.1 mhitch if (cbiisc_trace[i].status & NCRSTAT_TC)
457 1.1 mhitch printf("NCRTC/");
458 1.1 mhitch switch(cbiisc_trace[i].status & NCRSTAT_PHASE) {
459 1.1 mhitch case 0:
460 1.1 mhitch printf("dataout"); break;
461 1.1 mhitch case 1:
462 1.1 mhitch printf("datain"); break;
463 1.1 mhitch case 2:
464 1.1 mhitch printf("cmdout"); break;
465 1.1 mhitch case 3:
466 1.1 mhitch printf("status"); break;
467 1.1 mhitch case 6:
468 1.1 mhitch printf("msgout"); break;
469 1.1 mhitch case 7:
470 1.1 mhitch printf("msgin"); break;
471 1.1 mhitch default:
472 1.1 mhitch printf("phase%d?", cbiisc_trace[i].status & NCRSTAT_PHASE);
473 1.1 mhitch }
474 1.1 mhitch printf(") ");
475 1.1 mhitch i = (i + 1) & 127;
476 1.1 mhitch } while (i != cbiisc_trace_ptr);
477 1.1 mhitch printf("\n");
478 1.1 mhitch }
479 1.1 mhitch #endif
480