cbsc.c revision 1.1.4.2
1 /* $NetBSD: cbsc.c,v 1.1.4.2 1998/11/22 07:25:43 cgd Exp $ */ 2 3 /* 4 * Copyright (c) 1997 Michael L. Hitch 5 * Copyright (c) 1982, 1990 The Regents of the University of California. 6 * All rights reserved. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 3. All advertising materials mentioning features or use of this software 17 * must display the following acknowledgement: 18 * This product contains software written by Michael L. Hitch for 19 * the NetBSD project. 20 * 4. Neither the name of the University nor the names of its contributors 21 * may be used to endorse or promote products derived from this software 22 * without specific prior written permission. 23 * 24 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 25 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 26 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 27 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 28 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 29 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 30 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 31 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 32 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 33 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 34 * SUCH DAMAGE. 35 * 36 */ 37 38 #include <sys/types.h> 39 #include <sys/param.h> 40 #include <sys/systm.h> 41 #include <sys/kernel.h> 42 #include <sys/errno.h> 43 #include <sys/ioctl.h> 44 #include <sys/device.h> 45 #include <sys/buf.h> 46 #include <sys/proc.h> 47 #include <sys/user.h> 48 #include <sys/queue.h> 49 50 #include <dev/scsipi/scsi_all.h> 51 #include <dev/scsipi/scsipi_all.h> 52 #include <dev/scsipi/scsiconf.h> 53 #include <dev/scsipi/scsi_message.h> 54 55 #include <machine/cpu.h> 56 #include <machine/param.h> 57 58 #include <dev/ic/ncr53c9xreg.h> 59 #include <dev/ic/ncr53c9xvar.h> 60 61 #include <amiga/amiga/isr.h> 62 #include <amiga/dev/cbscvar.h> 63 #include <amiga/dev/zbusvar.h> 64 65 void cbscattach __P((struct device *, struct device *, void *)); 66 int cbscmatch __P((struct device *, struct cfdata *, void *)); 67 68 /* Linkup to the rest of the kernel */ 69 struct cfattach cbsc_ca = { 70 sizeof(struct cbsc_softc), cbscmatch, cbscattach 71 }; 72 73 struct cfdriver cbsc_cd = { 74 NULL, "cbsc", DV_DULL 75 }; 76 77 struct scsipi_adapter cbsc_switch = { 78 ncr53c9x_scsi_cmd, 79 minphys, /* no max at this level; handled by DMA code */ 80 NULL, 81 NULL, 82 }; 83 84 struct scsipi_device cbsc_dev = { 85 NULL, /* Use default error handler */ 86 NULL, /* have a queue, served by this */ 87 NULL, /* have no async handler */ 88 NULL, /* Use default 'done' routine */ 89 }; 90 91 /* 92 * Functions and the switch for the MI code. 93 */ 94 u_char cbsc_read_reg __P((struct ncr53c9x_softc *, int)); 95 void cbsc_write_reg __P((struct ncr53c9x_softc *, int, u_char)); 96 int cbsc_dma_isintr __P((struct ncr53c9x_softc *)); 97 void cbsc_dma_reset __P((struct ncr53c9x_softc *)); 98 int cbsc_dma_intr __P((struct ncr53c9x_softc *)); 99 int cbsc_dma_setup __P((struct ncr53c9x_softc *, caddr_t *, 100 size_t *, int, size_t *)); 101 void cbsc_dma_go __P((struct ncr53c9x_softc *)); 102 void cbsc_dma_stop __P((struct ncr53c9x_softc *)); 103 int cbsc_dma_isactive __P((struct ncr53c9x_softc *)); 104 105 struct ncr53c9x_glue cbsc_glue = { 106 cbsc_read_reg, 107 cbsc_write_reg, 108 cbsc_dma_isintr, 109 cbsc_dma_reset, 110 cbsc_dma_intr, 111 cbsc_dma_setup, 112 cbsc_dma_go, 113 cbsc_dma_stop, 114 cbsc_dma_isactive, 115 0, 116 }; 117 118 /* Maximum DMA transfer length to reduce impact on high-speed serial input */ 119 u_long cbsc_max_dma = 1024; 120 extern int ser_open_speed; 121 122 u_long cbsc_cnt_pio = 0; /* number of PIO transfers */ 123 u_long cbsc_cnt_dma = 0; /* number of DMA transfers */ 124 u_long cbsc_cnt_dma2 = 0; /* number of DMA transfers broken up */ 125 u_long cbsc_cnt_dma3 = 0; /* number of pages combined */ 126 127 #ifdef DEBUG 128 struct { 129 u_char hardbits; 130 u_char status; 131 u_char xx; 132 u_char yy; 133 } cbsc_trace[128]; 134 int cbsc_trace_ptr = 0; 135 int cbsc_trace_enable = 1; 136 void cbsc_dump __P((void)); 137 #endif 138 139 /* 140 * if we are a Phase5 CyberSCSI [mark I?] 141 */ 142 int 143 cbscmatch(parent, cf, aux) 144 struct device *parent; 145 struct cfdata *cf; 146 void *aux; 147 { 148 struct zbus_args *zap; 149 volatile u_char *regs; 150 151 zap = aux; 152 if (zap->manid != 0x2140) 153 return(0); /* It's not Phase5 */ 154 if (zap->prodid != 12 && zap->prodid != 11) 155 return(0); /* Not CyberStorm MKI SCSI */ 156 if (zap->prodid == 11 && iszthreepa(zap->pa)) 157 return(0); /* Fastlane Z3! */ 158 regs = &((volatile u_char *)zap->va)[0xf400]; 159 if (badaddr((caddr_t)regs)) 160 return(0); 161 regs[NCR_CFG1 * 4] = 0; 162 regs[NCR_CFG1 * 4] = NCRCFG1_PARENB | 7; 163 delay(5); 164 if (regs[NCR_CFG1 * 4] != (NCRCFG1_PARENB | 7)) 165 return(0); 166 return(1); 167 } 168 169 /* 170 * Attach this instance, and then all the sub-devices 171 */ 172 void 173 cbscattach(parent, self, aux) 174 struct device *parent, *self; 175 void *aux; 176 { 177 struct cbsc_softc *csc = (void *)self; 178 struct ncr53c9x_softc *sc = &csc->sc_ncr53c9x; 179 struct zbus_args *zap; 180 extern u_long scsi_nosync; 181 extern int shift_nosync; 182 extern int ncr53c9x_debug; 183 184 /* 185 * Set up the glue for MI code early; we use some of it here. 186 */ 187 sc->sc_glue = &cbsc_glue; 188 189 /* 190 * Save the regs 191 */ 192 zap = aux; 193 csc->sc_reg = &((volatile u_char *)zap->va)[0xf400]; 194 csc->sc_dmabase = &csc->sc_reg[0x400]; 195 196 sc->sc_freq = 40; /* Clocked at 40Mhz */ 197 198 printf(": address %p", csc->sc_reg); 199 200 sc->sc_id = 7; 201 202 /* 203 * It is necessary to try to load the 2nd config register here, 204 * to find out what rev the FAS chip is, else the ncr53c9x_reset 205 * will not set up the defaults correctly. 206 */ 207 sc->sc_cfg1 = sc->sc_id | NCRCFG1_PARENB; 208 sc->sc_cfg2 = NCRCFG2_SCSI2 | NCRCFG2_FE; 209 sc->sc_cfg3 = 0x08 /*FCLK*/ | NCRESPCFG3_FSCSI | NCRESPCFG3_CDB; 210 sc->sc_rev = NCR_VARIANT_FAS216; 211 212 /* 213 * This is the value used to start sync negotiations 214 * Note that the NCR register "SYNCTP" is programmed 215 * in "clocks per byte", and has a minimum value of 4. 216 * The SCSI period used in negotiation is one-fourth 217 * of the time (in nanoseconds) needed to transfer one byte. 218 * Since the chip's clock is given in MHz, we have the following 219 * formula: 4 * period = (1000 / freq) * 4 220 */ 221 sc->sc_minsync = 1000 / sc->sc_freq; 222 223 /* 224 * get flags from -I argument and set cf_flags. 225 * NOTE: low 8 bits are to disable disconnect, and the next 226 * 8 bits are to disable sync. 227 */ 228 sc->sc_dev.dv_cfdata->cf_flags |= (scsi_nosync >> shift_nosync) 229 & 0xffff; 230 shift_nosync += 16; 231 232 /* Use next 16 bits of -I argument to set ncr53c9x_debug flags */ 233 ncr53c9x_debug |= (scsi_nosync >> shift_nosync) & 0xffff; 234 shift_nosync += 16; 235 236 #if 1 237 if (((scsi_nosync >> shift_nosync) & 0xff00) == 0xff00) 238 sc->sc_minsync = 0; 239 #endif 240 241 /* Really no limit, but since we want to fit into the TCR... */ 242 sc->sc_maxxfer = 64 * 1024; 243 244 /* 245 * Configure interrupts. 246 */ 247 csc->sc_isr.isr_intr = (int (*)(void *))ncr53c9x_intr; 248 csc->sc_isr.isr_arg = sc; 249 csc->sc_isr.isr_ipl = 2; 250 add_isr(&csc->sc_isr); 251 252 /* 253 * Now try to attach all the sub-devices 254 */ 255 ncr53c9x_attach(sc, &cbsc_switch, &cbsc_dev); 256 } 257 258 /* 259 * Glue functions. 260 */ 261 262 u_char 263 cbsc_read_reg(sc, reg) 264 struct ncr53c9x_softc *sc; 265 int reg; 266 { 267 struct cbsc_softc *csc = (struct cbsc_softc *)sc; 268 269 return csc->sc_reg[reg * 4]; 270 } 271 272 void 273 cbsc_write_reg(sc, reg, val) 274 struct ncr53c9x_softc *sc; 275 int reg; 276 u_char val; 277 { 278 struct cbsc_softc *csc = (struct cbsc_softc *)sc; 279 u_char v = val; 280 281 csc->sc_reg[reg * 4] = v; 282 #ifdef DEBUG 283 if (cbsc_trace_enable/* && sc->sc_nexus && sc->sc_nexus->xs->flags & SCSI_POLL*/ && 284 reg == NCR_CMD/* && csc->sc_active*/) { 285 cbsc_trace[(cbsc_trace_ptr - 1) & 127].yy = v; 286 /* printf(" cmd %x", v);*/ 287 } 288 #endif 289 } 290 291 int 292 cbsc_dma_isintr(sc) 293 struct ncr53c9x_softc *sc; 294 { 295 struct cbsc_softc *csc = (struct cbsc_softc *)sc; 296 297 if ((csc->sc_reg[NCR_STAT * 4] & NCRSTAT_INT) == 0) 298 return 0; 299 300 if (sc->sc_state == NCR_CONNECTED) 301 csc->sc_portbits |= CBSC_PB_LED; 302 else 303 csc->sc_portbits &= ~CBSC_PB_LED; 304 csc->sc_reg[0x802] = csc->sc_portbits; 305 306 if ((csc->sc_reg[0x802] & CBSC_HB_CREQ) == 0) 307 return 0; 308 #ifdef DEBUG 309 if (/*sc->sc_nexus && sc->sc_nexus->xs->flags & SCSI_POLL &&*/ cbsc_trace_enable) { 310 cbsc_trace[cbsc_trace_ptr].status = csc->sc_reg[NCR_STAT * 4]; 311 cbsc_trace[cbsc_trace_ptr].xx = csc->sc_reg[NCR_CMD * 4]; 312 cbsc_trace[cbsc_trace_ptr].yy = csc->sc_active; 313 cbsc_trace_ptr = (cbsc_trace_ptr + 1) & 127; 314 } 315 #endif 316 return 1; 317 } 318 319 void 320 cbsc_dma_reset(sc) 321 struct ncr53c9x_softc *sc; 322 { 323 struct cbsc_softc *csc = (struct cbsc_softc *)sc; 324 325 csc->sc_active = 0; 326 } 327 328 int 329 cbsc_dma_intr(sc) 330 struct ncr53c9x_softc *sc; 331 { 332 register struct cbsc_softc *csc = (struct cbsc_softc *)sc; 333 register int cnt; 334 335 NCR_DMA(("cbsc_dma_intr: cnt %d int %x stat %x fifo %d ", 336 csc->sc_dmasize, sc->sc_espintr, sc->sc_espstat, 337 csc->sc_reg[NCR_FFLAG * 4] & NCRFIFO_FF)); 338 if (csc->sc_active == 0) { 339 printf("cbsc_intr--inactive DMA\n"); 340 return -1; 341 } 342 343 /* update sc_dmaaddr and sc_pdmalen */ 344 cnt = csc->sc_reg[NCR_TCL * 4]; 345 cnt += csc->sc_reg[NCR_TCM * 4] << 8; 346 cnt += csc->sc_reg[NCR_TCH * 4] << 16; 347 if (!csc->sc_datain) { 348 cnt += csc->sc_reg[NCR_FFLAG * 4] & NCRFIFO_FF; 349 csc->sc_reg[NCR_CMD * 4] = NCRCMD_FLUSH; 350 } 351 cnt = csc->sc_dmasize - cnt; /* number of bytes transferred */ 352 NCR_DMA(("DMA xferred %d\n", cnt)); 353 if (csc->sc_xfr_align) { 354 bcopy(csc->sc_alignbuf, *csc->sc_dmaaddr, cnt); 355 csc->sc_xfr_align = 0; 356 } 357 *csc->sc_dmaaddr += cnt; 358 *csc->sc_pdmalen -= cnt; 359 csc->sc_active = 0; 360 return 0; 361 } 362 363 int 364 cbsc_dma_setup(sc, addr, len, datain, dmasize) 365 struct ncr53c9x_softc *sc; 366 caddr_t *addr; 367 size_t *len; 368 int datain; 369 size_t *dmasize; 370 { 371 struct cbsc_softc *csc = (struct cbsc_softc *)sc; 372 vm_offset_t pa; 373 u_char *ptr; 374 size_t xfer; 375 376 csc->sc_dmaaddr = addr; 377 csc->sc_pdmalen = len; 378 csc->sc_datain = datain; 379 csc->sc_dmasize = *dmasize; 380 /* 381 * DMA can be nasty for high-speed serial input, so limit the 382 * size of this DMA operation if the serial port is running at 383 * a high speed (higher than 19200 for now - should be adjusted 384 * based on cpu type and speed?). 385 * XXX - add serial speed check XXX 386 */ 387 if (ser_open_speed > 19200 && cbsc_max_dma != 0 && 388 csc->sc_dmasize > cbsc_max_dma) 389 csc->sc_dmasize = cbsc_max_dma; 390 ptr = *addr; /* Kernel virtual address */ 391 pa = kvtop(ptr); /* Physical address of DMA */ 392 xfer = min(csc->sc_dmasize, NBPG - (pa & (NBPG - 1))); 393 csc->sc_xfr_align = 0; 394 /* 395 * If output and unaligned, stuff odd byte into FIFO 396 */ 397 if (datain == 0 && (int)ptr & 1) { 398 NCR_DMA(("cbsc_dma_setup: align byte written to fifo\n")); 399 pa++; 400 xfer--; /* XXXX CHECK THIS !!!! XXXX */ 401 csc->sc_reg[NCR_FIFO * 4] = *ptr++; 402 } 403 /* 404 * If unaligned address, read unaligned bytes into alignment buffer 405 */ 406 else if ((int)ptr & 1) { 407 pa = kvtop((caddr_t)&csc->sc_alignbuf); 408 xfer = csc->sc_dmasize = min(xfer, sizeof (csc->sc_alignbuf)); 409 NCR_DMA(("cbsc_dma_setup: align read by %d bytes\n", xfer)); 410 csc->sc_xfr_align = 1; 411 } 412 ++cbsc_cnt_dma; /* number of DMA operations */ 413 414 while (xfer < csc->sc_dmasize) { 415 if ((pa + xfer) != kvtop(*addr + xfer)) 416 break; 417 if ((csc->sc_dmasize - xfer) < NBPG) 418 xfer = csc->sc_dmasize; 419 else 420 xfer += NBPG; 421 ++cbsc_cnt_dma3; 422 } 423 if (xfer != *len) 424 ++cbsc_cnt_dma2; 425 426 csc->sc_dmasize = xfer; 427 *dmasize = csc->sc_dmasize; 428 csc->sc_pa = pa; 429 #if defined(M68040) || defined(M68060) 430 if (mmutype == MMU_68040) { 431 if (csc->sc_xfr_align) { 432 dma_cachectl(csc->sc_alignbuf, 433 sizeof(csc->sc_alignbuf)); 434 } 435 else 436 dma_cachectl(*csc->sc_dmaaddr, csc->sc_dmasize); 437 } 438 #endif 439 440 if (csc->sc_datain) 441 pa &= ~1; 442 else 443 pa |= 1; 444 csc->sc_dmabase[0] = (u_int8_t)(pa >> 24); 445 csc->sc_dmabase[2] = (u_int8_t)(pa >> 16); 446 csc->sc_dmabase[4] = (u_int8_t)(pa >> 8); 447 csc->sc_dmabase[6] = (u_int8_t)(pa); 448 if (csc->sc_datain) 449 csc->sc_portbits &= ~CBSC_PB_WRITE; 450 else 451 csc->sc_portbits |= CBSC_PB_WRITE; 452 csc->sc_reg[0x802] = csc->sc_portbits; 453 csc->sc_active = 1; 454 return 0; 455 } 456 457 void 458 cbsc_dma_go(sc) 459 struct ncr53c9x_softc *sc; 460 { 461 } 462 463 void 464 cbsc_dma_stop(sc) 465 struct ncr53c9x_softc *sc; 466 { 467 } 468 469 int 470 cbsc_dma_isactive(sc) 471 struct ncr53c9x_softc *sc; 472 { 473 struct cbsc_softc *csc = (struct cbsc_softc *)sc; 474 475 return csc->sc_active; 476 } 477 478 #ifdef DEBUG 479 void 480 cbsc_dump() 481 { 482 int i; 483 484 i = cbsc_trace_ptr; 485 printf("cbsc_trace dump: ptr %x\n", cbsc_trace_ptr); 486 do { 487 if (cbsc_trace[i].hardbits == 0) { 488 i = (i + 1) & 127; 489 continue; 490 } 491 printf("%02x%02x%02x%02x(", cbsc_trace[i].hardbits, 492 cbsc_trace[i].status, cbsc_trace[i].xx, cbsc_trace[i].yy); 493 if (cbsc_trace[i].status & NCRSTAT_INT) 494 printf("NCRINT/"); 495 if (cbsc_trace[i].status & NCRSTAT_TC) 496 printf("NCRTC/"); 497 switch(cbsc_trace[i].status & NCRSTAT_PHASE) { 498 case 0: 499 printf("dataout"); break; 500 case 1: 501 printf("datain"); break; 502 case 2: 503 printf("cmdout"); break; 504 case 3: 505 printf("status"); break; 506 case 6: 507 printf("msgout"); break; 508 case 7: 509 printf("msgin"); break; 510 default: 511 printf("phase%d?", cbsc_trace[i].status & NCRSTAT_PHASE); 512 } 513 printf(") "); 514 i = (i + 1) & 127; 515 } while (i != cbsc_trace_ptr); 516 printf("\n"); 517 } 518 #endif 519
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