efa.c revision 1.13
1 /* $NetBSD: efa.c,v 1.13 2017/09/04 17:26:06 phx Exp $ */ 2 3 /*- 4 * Copyright (c) 2011 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Radoslaw Kujawa. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 19 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 20 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 21 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 22 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 23 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 24 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 25 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 26 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 27 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 28 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 29 * POSSIBILITY OF SUCH DAMAGE. 30 */ 31 32 /* 33 * Driver for FastATA 1200 EIDE controller, manufactured by ELBOX Computer. 34 * 35 * Gayle-related stuff inspired by wdc_amiga.c written by Michael L. Hitch 36 * and Aymeric Vincent. 37 */ 38 39 #include <sys/cdefs.h> 40 41 #include <sys/types.h> 42 #include <sys/param.h> 43 #include <sys/systm.h> 44 #include <sys/malloc.h> 45 #include <sys/device.h> 46 #include <sys/bus.h> 47 #include <sys/proc.h> 48 #include <sys/kernel.h> 49 #include <sys/kthread.h> 50 51 #include <machine/cpu.h> 52 #include <machine/intr.h> 53 #include <sys/bswap.h> 54 55 #include <amiga/amiga/cia.h> 56 #include <amiga/amiga/custom.h> 57 #include <amiga/amiga/device.h> 58 #include <amiga/amiga/gayle.h> 59 #include <amiga/dev/zbusvar.h> 60 61 #include <dev/ata/atavar.h> 62 #include <dev/ic/wdcvar.h> 63 64 #include <amiga/dev/efareg.h> 65 #include <amiga/dev/efavar.h> 66 67 #define EFA_32BIT_IO 1 68 /* #define EFA_NO_INTR 1 */ 69 /* #define EFA_DEBUG 1 */ 70 71 int efa_probe(device_t, cfdata_t, void *); 72 void efa_attach(device_t, device_t, void *); 73 int efa_intr(void *); 74 int efa_intr_soft(void *arg); 75 static void efa_set_opts(struct efa_softc *sc); 76 static bool efa_mapbase(struct efa_softc *sc); 77 static bool efa_mapreg_gayle(struct efa_softc *sc); 78 static bool efa_mapreg_native(struct efa_softc *sc); 79 static void efa_fata_subregion_pio0(struct wdc_regs *wdr_fata); 80 static void efa_fata_subregion_pion(struct wdc_regs *wdr_fata, bool data32); 81 static void efa_setup_channel(struct ata_channel *chp); 82 static void efa_attach_channel(struct efa_softc *sc, int i); 83 static void efa_select_regset(struct efa_softc *sc, int chnum, 84 uint8_t piomode); 85 static void efa_poll_kthread(void *arg); 86 static bool efa_compare_status(void); 87 #ifdef EFA_DEBUG 88 static void efa_debug_print_regmapping(struct wdc_regs *wdr_fata); 89 #endif /* EFA_DEBUG */ 90 91 CFATTACH_DECL_NEW(efa, sizeof(struct efa_softc), 92 efa_probe, efa_attach, NULL, NULL); 93 94 #define PIO_NSUPP 0xFFFFFFFF 95 96 static const bus_addr_t pio_offsets[] = 97 { FATA1_PIO0_OFF, PIO_NSUPP, PIO_NSUPP, FATA1_PIO3_OFF, FATA1_PIO4_OFF, 98 FATA1_PIO5_OFF }; 99 static const unsigned int wdr_offsets_pio0[] = 100 { FATA1_PIO0_OFF_DATA, FATA1_PIO0_OFF_ERROR, FATA1_PIO0_OFF_SECCNT, 101 FATA1_PIO0_OFF_SECTOR, FATA1_PIO0_OFF_CYL_LO, FATA1_PIO0_OFF_CYL_HI, 102 FATA1_PIO0_OFF_SDH, FATA1_PIO0_OFF_COMMAND }; 103 static const unsigned int wdr_offsets_pion[] = 104 { FATA1_PION_OFF_DATA, FATA1_PION_OFF_ERROR, FATA1_PION_OFF_SECCNT, 105 FATA1_PION_OFF_SECTOR, FATA1_PION_OFF_CYL_LO, FATA1_PION_OFF_CYL_HI, 106 FATA1_PION_OFF_SDH, FATA1_PION_OFF_COMMAND }; 107 108 int 109 efa_probe(device_t parent, cfdata_t cfp, void *aux) 110 { 111 /* 112 * FastATA 1200 uses portions of Gayle IDE interface, and efa driver 113 * can't coexist with wdc_amiga. Match "wdc" on an A1200, because 114 * FastATA 1200 does not autoconfigure. 115 */ 116 if (!matchname(aux, "wdc") || !is_a1200()) 117 return(0); 118 119 if (!efa_compare_status()) 120 return(0); 121 122 #ifdef EFA_DEBUG 123 aprint_normal("efa_probe succeeded\n"); 124 #endif /* EFA_DEBUG */ 125 126 return 100; 127 } 128 129 void 130 efa_attach(device_t parent, device_t self, void *aux) 131 { 132 int i; 133 struct efa_softc *sc = device_private(self); 134 135 aprint_normal(": ELBOX FastATA 1200\n"); 136 137 gayle_init(); 138 139 efa_set_opts(sc); 140 141 if (!efa_mapbase(sc)) { 142 aprint_error_dev(self, "couldn't map base addresses\n"); 143 return; 144 } 145 if (!efa_mapreg_gayle(sc)) { 146 aprint_error_dev(self, "couldn't map Gayle registers\n"); 147 return; 148 } 149 if (!efa_mapreg_native(sc)) { 150 aprint_error_dev(self, "couldn't map FastATA regsters\n"); 151 return; 152 } 153 154 sc->sc_wdcdev.sc_atac.atac_pio_cap = 5; 155 sc->sc_wdcdev.sc_atac.atac_nchannels = FATA1_CHANNELS; 156 sc->sc_wdcdev.sc_atac.atac_set_modes = efa_setup_channel; 157 sc->sc_wdcdev.sc_atac.atac_dev = self; 158 sc->sc_wdcdev.sc_atac.atac_channels = sc->sc_chanlist; 159 sc->sc_wdcdev.sc_atac.atac_cap = ATAC_CAP_DATA16; 160 sc->sc_wdcdev.wdc_maxdrives = 2; 161 162 if (sc->sc_32bit_io) 163 sc->sc_wdcdev.sc_atac.atac_cap |= ATAC_CAP_DATA32; 164 165 /* 166 * The following should work for polling mode, but it does not. 167 * if (sc->sc_no_intr) 168 * sc->sc_wdcdev.sc_atac.atac_cap |= ATAC_CAP_NOIRQ; 169 */ 170 171 wdc_allocate_regs(&sc->sc_wdcdev); 172 173 for (i = 0; i < FATA1_CHANNELS; i++) 174 efa_attach_channel(sc, i); 175 176 if (sc->sc_no_intr) { 177 sc->sc_fata_softintr = softint_establish(SOFTINT_BIO, 178 (void (*)(void *))efa_intr_soft, sc); 179 if (sc->sc_fata_softintr == NULL) { 180 aprint_error_dev(self, "couldn't create soft intr\n"); 181 return; 182 } 183 if (kthread_create(PRI_NONE, 0, NULL, efa_poll_kthread, sc, 184 NULL, "efa")) { 185 aprint_error_dev(self, "couldn't create kthread\n"); 186 return; 187 } 188 } else { 189 sc->sc_isr.isr_intr = efa_intr; 190 sc->sc_isr.isr_arg = sc; 191 sc->sc_isr.isr_ipl = 2; 192 add_isr (&sc->sc_isr); 193 gayle_intr_enable_set(GAYLE_INT_IDE); 194 } 195 196 } 197 198 static void 199 efa_attach_channel(struct efa_softc *sc, int chnum) 200 { 201 #ifdef EFA_DEBUG 202 device_t self; 203 204 self = sc->sc_wdcdev.sc_atac.atac_dev; 205 #endif /* EFA_DEBUG */ 206 207 sc->sc_chanlist[chnum] = &sc->sc_ports[chnum].chan; 208 209 sc->sc_ports[chnum].chan.ch_channel = chnum; 210 sc->sc_ports[chnum].chan.ch_atac = &sc->sc_wdcdev.sc_atac; 211 sc->sc_ports[chnum].chan.ch_queue = &sc->sc_ports[chnum].queue; 212 213 if (!sc->sc_32bit_io) 214 efa_select_regset(sc, chnum, 0); /* Start in PIO0. */ 215 else 216 efa_select_regset(sc, chnum, 3); 217 218 wdc_init_shadow_regs(&sc->sc_ports[chnum].chan); 219 220 wdcattach(&sc->sc_ports[chnum].chan); 221 222 #ifdef EFA_DEBUG 223 aprint_normal_dev(self, "done init for channel %d\n", chnum); 224 #endif 225 226 } 227 228 /* TODO: convert to callout(9) */ 229 static void 230 efa_poll_kthread(void *arg) 231 { 232 struct efa_softc *sc = arg; 233 234 for (;;) { 235 /* TODO: actually check if interrupt status register is set */ 236 softint_schedule(sc->sc_fata_softintr); 237 /* TODO: convert to kpause */ 238 tsleep(arg, PWAIT, "efa_poll", hz); 239 } 240 } 241 242 static void 243 efa_set_opts(struct efa_softc *sc) 244 { 245 device_t self; 246 247 self = sc->sc_wdcdev.sc_atac.atac_dev; 248 249 #ifdef EFA_32BIT_IO 250 sc->sc_32bit_io = true; 251 #else 252 sc->sc_32bit_io = false; 253 #endif /* EFA_32BIT_IO */ 254 255 #ifdef EFA_NO_INTR 256 sc->sc_no_intr = true; /* XXX: not yet! */ 257 #else 258 sc->sc_no_intr = false; 259 #endif /* EFA_NO_INTR */ 260 261 if (sc->sc_no_intr) 262 aprint_verbose_dev(self, "hardware interrupt disabled\n"); 263 264 if (sc->sc_32bit_io) 265 aprint_verbose_dev(self, "32-bit I/O enabled\n"); 266 } 267 268 int 269 efa_intr_soft(void *arg) 270 { 271 int ret = 0; 272 struct efa_softc *sc = (struct efa_softc *)arg; 273 274 /* TODO: check which channel needs servicing */ 275 /* 276 uint8_t fataintreq; 277 fataintreq = bus_space_read_1(sc->sc_ports[0].wdr[piom].cmd_iot, 278 sc->sc_ports[chnum].intst[piom], 0); 279 */ 280 281 ret = wdcintr(&sc->sc_ports[0].chan); 282 ret = wdcintr(&sc->sc_ports[1].chan); 283 284 return ret; 285 } 286 287 int 288 efa_intr(void *arg) 289 { 290 struct efa_softc *sc = (struct efa_softc *)arg; 291 int r1, r2, ret; 292 uint8_t intreq; 293 294 intreq = gayle_intr_status(); 295 ret = 0; 296 297 if (intreq & GAYLE_INT_IDE) { 298 gayle_intr_ack(0x7C | (intreq & 0x03)); 299 /* How to check which channel caused interrupt? 300 * Interrupt status register is not very useful here. */ 301 r1 = wdcintr(&sc->sc_ports[0].chan); 302 r2 = wdcintr(&sc->sc_ports[1].chan); 303 ret = r1 | r2; 304 } 305 306 return ret; 307 } 308 309 static bool 310 efa_mapbase(struct efa_softc *sc) 311 { 312 static struct bus_space_tag fata_cmd_iot; 313 static struct bus_space_tag gayle_cmd_iot; 314 int i, j; 315 #ifdef EFA_DEBUG 316 device_t self; 317 318 self = sc->sc_wdcdev.sc_atac.atac_dev; 319 #endif /* EFA_DEBUG */ 320 321 gayle_cmd_iot.base = (bus_addr_t) ztwomap(GAYLE_IDE_BASE + 2); 322 gayle_cmd_iot.absm = &amiga_bus_stride_4swap; 323 fata_cmd_iot.base = (bus_addr_t) ztwomap(FATA1_BASE); 324 fata_cmd_iot.absm = &amiga_bus_stride_4swap; 325 326 #ifdef EFA_DEBUG 327 aprint_normal_dev(self, "Gayle %x -> %x, FastATA %x -> %x\n", 328 GAYLE_IDE_BASE, gayle_cmd_iot.base, FATA1_BASE, fata_cmd_iot.base); 329 #endif 330 331 if (!gayle_cmd_iot.base) 332 return false; 333 if (!fata_cmd_iot.base) 334 return false; 335 336 sc->sc_gayle_wdc_regs.cmd_iot = &gayle_cmd_iot; 337 sc->sc_gayle_wdc_regs.ctl_iot = &gayle_cmd_iot; 338 339 for (i = 0; i < FATA1_CHANNELS; i++) { 340 for (j = 0; j < PIO_COUNT; j++) { 341 sc->sc_ports[i].wdr[j].cmd_iot = &fata_cmd_iot; 342 sc->sc_ports[i].wdr[j].data32iot = &fata_cmd_iot; 343 sc->sc_ports[i].wdr[j].ctl_iot = &gayle_cmd_iot; 344 } 345 } 346 347 return true; 348 } 349 350 351 /* Gayle IDE register mapping, we need it anyway. */ 352 static bool 353 efa_mapreg_gayle(struct efa_softc *sc) 354 { 355 int i; 356 357 struct wdc_regs *wdr = &sc->sc_gayle_wdc_regs; 358 359 if (bus_space_map(wdr->cmd_iot, 0, 0x40, 0, 360 &wdr->cmd_baseioh)) { 361 return false; 362 } 363 364 for (i = 0; i < WDC_NREG; i++) { 365 if (bus_space_subregion(wdr->cmd_iot, 366 wdr->cmd_baseioh, i, i == 0 ? 4 : 1, 367 &wdr->cmd_iohs[i]) != 0) { 368 369 bus_space_unmap(wdr->cmd_iot, 370 wdr->cmd_baseioh, 0x40); 371 return false; 372 } 373 } 374 375 if (bus_space_subregion(wdr->cmd_iot, 376 wdr->cmd_baseioh, 0x406, 1, &wdr->ctl_ioh)) 377 return false; 378 379 return true; 380 } 381 382 /* Native FastATA register mapping, suitable for PIO modes 0 to 5. */ 383 static bool 384 efa_mapreg_native(struct efa_softc *sc) 385 { 386 struct wdc_regs *wdr_gayle = &sc->sc_gayle_wdc_regs; 387 struct wdc_regs *wdr_fata; 388 int i,j; 389 #ifdef EFA_DEBUG 390 device_t self; 391 392 self = sc->sc_wdcdev.sc_atac.atac_dev; 393 #endif /* EFA_DEBUG */ 394 395 for (i = 0; i < FATA1_CHANNELS; i++) { 396 397 for (j = 0; j < PIO_COUNT; j++) { 398 399 wdr_fata = &sc->sc_ports[i].wdr[j]; 400 sc->sc_ports[i].mode_ok[j] = false; 401 402 if (pio_offsets[j] == PIO_NSUPP) { 403 #ifdef EFA_DEBUG 404 aprint_normal_dev(self, 405 "Skipping mapping for PIO mode %x\n", j); 406 #endif 407 continue; 408 } 409 410 if (bus_space_map(wdr_fata->cmd_iot, 411 pio_offsets[j] + FATA1_CHAN_SIZE * i, 412 FATA1_CHAN_SIZE, 0, &wdr_fata->cmd_baseioh)) { 413 return false; 414 } 415 #ifdef EFA_DEBUG 416 aprint_normal_dev(self, 417 "Chan %x PIO mode %x mapped %x -> %x\n", 418 i, j, (bus_addr_t) kvtop((void*) 419 wdr_fata->cmd_baseioh), (unsigned int) 420 wdr_fata->cmd_baseioh); 421 #endif 422 423 sc->sc_ports[i].mode_ok[j] = true; 424 425 if (j == 0) 426 efa_fata_subregion_pio0(wdr_fata); 427 else { 428 if (sc->sc_32bit_io) 429 efa_fata_subregion_pion(wdr_fata, 430 true); 431 else 432 efa_fata_subregion_pion(wdr_fata, 433 false); 434 435 bus_space_subregion(wdr_fata->cmd_iot, 436 wdr_fata->cmd_baseioh, FATA1_PION_OFF_INTST, 437 1, &sc->sc_ports[i].intst[j]); 438 } 439 440 /* No 32-bit register for PIO0 ... */ 441 if (j == 0 && sc->sc_32bit_io) 442 sc->sc_ports[i].mode_ok[j] = false; 443 444 wdr_fata->ctl_ioh = wdr_gayle->ctl_ioh; 445 }; 446 } 447 return true; 448 } 449 450 451 static void 452 efa_fata_subregion_pio0(struct wdc_regs *wdr_fata) 453 { 454 int i; 455 456 for (i = 0; i < WDC_NREG; i++) 457 bus_space_subregion(wdr_fata->cmd_iot, 458 wdr_fata->cmd_baseioh, wdr_offsets_pio0[i], 459 i == 0 ? 4 : 1, &wdr_fata->cmd_iohs[i]); 460 } 461 462 static void 463 efa_fata_subregion_pion(struct wdc_regs *wdr_fata, bool data32) 464 { 465 int i; 466 467 if (data32) 468 bus_space_subregion(wdr_fata->cmd_iot, wdr_fata->cmd_baseioh, 469 FATA1_PION_OFF_DATA32, 8, &wdr_fata->data32ioh); 470 471 for (i = 0; i < WDC_NREG; i++) 472 bus_space_subregion(wdr_fata->cmd_iot, 473 wdr_fata->cmd_baseioh, wdr_offsets_pion[i], 474 i == 0 ? 4 : 1, &wdr_fata->cmd_iohs[i]); 475 } 476 477 static void 478 efa_setup_channel(struct ata_channel *chp) 479 { 480 int drive, chnum; 481 uint8_t mode; 482 struct atac_softc *atac; 483 struct ata_drive_datas *drvp; 484 struct efa_softc *sc; 485 int ipl; 486 #ifdef EFA_DEBUG 487 device_t self; 488 #endif /* EFA_DEBUG */ 489 490 chnum = chp->ch_channel; 491 atac = chp->ch_atac; 492 493 sc = device_private(atac->atac_dev); 494 495 mode = 5; /* start with fastest possible setting */ 496 497 #ifdef EFA_DEBUG 498 self = sc->sc_wdcdev.sc_atac.atac_dev; 499 aprint_normal_dev(self, "efa_setup_channel for ch %d\n", 500 chnum); 501 #endif /* EFA_DEBUG */ 502 503 /* We might be in the middle of something... so raise IPL. */ 504 ipl = splvm(); 505 506 for (drive = 0; drive < 2; drive++) { 507 drvp = &chp->ch_drive[drive]; 508 509 if (drvp->drive_type == ATA_DRIVET_NONE) 510 continue; /* nothing to see here */ 511 512 if (drvp->PIO_cap < mode) 513 mode = drvp->PIO_cap; 514 515 /* TODO: check if sc_ports->mode_ok */ 516 517 #ifdef EFA_DEBUG 518 aprint_normal_dev(self, "drive %d supports %d\n", 519 drive, drvp->PIO_cap); 520 #endif /* EFA_DEBUG */ 521 522 drvp->PIO_mode = mode; 523 } 524 525 /* Change FastATA register set. */ 526 efa_select_regset(sc, chnum, mode); 527 /* re-init shadow regs */ 528 wdc_init_shadow_regs(&sc->sc_ports[chnum].chan); 529 530 splx(ipl); 531 } 532 533 static void 534 efa_select_regset(struct efa_softc *sc, int chnum, uint8_t piomode) 535 { 536 struct wdc_softc *wdc; 537 #ifdef EFA_DEBUG 538 device_t self; 539 540 self = sc->sc_wdcdev.sc_atac.atac_dev; 541 #endif /* EFA_DEBUG */ 542 543 wdc = CHAN_TO_WDC(&sc->sc_ports[chnum].chan); 544 wdc->regs[chnum] = sc->sc_ports[chnum].wdr[piomode]; 545 546 #ifdef EFA_DEBUG 547 aprint_normal_dev(self, "switched ch %d to PIO %d\n", 548 chnum, piomode); 549 550 efa_debug_print_regmapping(&wdc->regs[chnum]); 551 #endif /* EFA_DEBUG */ 552 } 553 554 #ifdef EFA_DEBUG 555 static void 556 efa_debug_print_regmapping(struct wdc_regs *wdr_fata) 557 { 558 int i; 559 aprint_normal("base %x->%x", 560 (bus_addr_t) kvtop((void*) wdr_fata->cmd_baseioh), 561 (bus_addr_t) wdr_fata->cmd_baseioh); 562 for (i = 0; i < WDC_NREG; i++) { 563 aprint_normal("reg %x, %x->%x, ", i, 564 (bus_addr_t) kvtop((void*) wdr_fata->cmd_iohs[i]), 565 (bus_addr_t) wdr_fata->cmd_iohs[i]); 566 } 567 aprint_normal("\n"); 568 } 569 #endif /* EFA_DEBUG */ 570 571 /* Compare the values of (status) command register in PIO0, PIO3 sets. */ 572 static bool 573 efa_compare_status(void) 574 { 575 uint8_t cmd0, cmd3; 576 struct bus_space_tag fata_bst; 577 bus_space_tag_t fata_iot; 578 bus_space_handle_t cmd0_ioh, cmd3_ioh; 579 bool rv; 580 581 rv = false; 582 583 fata_bst.base = (bus_addr_t) ztwomap(FATA1_BASE); 584 fata_bst.absm = &amiga_bus_stride_4swap; 585 586 fata_iot = &fata_bst; 587 588 if (bus_space_map(fata_iot, pio_offsets[0], FATA1_CHAN_SIZE, 0, 589 &cmd0_ioh)) 590 return false; 591 if (bus_space_map(fata_iot, pio_offsets[3], FATA1_CHAN_SIZE, 0, 592 &cmd3_ioh)) 593 return false; 594 595 #ifdef EFA_DEBUG 596 aprint_normal("probing for FastATA at %x, %x: ", (bus_addr_t) cmd0_ioh, 597 (bus_addr_t) cmd3_ioh); 598 #endif /* EFA_DEBUG */ 599 600 cmd0 = bus_space_read_1(fata_iot, cmd0_ioh, FATA1_PIO0_OFF_COMMAND); 601 cmd3 = bus_space_read_1(fata_iot, cmd3_ioh, FATA1_PION_OFF_COMMAND); 602 603 if (cmd0 == cmd3) 604 rv = true; 605 606 if ( (cmd0 == 0xFF) || (cmd0 == 0x00) ) { 607 /* Assume there's nothing there... */ 608 rv = false; 609 } 610 611 #ifdef EFA_DEBUG 612 aprint_normal("cmd0 %x, cmd3 %x\n", cmd0, cmd3); 613 #endif /* EFA_DEBUG */ 614 615 bus_space_unmap(fata_iot, pio_offsets[0], FATA1_CHAN_SIZE); 616 bus_space_unmap(fata_iot, pio_offsets[3], FATA1_CHAN_SIZE); 617 618 return rv; 619 } 620 621
Indexes created Tue Sep 30 20:09:53 GMT 2025