efa.c revision 1.16
1 /* $NetBSD: efa.c,v 1.16 2023/05/06 21:34:39 andvar Exp $ */ 2 3 /*- 4 * Copyright (c) 2011 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Radoslaw Kujawa. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 19 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 20 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 21 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 22 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 23 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 24 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 25 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 26 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 27 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 28 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 29 * POSSIBILITY OF SUCH DAMAGE. 30 */ 31 32 /* 33 * Driver for FastATA 1200 EIDE controller, manufactured by ELBOX Computer. 34 * 35 * Gayle-related stuff inspired by wdc_amiga.c written by Michael L. Hitch 36 * and Aymeric Vincent. 37 */ 38 39 #include <sys/cdefs.h> 40 41 #include <sys/types.h> 42 #include <sys/param.h> 43 #include <sys/systm.h> 44 #include <sys/malloc.h> 45 #include <sys/device.h> 46 #include <sys/bus.h> 47 #include <sys/proc.h> 48 #include <sys/kernel.h> 49 #include <sys/kthread.h> 50 51 #include <machine/cpu.h> 52 #include <machine/intr.h> 53 #include <sys/bswap.h> 54 55 #include <amiga/amiga/cia.h> 56 #include <amiga/amiga/custom.h> 57 #include <amiga/amiga/device.h> 58 #include <amiga/amiga/gayle.h> 59 #include <amiga/dev/zbusvar.h> 60 61 #include <dev/ata/atavar.h> 62 #include <dev/ic/wdcvar.h> 63 64 #include <amiga/dev/efareg.h> 65 #include <amiga/dev/efavar.h> 66 67 #define EFA_32BIT_IO 1 68 /* #define EFA_NO_INTR 1 */ 69 /* #define EFA_DEBUG 1 */ 70 71 int efa_probe(device_t, cfdata_t, void *); 72 void efa_attach(device_t, device_t, void *); 73 int efa_intr(void *); 74 int efa_intr_soft(void *arg); 75 static void efa_set_opts(struct efa_softc *sc); 76 static bool efa_mapbase(struct efa_softc *sc); 77 static bool efa_mapreg_gayle(struct efa_softc *sc); 78 static bool efa_mapreg_native(struct efa_softc *sc); 79 static void efa_fata_subregion_pio0(struct wdc_regs *wdr_fata); 80 static void efa_fata_subregion_pion(struct wdc_regs *wdr_fata, bool data32); 81 static void efa_setup_channel(struct ata_channel *chp); 82 static void efa_attach_channel(struct efa_softc *sc, int i); 83 static void efa_select_regset(struct efa_softc *sc, int chnum, 84 uint8_t piomode); 85 static void efa_poll_kthread(void *arg); 86 static bool efa_compare_status(void); 87 #ifdef EFA_DEBUG 88 static void efa_debug_print_regmapping(struct wdc_regs *wdr_fata); 89 #endif /* EFA_DEBUG */ 90 91 CFATTACH_DECL_NEW(efa, sizeof(struct efa_softc), 92 efa_probe, efa_attach, NULL, NULL); 93 94 #define PIO_NSUPP 0xFFFFFFFF 95 96 static const bus_addr_t pio_offsets[] = 97 { FATA1_PIO0_OFF, PIO_NSUPP, PIO_NSUPP, FATA1_PIO3_OFF, FATA1_PIO4_OFF, 98 FATA1_PIO5_OFF }; 99 static const unsigned int wdr_offsets_pio0[] = 100 { FATA1_PIO0_OFF_DATA, FATA1_PIO0_OFF_ERROR, FATA1_PIO0_OFF_SECCNT, 101 FATA1_PIO0_OFF_SECTOR, FATA1_PIO0_OFF_CYL_LO, FATA1_PIO0_OFF_CYL_HI, 102 FATA1_PIO0_OFF_SDH, FATA1_PIO0_OFF_COMMAND }; 103 static const unsigned int wdr_offsets_pion[] = 104 { FATA1_PION_OFF_DATA, FATA1_PION_OFF_ERROR, FATA1_PION_OFF_SECCNT, 105 FATA1_PION_OFF_SECTOR, FATA1_PION_OFF_CYL_LO, FATA1_PION_OFF_CYL_HI, 106 FATA1_PION_OFF_SDH, FATA1_PION_OFF_COMMAND }; 107 108 int 109 efa_probe(device_t parent, cfdata_t cfp, void *aux) 110 { 111 /* 112 * FastATA 1200 uses portions of Gayle IDE interface, and efa driver 113 * can't coexist with wdc_amiga. Match "wdc" on an A1200, because 114 * FastATA 1200 does not autoconfigure. 115 */ 116 if (!matchname(aux, "wdc") || !is_a1200()) 117 return(0); 118 119 if (!efa_compare_status()) 120 return(0); 121 122 #ifdef EFA_DEBUG 123 aprint_normal("efa_probe succeeded\n"); 124 #endif /* EFA_DEBUG */ 125 126 return 100; 127 } 128 129 void 130 efa_attach(device_t parent, device_t self, void *aux) 131 { 132 int i; 133 struct efa_softc *sc = device_private(self); 134 135 aprint_normal(": ELBOX FastATA 1200\n"); 136 137 gayle_init(); 138 139 efa_set_opts(sc); 140 141 if (!efa_mapbase(sc)) { 142 aprint_error_dev(self, "couldn't map base addresses\n"); 143 return; 144 } 145 if (!efa_mapreg_gayle(sc)) { 146 aprint_error_dev(self, "couldn't map Gayle registers\n"); 147 return; 148 } 149 if (!efa_mapreg_native(sc)) { 150 aprint_error_dev(self, "couldn't map FastATA registers\n"); 151 return; 152 } 153 154 sc->sc_wdcdev.sc_atac.atac_pio_cap = 5; 155 sc->sc_wdcdev.sc_atac.atac_nchannels = FATA1_CHANNELS; 156 sc->sc_wdcdev.sc_atac.atac_set_modes = efa_setup_channel; 157 sc->sc_wdcdev.sc_atac.atac_dev = self; 158 sc->sc_wdcdev.sc_atac.atac_channels = sc->sc_chanlist; 159 sc->sc_wdcdev.sc_atac.atac_cap = ATAC_CAP_DATA16; 160 sc->sc_wdcdev.wdc_maxdrives = 2; 161 162 if (sc->sc_32bit_io) 163 sc->sc_wdcdev.sc_atac.atac_cap |= ATAC_CAP_DATA32; 164 165 /* 166 * The following should work for polling mode, but it does not. 167 * if (sc->sc_no_intr) 168 * sc->sc_wdcdev.sc_atac.atac_cap |= ATAC_CAP_NOIRQ; 169 */ 170 171 wdc_allocate_regs(&sc->sc_wdcdev); 172 173 for (i = 0; i < FATA1_CHANNELS; i++) 174 efa_attach_channel(sc, i); 175 176 if (sc->sc_no_intr) { 177 sc->sc_fata_softintr = softint_establish(SOFTINT_BIO, 178 (void (*)(void *))efa_intr_soft, sc); 179 if (sc->sc_fata_softintr == NULL) { 180 aprint_error_dev(self, "couldn't create soft intr\n"); 181 return; 182 } 183 if (kthread_create(PRI_NONE, 0, NULL, efa_poll_kthread, sc, 184 NULL, "efa")) { 185 aprint_error_dev(self, "couldn't create kthread\n"); 186 return; 187 } 188 } else { 189 sc->sc_isr.isr_intr = efa_intr; 190 sc->sc_isr.isr_arg = sc; 191 sc->sc_isr.isr_ipl = 2; 192 add_isr (&sc->sc_isr); 193 gayle_intr_enable_set(GAYLE_INT_IDE); 194 } 195 196 } 197 198 static void 199 efa_attach_channel(struct efa_softc *sc, int chnum) 200 { 201 #ifdef EFA_DEBUG 202 device_t self; 203 204 self = sc->sc_wdcdev.sc_atac.atac_dev; 205 #endif /* EFA_DEBUG */ 206 207 sc->sc_chanlist[chnum] = &sc->sc_ports[chnum].chan; 208 209 sc->sc_ports[chnum].chan.ch_channel = chnum; 210 sc->sc_ports[chnum].chan.ch_atac = &sc->sc_wdcdev.sc_atac; 211 212 if (!sc->sc_32bit_io) 213 efa_select_regset(sc, chnum, 0); /* Start in PIO0. */ 214 else 215 efa_select_regset(sc, chnum, 3); 216 217 wdc_init_shadow_regs(CHAN_TO_WDC_REGS(&sc->sc_ports[chnum].chan)); 218 219 wdcattach(&sc->sc_ports[chnum].chan); 220 221 #ifdef EFA_DEBUG 222 aprint_normal_dev(self, "done init for channel %d\n", chnum); 223 #endif 224 225 } 226 227 /* TODO: convert to callout(9) */ 228 static void 229 efa_poll_kthread(void *arg) 230 { 231 struct efa_softc *sc = arg; 232 233 for (;;) { 234 /* TODO: actually check if interrupt status register is set */ 235 softint_schedule(sc->sc_fata_softintr); 236 /* TODO: convert to kpause */ 237 tsleep(arg, PWAIT, "efa_poll", hz); 238 } 239 } 240 241 static void 242 efa_set_opts(struct efa_softc *sc) 243 { 244 device_t self; 245 246 self = sc->sc_wdcdev.sc_atac.atac_dev; 247 248 #ifdef EFA_32BIT_IO 249 sc->sc_32bit_io = true; 250 #else 251 sc->sc_32bit_io = false; 252 #endif /* EFA_32BIT_IO */ 253 254 #ifdef EFA_NO_INTR 255 sc->sc_no_intr = true; /* XXX: not yet! */ 256 #else 257 sc->sc_no_intr = false; 258 #endif /* EFA_NO_INTR */ 259 260 if (sc->sc_no_intr) 261 aprint_verbose_dev(self, "hardware interrupt disabled\n"); 262 263 if (sc->sc_32bit_io) 264 aprint_verbose_dev(self, "32-bit I/O enabled\n"); 265 } 266 267 int 268 efa_intr_soft(void *arg) 269 { 270 int ret = 0; 271 struct efa_softc *sc = (struct efa_softc *)arg; 272 273 /* TODO: check which channel needs servicing */ 274 /* 275 uint8_t fataintreq; 276 fataintreq = bus_space_read_1(sc->sc_ports[0].wdr[piom].cmd_iot, 277 sc->sc_ports[chnum].intst[piom], 0); 278 */ 279 280 ret = wdcintr(&sc->sc_ports[0].chan); 281 ret = wdcintr(&sc->sc_ports[1].chan); 282 283 return ret; 284 } 285 286 int 287 efa_intr(void *arg) 288 { 289 struct efa_softc *sc = (struct efa_softc *)arg; 290 int r1, r2, ret; 291 uint8_t intreq; 292 293 intreq = gayle_intr_status(); 294 ret = 0; 295 296 if (intreq & GAYLE_INT_IDE) { 297 gayle_intr_ack(0x7C | (intreq & 0x03)); 298 /* How to check which channel caused interrupt? 299 * Interrupt status register is not very useful here. */ 300 r1 = wdcintr(&sc->sc_ports[0].chan); 301 r2 = wdcintr(&sc->sc_ports[1].chan); 302 ret = r1 | r2; 303 } 304 305 return ret; 306 } 307 308 static bool 309 efa_mapbase(struct efa_softc *sc) 310 { 311 static struct bus_space_tag fata_cmd_iot; 312 static struct bus_space_tag gayle_cmd_iot; 313 int i, j; 314 #ifdef EFA_DEBUG 315 device_t self; 316 317 self = sc->sc_wdcdev.sc_atac.atac_dev; 318 #endif /* EFA_DEBUG */ 319 320 gayle_cmd_iot.base = (bus_addr_t) ztwomap(GAYLE_IDE_BASE + 2); 321 gayle_cmd_iot.absm = &amiga_bus_stride_4swap; 322 fata_cmd_iot.base = (bus_addr_t) ztwomap(FATA1_BASE); 323 fata_cmd_iot.absm = &amiga_bus_stride_4swap; 324 325 #ifdef EFA_DEBUG 326 aprint_normal_dev(self, "Gayle %x -> %x, FastATA %x -> %x\n", 327 GAYLE_IDE_BASE, gayle_cmd_iot.base, FATA1_BASE, fata_cmd_iot.base); 328 #endif 329 330 if (!gayle_cmd_iot.base) 331 return false; 332 if (!fata_cmd_iot.base) 333 return false; 334 335 sc->sc_gayle_wdc_regs.cmd_iot = &gayle_cmd_iot; 336 sc->sc_gayle_wdc_regs.ctl_iot = &gayle_cmd_iot; 337 338 for (i = 0; i < FATA1_CHANNELS; i++) { 339 for (j = 0; j < PIO_COUNT; j++) { 340 sc->sc_ports[i].wdr[j].cmd_iot = &fata_cmd_iot; 341 sc->sc_ports[i].wdr[j].data32iot = &fata_cmd_iot; 342 sc->sc_ports[i].wdr[j].ctl_iot = &gayle_cmd_iot; 343 } 344 } 345 346 return true; 347 } 348 349 350 /* Gayle IDE register mapping, we need it anyway. */ 351 static bool 352 efa_mapreg_gayle(struct efa_softc *sc) 353 { 354 int i; 355 356 struct wdc_regs *wdr = &sc->sc_gayle_wdc_regs; 357 358 if (bus_space_map(wdr->cmd_iot, 0, 0x40, 0, 359 &wdr->cmd_baseioh)) { 360 return false; 361 } 362 363 for (i = 0; i < WDC_NREG; i++) { 364 if (bus_space_subregion(wdr->cmd_iot, 365 wdr->cmd_baseioh, i, i == 0 ? 4 : 1, 366 &wdr->cmd_iohs[i]) != 0) { 367 368 bus_space_unmap(wdr->cmd_iot, 369 wdr->cmd_baseioh, 0x40); 370 return false; 371 } 372 } 373 374 if (bus_space_subregion(wdr->cmd_iot, 375 wdr->cmd_baseioh, 0x406, 1, &wdr->ctl_ioh)) 376 return false; 377 378 return true; 379 } 380 381 /* Native FastATA register mapping, suitable for PIO modes 0 to 5. */ 382 static bool 383 efa_mapreg_native(struct efa_softc *sc) 384 { 385 struct wdc_regs *wdr_gayle = &sc->sc_gayle_wdc_regs; 386 struct wdc_regs *wdr_fata; 387 int i,j; 388 #ifdef EFA_DEBUG 389 device_t self; 390 391 self = sc->sc_wdcdev.sc_atac.atac_dev; 392 #endif /* EFA_DEBUG */ 393 394 for (i = 0; i < FATA1_CHANNELS; i++) { 395 396 for (j = 0; j < PIO_COUNT; j++) { 397 398 wdr_fata = &sc->sc_ports[i].wdr[j]; 399 sc->sc_ports[i].mode_ok[j] = false; 400 401 if (pio_offsets[j] == PIO_NSUPP) { 402 #ifdef EFA_DEBUG 403 aprint_normal_dev(self, 404 "Skipping mapping for PIO mode %x\n", j); 405 #endif 406 continue; 407 } 408 409 if (bus_space_map(wdr_fata->cmd_iot, 410 pio_offsets[j] + FATA1_CHAN_SIZE * i, 411 FATA1_CHAN_SIZE, 0, &wdr_fata->cmd_baseioh)) { 412 return false; 413 } 414 #ifdef EFA_DEBUG 415 aprint_normal_dev(self, 416 "Chan %x PIO mode %x mapped %x -> %x\n", 417 i, j, (bus_addr_t) kvtop((void*) 418 wdr_fata->cmd_baseioh), (unsigned int) 419 wdr_fata->cmd_baseioh); 420 #endif 421 422 sc->sc_ports[i].mode_ok[j] = true; 423 424 if (j == 0) 425 efa_fata_subregion_pio0(wdr_fata); 426 else { 427 if (sc->sc_32bit_io) 428 efa_fata_subregion_pion(wdr_fata, 429 true); 430 else 431 efa_fata_subregion_pion(wdr_fata, 432 false); 433 434 bus_space_subregion(wdr_fata->cmd_iot, 435 wdr_fata->cmd_baseioh, FATA1_PION_OFF_INTST, 436 1, &sc->sc_ports[i].intst[j]); 437 } 438 439 /* No 32-bit register for PIO0 ... */ 440 if (j == 0 && sc->sc_32bit_io) 441 sc->sc_ports[i].mode_ok[j] = false; 442 443 wdr_fata->ctl_ioh = wdr_gayle->ctl_ioh; 444 }; 445 } 446 return true; 447 } 448 449 450 static void 451 efa_fata_subregion_pio0(struct wdc_regs *wdr_fata) 452 { 453 int i; 454 455 for (i = 0; i < WDC_NREG; i++) 456 bus_space_subregion(wdr_fata->cmd_iot, 457 wdr_fata->cmd_baseioh, wdr_offsets_pio0[i], 458 i == 0 ? 4 : 1, &wdr_fata->cmd_iohs[i]); 459 } 460 461 static void 462 efa_fata_subregion_pion(struct wdc_regs *wdr_fata, bool data32) 463 { 464 int i; 465 466 if (data32) 467 bus_space_subregion(wdr_fata->cmd_iot, wdr_fata->cmd_baseioh, 468 FATA1_PION_OFF_DATA32, 8, &wdr_fata->data32ioh); 469 470 for (i = 0; i < WDC_NREG; i++) 471 bus_space_subregion(wdr_fata->cmd_iot, 472 wdr_fata->cmd_baseioh, wdr_offsets_pion[i], 473 i == 0 ? 4 : 1, &wdr_fata->cmd_iohs[i]); 474 } 475 476 static void 477 efa_setup_channel(struct ata_channel *chp) 478 { 479 int drive, chnum; 480 uint8_t mode; 481 struct atac_softc *atac; 482 struct ata_drive_datas *drvp; 483 struct efa_softc *sc; 484 int ipl; 485 #ifdef EFA_DEBUG 486 device_t self; 487 #endif /* EFA_DEBUG */ 488 489 chnum = chp->ch_channel; 490 atac = chp->ch_atac; 491 492 sc = device_private(atac->atac_dev); 493 494 mode = 5; /* start with fastest possible setting */ 495 496 #ifdef EFA_DEBUG 497 self = sc->sc_wdcdev.sc_atac.atac_dev; 498 aprint_normal_dev(self, "efa_setup_channel for ch %d\n", 499 chnum); 500 #endif /* EFA_DEBUG */ 501 502 /* We might be in the middle of something... so raise IPL. */ 503 ipl = splvm(); 504 505 for (drive = 0; drive < 2; drive++) { 506 drvp = &chp->ch_drive[drive]; 507 508 if (drvp->drive_type == ATA_DRIVET_NONE) 509 continue; /* nothing to see here */ 510 511 if (drvp->PIO_cap < mode) 512 mode = drvp->PIO_cap; 513 514 /* TODO: check if sc_ports->mode_ok */ 515 516 #ifdef EFA_DEBUG 517 aprint_normal_dev(self, "drive %d supports %d\n", 518 drive, drvp->PIO_cap); 519 #endif /* EFA_DEBUG */ 520 521 drvp->PIO_mode = mode; 522 } 523 524 /* Change FastATA register set. */ 525 efa_select_regset(sc, chnum, mode); 526 /* re-init shadow regs */ 527 wdc_init_shadow_regs(CHAN_TO_WDC_REGS(&sc->sc_ports[chnum].chan)); 528 529 splx(ipl); 530 } 531 532 static void 533 efa_select_regset(struct efa_softc *sc, int chnum, uint8_t piomode) 534 { 535 struct wdc_softc *wdc; 536 #ifdef EFA_DEBUG 537 device_t self; 538 539 self = sc->sc_wdcdev.sc_atac.atac_dev; 540 #endif /* EFA_DEBUG */ 541 542 wdc = CHAN_TO_WDC(&sc->sc_ports[chnum].chan); 543 wdc->regs[chnum] = sc->sc_ports[chnum].wdr[piomode]; 544 545 #ifdef EFA_DEBUG 546 aprint_normal_dev(self, "switched ch %d to PIO %d\n", 547 chnum, piomode); 548 549 efa_debug_print_regmapping(&wdc->regs[chnum]); 550 #endif /* EFA_DEBUG */ 551 } 552 553 #ifdef EFA_DEBUG 554 static void 555 efa_debug_print_regmapping(struct wdc_regs *wdr_fata) 556 { 557 int i; 558 aprint_normal("base %x->%x", 559 (bus_addr_t) kvtop((void*) wdr_fata->cmd_baseioh), 560 (bus_addr_t) wdr_fata->cmd_baseioh); 561 for (i = 0; i < WDC_NREG; i++) { 562 aprint_normal("reg %x, %x->%x, ", i, 563 (bus_addr_t) kvtop((void*) wdr_fata->cmd_iohs[i]), 564 (bus_addr_t) wdr_fata->cmd_iohs[i]); 565 } 566 aprint_normal("\n"); 567 } 568 #endif /* EFA_DEBUG */ 569 570 /* Compare the values of (status) command register in PIO0, PIO3 sets. */ 571 static bool 572 efa_compare_status(void) 573 { 574 uint8_t cmd0, cmd3; 575 struct bus_space_tag fata_bst; 576 bus_space_tag_t fata_iot; 577 bus_space_handle_t cmd0_ioh, cmd3_ioh; 578 bool rv; 579 580 rv = false; 581 582 fata_bst.base = (bus_addr_t) ztwomap(FATA1_BASE); 583 fata_bst.absm = &amiga_bus_stride_4swap; 584 585 fata_iot = &fata_bst; 586 587 if (bus_space_map(fata_iot, pio_offsets[0], FATA1_CHAN_SIZE, 0, 588 &cmd0_ioh)) 589 return false; 590 if (bus_space_map(fata_iot, pio_offsets[3], FATA1_CHAN_SIZE, 0, 591 &cmd3_ioh)) 592 return false; 593 594 #ifdef EFA_DEBUG 595 aprint_normal("probing for FastATA at %x, %x: ", (bus_addr_t) cmd0_ioh, 596 (bus_addr_t) cmd3_ioh); 597 #endif /* EFA_DEBUG */ 598 599 cmd0 = bus_space_read_1(fata_iot, cmd0_ioh, FATA1_PIO0_OFF_COMMAND); 600 cmd3 = bus_space_read_1(fata_iot, cmd3_ioh, FATA1_PION_OFF_COMMAND); 601 602 if (cmd0 == cmd3) 603 rv = true; 604 605 if ( (cmd0 == 0xFF) || (cmd0 == 0x00) ) { 606 /* Assume there's nothing there... */ 607 rv = false; 608 } 609 610 #ifdef EFA_DEBUG 611 aprint_normal("cmd0 %x, cmd3 %x\n", cmd0, cmd3); 612 #endif /* EFA_DEBUG */ 613 614 bus_space_unmap(fata_iot, pio_offsets[0], FATA1_CHAN_SIZE); 615 bus_space_unmap(fata_iot, pio_offsets[3], FATA1_CHAN_SIZE); 616 617 return rv; 618 } 619 620
Indexes created Tue Sep 30 20:09:53 GMT 2025