efa.c revision 1.4
1 /* $NetBSD: efa.c,v 1.4 2011/10/30 11:10:42 rkujawa Exp $ */ 2 3 /*- 4 * Copyright (c) 2011 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Radoslaw Kujawa. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 19 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 20 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 21 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 22 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 23 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 24 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 25 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 26 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 27 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 28 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 29 * POSSIBILITY OF SUCH DAMAGE. 30 */ 31 32 /* 33 * Driver for FastATA 1200 EIDE controller, manufactured by ELBOX Computer. 34 * 35 * Gayle-related stuff inspired by wdc_amiga.c written by Michael L. Hitch 36 * and Aymeric Vincent. 37 */ 38 39 #include <sys/cdefs.h> 40 41 #include <sys/types.h> 42 #include <sys/param.h> 43 #include <sys/systm.h> 44 #include <sys/malloc.h> 45 #include <sys/device.h> 46 #include <sys/bus.h> 47 #include <sys/proc.h> 48 #include <sys/kernel.h> 49 #include <sys/kthread.h> 50 51 #include <machine/cpu.h> 52 #include <machine/intr.h> 53 #include <sys/bswap.h> 54 55 #include <amiga/amiga/cia.h> 56 #include <amiga/amiga/custom.h> 57 #include <amiga/amiga/device.h> 58 #include <amiga/amiga/gayle.h> 59 #include <amiga/dev/zbusvar.h> 60 61 #include <dev/ata/atavar.h> 62 #include <dev/ic/wdcvar.h> 63 64 #include <amiga/dev/efareg.h> 65 #include <amiga/dev/efavar.h> 66 67 #define EFA_32BIT_IO 1 68 /* #define EFA_NO_INTR 1 */ 69 /* #define EFA_DEBUG 1 */ 70 71 int efa_probe(device_t, cfdata_t, void *); 72 void efa_attach(device_t, device_t, void *); 73 int efa_intr(void *); 74 int efa_intr_soft(void *arg); 75 static void efa_set_opts(struct efa_softc *sc); 76 static bool efa_mapbase(struct efa_softc *sc); 77 static bool efa_mapreg_gayle(struct efa_softc *sc); 78 static bool efa_mapreg_native(struct efa_softc *sc); 79 static void efa_fata_subregion_pio0(struct wdc_regs *wdr_fata); 80 static void efa_fata_subregion_pion(struct wdc_regs *wdr_fata, bool data32); 81 static void efa_setup_channel(struct ata_channel *chp); 82 static void efa_attach_channel(struct efa_softc *sc, int i); 83 static void efa_select_regset(struct efa_softc *sc, int chnum, 84 uint8_t piomode); 85 static void efa_poll_kthread(void *arg); 86 static bool efa_compare_status(void); 87 #ifdef EFA_DEBUG 88 static void efa_debug_print_regmapping(struct wdc_regs *wdr_fata); 89 #endif /* EFA_DEBUG */ 90 91 CFATTACH_DECL_NEW(efa, sizeof(struct efa_softc), 92 efa_probe, efa_attach, NULL, NULL); 93 94 #define PIO_NSUPP 0xFFFFFFFF 95 96 static const bus_addr_t pio_offsets[] = 97 { FATA1_PIO0_OFF, PIO_NSUPP, PIO_NSUPP, FATA1_PIO3_OFF, FATA1_PIO4_OFF, 98 FATA1_PIO5_OFF }; 99 static const unsigned int wdr_offsets_pio0[] = 100 { FATA1_PIO0_OFF_DATA, FATA1_PIO0_OFF_ERROR, FATA1_PIO0_OFF_SECCNT, 101 FATA1_PIO0_OFF_SECTOR, FATA1_PIO0_OFF_CYL_LO, FATA1_PIO0_OFF_CYL_HI, 102 FATA1_PIO0_OFF_SDH, FATA1_PIO0_OFF_COMMAND }; 103 static const unsigned int wdr_offsets_pion[] = 104 { FATA1_PION_OFF_DATA, FATA1_PION_OFF_ERROR, FATA1_PION_OFF_SECCNT, 105 FATA1_PION_OFF_SECTOR, FATA1_PION_OFF_CYL_LO, FATA1_PION_OFF_CYL_HI, 106 FATA1_PION_OFF_SDH, FATA1_PION_OFF_COMMAND }; 107 static const unsigned int wdr_offsets_pion32[] = 108 { FATA1_PION_OFF_DATA32, FATA1_PION_OFF_ERROR, FATA1_PION_OFF_SECCNT, 109 FATA1_PION_OFF_SECTOR, FATA1_PION_OFF_CYL_LO, FATA1_PION_OFF_CYL_HI, 110 FATA1_PION_OFF_SDH, FATA1_PION_OFF_COMMAND }; 111 112 int 113 efa_probe(device_t parent, cfdata_t cfp, void *aux) 114 { 115 /* 116 * FastATA 1200 uses portions of Gayle IDE interface, and efa driver 117 * can't coexist with wdc_amiga. Match "wdc" on an A1200, because 118 * FastATA 1200 does not autoconfigure. 119 */ 120 if (!matchname(aux, "wdc") || !is_a1200()) 121 return(0); 122 123 if (!efa_compare_status()) 124 return(0); 125 126 #ifdef EFA_DEBUG 127 aprint_normal("efa_probe succeeded\n"); 128 #endif /* EFA_DEBUG */ 129 130 return 100; 131 } 132 133 void 134 efa_attach(device_t parent, device_t self, void *aux) 135 { 136 int i; 137 struct efa_softc *sc = device_private(self); 138 139 aprint_normal(": ELBOX FastATA 1200\n"); 140 141 gayle_init(); 142 143 sc->sc_dev = self; 144 145 efa_set_opts(sc); 146 147 if (!efa_mapbase(sc)) { 148 aprint_error_dev(self, "couldn't map base addresses\n"); 149 return; 150 } 151 if (!efa_mapreg_gayle(sc)) { 152 aprint_error_dev(self, "couldn't map Gayle registers\n"); 153 return; 154 } 155 if (!efa_mapreg_native(sc)) { 156 aprint_error_dev(self, "couldn't map FastATA regsters\n"); 157 return; 158 } 159 160 sc->sc_wdcdev.sc_atac.atac_pio_cap = 5; 161 sc->sc_wdcdev.sc_atac.atac_nchannels = FATA1_CHANNELS; 162 sc->sc_wdcdev.sc_atac.atac_set_modes = efa_setup_channel; 163 sc->sc_wdcdev.sc_atac.atac_dev = self; 164 sc->sc_wdcdev.sc_atac.atac_channels = sc->sc_chanlist; 165 sc->sc_wdcdev.sc_atac.atac_cap = ATAC_CAP_DATA16; 166 167 if (sc->sc_32bit_io) 168 sc->sc_wdcdev.sc_atac.atac_cap |= ATAC_CAP_DATA32; 169 170 /* 171 * The following should work for polling mode, but it does not. 172 * if (sc->sc_no_intr) 173 * sc->sc_wdcdev.sc_atac.atac_cap |= ATAC_CAP_NOIRQ; 174 */ 175 176 wdc_allocate_regs(&sc->sc_wdcdev); 177 178 sc->sc_intreg = &gayle.intreq; 179 180 for (i = 0; i < FATA1_CHANNELS; i++) 181 efa_attach_channel(sc, i); 182 183 if (sc->sc_no_intr) { 184 sc->sc_fata_softintr = softint_establish(SOFTINT_BIO, 185 (void (*)(void *))efa_intr_soft, sc); 186 if (sc->sc_fata_softintr == NULL) { 187 aprint_error_dev(self, "couldn't create soft intr\n"); 188 return; 189 } 190 if (kthread_create(PRI_NONE, 0, NULL, efa_poll_kthread, sc, 191 NULL, "efa")) { 192 aprint_error_dev(self, "couldn't create kthread\n"); 193 return; 194 } 195 } else { 196 sc->sc_isr.isr_intr = efa_intr; 197 sc->sc_isr.isr_arg = sc; 198 sc->sc_isr.isr_ipl = 2; 199 add_isr (&sc->sc_isr); 200 gayle.intena |= GAYLE_INT_IDE; 201 } 202 203 } 204 205 static void 206 efa_attach_channel(struct efa_softc *sc, int chnum) 207 { 208 sc->sc_chanlist[chnum] = &sc->sc_ports[chnum].chan; 209 210 sc->sc_ports[chnum].chan.ch_channel = chnum; 211 sc->sc_ports[chnum].chan.ch_atac = &sc->sc_wdcdev.sc_atac; 212 sc->sc_ports[chnum].chan.ch_queue = &sc->sc_ports[chnum].queue; 213 sc->sc_ports[chnum].chan.ch_ndrive = 2; 214 215 if (!sc->sc_32bit_io) 216 efa_select_regset(sc, chnum, 0); /* Start in PIO0. */ 217 else 218 efa_select_regset(sc, chnum, 3); 219 220 wdc_init_shadow_regs(&sc->sc_ports[chnum].chan); 221 222 wdcattach(&sc->sc_ports[chnum].chan); 223 224 #ifdef EFA_DEBUG 225 aprint_normal_dev(sc->sc_dev, "done init for channel %d\n", chnum); 226 #endif 227 228 } 229 230 /* TODO: convert to callout(9) */ 231 static void 232 efa_poll_kthread(void *arg) 233 { 234 struct efa_softc *sc = arg; 235 236 for (;;) { 237 /* TODO: actually check if interrupt status register is set */ 238 softint_schedule(sc->sc_fata_softintr); 239 /* TODO: convert to kpause */ 240 tsleep(arg, PWAIT, "efa_poll", hz); 241 } 242 } 243 244 static void 245 efa_set_opts(struct efa_softc *sc) 246 { 247 #ifdef EFA_32BIT_IO 248 sc->sc_32bit_io = true; 249 #else 250 sc->sc_32bit_io = false; 251 #endif /* EFA_32BIT_IO */ 252 253 #ifdef EFA_NO_INTR 254 sc->sc_no_intr = true; /* XXX: not yet! */ 255 #else 256 sc->sc_no_intr = false; 257 #endif /* EFA_NO_INTR */ 258 259 if (sc->sc_no_intr) 260 aprint_verbose_dev(sc->sc_dev, "hardware interrupt disabled\n"); 261 262 if (sc->sc_32bit_io) 263 aprint_verbose_dev(sc->sc_dev, "32-bit I/O enabled\n"); 264 } 265 266 int 267 efa_intr_soft(void *arg) 268 { 269 int ret = 0; 270 struct efa_softc *sc = (struct efa_softc *)arg; 271 272 /* TODO: check which channel needs servicing */ 273 /* 274 uint8_t fataintreq; 275 fataintreq = bus_space_read_1(sc->sc_ports[0].wdr[piom].cmd_iot, 276 sc->sc_ports[chnum].intst[piom], 0); 277 */ 278 279 ret = wdcintr(&sc->sc_ports[0].chan); 280 ret = wdcintr(&sc->sc_ports[1].chan); 281 282 return ret; 283 } 284 285 int 286 efa_intr(void *arg) 287 { 288 struct efa_softc *sc = (struct efa_softc *)arg; 289 int r1, r2, ret; 290 u_char intreq; 291 292 intreq = *sc->sc_intreg; 293 ret = 0; 294 295 if (intreq & GAYLE_INT_IDE) { 296 gayle.intreq = 0x7c | (intreq & 0x03); 297 /* How to check which channel caused interrupt? 298 * Interrupt status register is not very useful here. */ 299 r1 = wdcintr(&sc->sc_ports[0].chan); 300 r2 = wdcintr(&sc->sc_ports[1].chan); 301 ret = r1 | r2; 302 } 303 304 return ret; 305 } 306 307 static bool 308 efa_mapbase(struct efa_softc *sc) 309 { 310 int i, j; 311 static struct bus_space_tag fata_cmd_iot; 312 static struct bus_space_tag gayle_cmd_iot; 313 314 gayle_cmd_iot.base = (bus_addr_t) ztwomap(GAYLE_IDE_BASE + 2); 315 gayle_cmd_iot.absm = &amiga_bus_stride_4swap; 316 fata_cmd_iot.base = (bus_addr_t) ztwomap(FATA1_BASE); 317 fata_cmd_iot.absm = &amiga_bus_stride_4swap; 318 319 #ifdef EFA_DEBUG 320 aprint_normal_dev(sc->sc_dev, "Gayle %x -> %x, FastATA %x -> %x\n", 321 GAYLE_IDE_BASE, gayle_cmd_iot.base, FATA1_BASE, fata_cmd_iot.base); 322 #endif 323 324 if (!gayle_cmd_iot.base) 325 return false; 326 if (!fata_cmd_iot.base) 327 return false; 328 329 sc->sc_gayle_wdc_regs.cmd_iot = &gayle_cmd_iot; 330 sc->sc_gayle_wdc_regs.ctl_iot = &gayle_cmd_iot; 331 332 for (i = 0; i < FATA1_CHANNELS; i++) { 333 for (j = 0; j < PIO_COUNT; j++) { 334 sc->sc_ports[i].wdr[j].cmd_iot = &fata_cmd_iot; 335 sc->sc_ports[i].wdr[j].data32iot = &fata_cmd_iot; 336 sc->sc_ports[i].wdr[j].ctl_iot = &gayle_cmd_iot; 337 } 338 } 339 340 return true; 341 } 342 343 344 /* Gayle IDE register mapping, we need it anyway. */ 345 static bool 346 efa_mapreg_gayle(struct efa_softc *sc) 347 { 348 int i; 349 350 struct wdc_regs *wdr = &sc->sc_gayle_wdc_regs; 351 352 if (bus_space_map(wdr->cmd_iot, 0, 0x40, 0, 353 &wdr->cmd_baseioh)) { 354 return false; 355 } 356 357 for (i = 0; i < WDC_NREG; i++) { 358 if (bus_space_subregion(wdr->cmd_iot, 359 wdr->cmd_baseioh, i, i == 0 ? 4 : 1, 360 &wdr->cmd_iohs[i]) != 0) { 361 362 bus_space_unmap(wdr->cmd_iot, 363 wdr->cmd_baseioh, 0x40); 364 return false; 365 } 366 } 367 368 if (bus_space_subregion(wdr->cmd_iot, 369 wdr->cmd_baseioh, 0x406, 1, &wdr->ctl_ioh)) 370 return false; 371 372 return true; 373 } 374 375 /* Native FastATA register mapping, suitable for PIO modes 0 to 5. */ 376 static bool 377 efa_mapreg_native(struct efa_softc *sc) 378 { 379 int i,j; 380 struct wdc_regs *wdr_gayle = &sc->sc_gayle_wdc_regs; 381 struct wdc_regs *wdr_fata; 382 383 for (i = 0; i < FATA1_CHANNELS; i++) { 384 385 for (j = 0; j < PIO_COUNT; j++) { 386 387 wdr_fata = &sc->sc_ports[i].wdr[j]; 388 sc->sc_ports[i].mode_ok[j] = false; 389 390 if (pio_offsets[j] == PIO_NSUPP) { 391 #ifdef EFA_DEBUG 392 aprint_normal_dev(sc->sc_dev, 393 "Skipping mapping for PIO mode %x\n", j); 394 #endif 395 continue; 396 } 397 398 if (bus_space_map(wdr_fata->cmd_iot, 399 pio_offsets[j] + FATA1_CHAN_SIZE * i, 400 FATA1_CHAN_SIZE, 0, &wdr_fata->cmd_baseioh)) { 401 return false; 402 } 403 #ifdef EFA_DEBUG 404 aprint_normal_dev(sc->sc_dev, 405 "Chan %x PIO mode %x mapped %x -> %x\n", 406 i, j, (bus_addr_t) kvtop((void*) 407 wdr_fata->cmd_baseioh), (unsigned int) 408 wdr_fata->cmd_baseioh); 409 #endif 410 411 sc->sc_ports[i].mode_ok[j] = true; 412 413 if (j == 0) 414 efa_fata_subregion_pio0(wdr_fata); 415 else { 416 if (sc->sc_32bit_io) 417 efa_fata_subregion_pion(wdr_fata, 418 true); 419 else 420 efa_fata_subregion_pion(wdr_fata, 421 false); 422 423 bus_space_subregion(wdr_fata->cmd_iot, 424 wdr_fata->cmd_baseioh, FATA1_PION_OFF_INTST, 425 1, &sc->sc_ports[i].intst[j]); 426 } 427 428 /* No 32-bit register for PIO0 ... */ 429 if (j == 0 && sc->sc_32bit_io) 430 sc->sc_ports[i].mode_ok[j] = false; 431 432 wdr_fata->ctl_ioh = wdr_gayle->ctl_ioh; 433 }; 434 } 435 return true; 436 } 437 438 439 static void 440 efa_fata_subregion_pio0(struct wdc_regs *wdr_fata) 441 { 442 443 bus_space_subregion(wdr_fata->cmd_iot, wdr_fata->cmd_baseioh, 444 FATA1_PIO0_OFF_DATA, 4, &wdr_fata->cmd_iohs[wd_data]); 445 bus_space_subregion(wdr_fata->cmd_iot, wdr_fata->cmd_baseioh, 446 FATA1_PIO0_OFF_ERROR, 1, &wdr_fata->cmd_iohs[wd_error]); 447 bus_space_subregion(wdr_fata->cmd_iot, wdr_fata->cmd_baseioh, 448 FATA1_PIO0_OFF_SECCNT, 1, &wdr_fata->cmd_iohs[wd_seccnt]); 449 bus_space_subregion(wdr_fata->cmd_iot, wdr_fata->cmd_baseioh, 450 FATA1_PIO0_OFF_SECTOR, 1, &wdr_fata->cmd_iohs[wd_sector]); 451 bus_space_subregion(wdr_fata->cmd_iot, wdr_fata->cmd_baseioh, 452 FATA1_PIO0_OFF_CYL_LO, 1, &wdr_fata->cmd_iohs[wd_cyl_lo]); 453 bus_space_subregion(wdr_fata->cmd_iot, wdr_fata->cmd_baseioh, 454 FATA1_PIO0_OFF_CYL_HI, 1, &wdr_fata->cmd_iohs[wd_cyl_hi]); 455 bus_space_subregion(wdr_fata->cmd_iot, wdr_fata->cmd_baseioh, 456 FATA1_PIO0_OFF_SDH, 1, &wdr_fata->cmd_iohs[wd_sdh]); 457 bus_space_subregion(wdr_fata->cmd_iot, wdr_fata->cmd_baseioh, 458 FATA1_PIO0_OFF_COMMAND, 1, &wdr_fata->cmd_iohs[wd_command]); 459 } 460 461 static void 462 efa_fata_subregion_pion(struct wdc_regs *wdr_fata, bool data32) 463 { 464 if (data32) 465 bus_space_subregion(wdr_fata->cmd_iot, wdr_fata->cmd_baseioh, 466 FATA1_PION_OFF_DATA32, 8, &wdr_fata->data32ioh); 467 468 bus_space_subregion(wdr_fata->cmd_iot, wdr_fata->cmd_baseioh, 469 FATA1_PION_OFF_DATA, 4, &wdr_fata->cmd_iohs[wd_data]); 470 bus_space_subregion(wdr_fata->cmd_iot, wdr_fata->cmd_baseioh, 471 FATA1_PION_OFF_ERROR, 1, &wdr_fata->cmd_iohs[wd_error]); 472 bus_space_subregion(wdr_fata->cmd_iot, wdr_fata->cmd_baseioh, 473 FATA1_PION_OFF_SECCNT, 1, &wdr_fata->cmd_iohs[wd_seccnt]); 474 bus_space_subregion(wdr_fata->cmd_iot, wdr_fata->cmd_baseioh, 475 FATA1_PION_OFF_SECTOR, 1, &wdr_fata->cmd_iohs[wd_sector]); 476 bus_space_subregion(wdr_fata->cmd_iot, wdr_fata->cmd_baseioh, 477 FATA1_PION_OFF_CYL_LO, 1, &wdr_fata->cmd_iohs[wd_cyl_lo]); 478 bus_space_subregion(wdr_fata->cmd_iot, wdr_fata->cmd_baseioh, 479 FATA1_PION_OFF_CYL_HI, 1, &wdr_fata->cmd_iohs[wd_cyl_hi]); 480 bus_space_subregion(wdr_fata->cmd_iot, wdr_fata->cmd_baseioh, 481 FATA1_PION_OFF_SDH, 1, &wdr_fata->cmd_iohs[wd_sdh]); 482 bus_space_subregion(wdr_fata->cmd_iot, wdr_fata->cmd_baseioh, 483 FATA1_PION_OFF_COMMAND, 1, &wdr_fata->cmd_iohs[wd_command]); 484 } 485 486 static void 487 efa_setup_channel(struct ata_channel *chp) 488 { 489 int drive, chnum; 490 uint8_t mode; 491 struct atac_softc *atac; 492 struct ata_drive_datas *drvp; 493 struct efa_softc *sc; 494 int ipl; 495 496 chnum = chp->ch_channel; 497 atac = chp->ch_atac; 498 sc = device_private(atac->atac_dev); 499 500 mode = 5; /* start with fastest possible setting */ 501 502 #ifdef EFA_DEBUG 503 aprint_normal_dev(sc->sc_dev, "efa_setup_channel for ch %d\n", 504 chnum); 505 #endif /* EFA_DEBUG */ 506 507 /* We might be in the middle of something... so raise IPL. */ 508 ipl = splvm(); 509 510 for (drive = 0; drive < 2; drive++) { 511 drvp = &chp->ch_drive[drive]; 512 513 if ((drvp->drive_flags & DRIVE) == 0) 514 continue; /* nothing to see here */ 515 516 if (drvp->PIO_cap < mode); 517 mode = drvp->PIO_cap; 518 519 /* TODO: check if sc_ports->mode_ok */ 520 521 #ifdef EFA_DEBUG 522 aprint_normal_dev(sc->sc_dev, "drive %d supports %d\n", 523 drive, drvp->PIO_cap); 524 #endif /* EFA_DEBUG */ 525 526 drvp->PIO_mode = mode; 527 } 528 529 /* Change FastATA register set. */ 530 efa_select_regset(sc, chnum, mode); 531 /* re-init shadow regs */ 532 wdc_init_shadow_regs(&sc->sc_ports[chnum].chan); 533 534 splx(ipl); 535 } 536 537 static void 538 efa_select_regset(struct efa_softc *sc, int chnum, uint8_t piomode) 539 { 540 struct wdc_softc *wdc; 541 542 wdc = CHAN_TO_WDC(&sc->sc_ports[chnum].chan); 543 wdc->regs[chnum] = sc->sc_ports[chnum].wdr[piomode]; 544 545 #ifdef EFA_DEBUG 546 aprint_normal_dev(sc->sc_dev, "switched ch %d to PIO %d\n", 547 chnum, piomode); 548 549 efa_debug_print_regmapping(&wdc->regs[chnum]); 550 #endif /* EFA_DEBUG */ 551 } 552 553 #ifdef EFA_DEBUG 554 static void 555 efa_debug_print_regmapping(struct wdc_regs *wdr_fata) 556 { 557 int i; 558 aprint_normal("base %x->%x", 559 (bus_addr_t) kvtop((void*) wdr_fata->cmd_baseioh), 560 (bus_addr_t) wdr_fata->cmd_baseioh); 561 for (i = 0; i < WDC_NREG; i++) { 562 aprint_normal("reg %x, %x->%x, ", i, 563 (bus_addr_t) kvtop((void*) wdr_fata->cmd_iohs[i]), 564 (bus_addr_t) wdr_fata->cmd_iohs[i]); 565 } 566 aprint_normal("\n"); 567 } 568 #endif /* EFA_DEBUG */ 569 570 /* Compare the values of (status) command register in PIO0, PIO3 sets. */ 571 static bool 572 efa_compare_status(void) 573 { 574 uint8_t cmd0, cmd3; 575 struct bus_space_tag fata_bst; 576 bus_space_tag_t fata_iot; 577 bus_space_handle_t cmd0_ioh, cmd3_ioh; 578 bool rv; 579 580 rv = false; 581 582 fata_bst.base = (bus_addr_t) ztwomap(FATA1_BASE); 583 fata_bst.absm = &amiga_bus_stride_4swap; 584 585 fata_iot = &fata_bst; 586 587 if (bus_space_map(fata_iot, pio_offsets[0], FATA1_CHAN_SIZE, 0, 588 &cmd0_ioh)) 589 return false; 590 if (bus_space_map(fata_iot, pio_offsets[3], FATA1_CHAN_SIZE, 0, 591 &cmd3_ioh)) 592 return false; 593 594 #ifdef EFA_DEBUG 595 aprint_normal("probing for FastATA at %x, %x: ", (bus_addr_t) cmd0_ioh, 596 (bus_addr_t) cmd3_ioh); 597 #endif /* EFA_DEBUG */ 598 599 cmd0 = bus_space_read_1(fata_iot, cmd0_ioh, FATA1_PIO0_OFF_COMMAND); 600 cmd3 = bus_space_read_1(fata_iot, cmd3_ioh, FATA1_PION_OFF_COMMAND); 601 602 if (cmd0 == cmd3) 603 rv = true; 604 605 if ( (cmd0 == 0xFF) || (cmd0 == 0x00) ) { 606 /* Assume there's nothing there... */ 607 rv = false; 608 } 609 610 #ifdef EFA_DEBUG 611 aprint_normal("cmd0 %x, cmd3 %x\n", cmd0, cmd3); 612 #endif /* EFA_DEBUG */ 613 614 bus_space_unmap(fata_iot, pio_offsets[0], FATA1_CHAN_SIZE); 615 bus_space_unmap(fata_iot, pio_offsets[3], FATA1_CHAN_SIZE); 616 617 return rv; 618 } 619 620
Indexes created Tue Sep 30 20:09:53 GMT 2025