flsc.c revision 1.14.10.1
1 /* $NetBSD: flsc.c,v 1.14.10.1 1997/08/27 21:45:18 thorpej Exp $ */ 2 3 /* 4 * Copyright (c) 1995 Daniel Widenfalk 5 * Copyright (c) 1994 Christian E. Hopps 6 * Copyright (c) 1982, 1990 The Regents of the University of California. 7 * All rights reserved. 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions 11 * are met: 12 * 1. Redistributions of source code must retain the above copyright 13 * notice, this list of conditions and the following disclaimer. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 3. All advertising materials mentioning features or use of this software 18 * must display the following acknowledgement: 19 * This product includes software developed by the University of 20 * California, Berkeley and its contributors. 21 * 4. Neither the name of the University nor the names of its contributors 22 * may be used to endorse or promote products derived from this software 23 * without specific prior written permission. 24 * 25 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 26 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 27 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 28 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 29 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 30 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 31 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 32 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 33 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 34 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 35 * SUCH DAMAGE. 36 * 37 * @(#)dma.c 38 */ 39 40 #include <sys/param.h> 41 #include <sys/systm.h> 42 #include <sys/kernel.h> 43 #include <sys/device.h> 44 #include <dev/scsipi/scsi_all.h> 45 #include <dev/scsipi/scsipi_all.h> 46 #include <dev/scsipi/scsiconf.h> 47 #include <vm/vm.h> 48 #include <vm/vm_kern.h> 49 #include <vm/vm_page.h> 50 #include <machine/pmap.h> 51 #include <amiga/amiga/custom.h> 52 #include <amiga/amiga/cc.h> 53 #include <amiga/amiga/device.h> 54 #include <amiga/amiga/isr.h> 55 #include <amiga/dev/sfasreg.h> 56 #include <amiga/dev/sfasvar.h> 57 #include <amiga/dev/zbusvar.h> 58 #include <amiga/dev/flscreg.h> 59 #include <amiga/dev/flscvar.h> 60 61 void flscattach __P((struct device *, struct device *, void *)); 62 int flscmatch __P((struct device *, struct cfdata *, void *)); 63 64 struct scsipi_adapter flsc_scsiswitch = { 65 sfas_scsicmd, 66 sfas_minphys, 67 0, /* no lun support */ 68 0, /* no lun support */ 69 }; 70 71 struct scsipi_device flsc_scsidev = { 72 NULL, /* use default error handler */ 73 NULL, /* do not have a start functio */ 74 NULL, /* have no async handler */ 75 NULL, /* Use default done routine */ 76 }; 77 78 struct cfattach flsc_ca = { 79 sizeof(struct flsc_softc), flscmatch, flscattach 80 }; 81 82 struct cfdriver flsc_cd = { 83 NULL, "flsc", DV_DULL, NULL, 0 84 }; 85 86 int flsc_intr __P((void *)); 87 void flsc_set_dma_adr __P((struct sfas_softc *sc, vm_offset_t ptr)); 88 void flsc_set_dma_tc __P((struct sfas_softc *sc, unsigned int len)); 89 void flsc_set_dma_mode __P((struct sfas_softc *sc, int mode)); 90 int flsc_setup_dma __P((struct sfas_softc *sc, vm_offset_t ptr, int len, 91 int mode)); 92 int flsc_build_dma_chain __P((struct sfas_softc *sc, 93 struct sfas_dma_chain *chain, void *p, int l)); 94 int flsc_need_bump __P((struct sfas_softc *sc, vm_offset_t ptr, int len)); 95 void flsc_led __P((struct sfas_softc *sc, int mode)); 96 97 /* 98 * if we are an Advanced Systems & Software FastlaneZ3 99 */ 100 int 101 flscmatch(pdp, cfp, auxp) 102 struct device *pdp; 103 struct cfdata *cfp; 104 void *auxp; 105 { 106 struct zbus_args *zap; 107 108 if (!is_a4000() && !is_a3000()) 109 return(0); 110 111 zap = auxp; 112 if (zap->manid == 0x2140 && zap->prodid == 11 113 && iszthreepa(zap->pa)) 114 return(1); 115 116 return(0); 117 } 118 119 void 120 flscattach(pdp, dp, auxp) 121 struct device *pdp; 122 struct device *dp; 123 void *auxp; 124 { 125 struct flsc_softc *sc; 126 struct zbus_args *zap; 127 flsc_regmap_p rp; 128 vu_char *fas; 129 130 zap = auxp; 131 fas = &((vu_char *)zap->va)[0x1000001]; 132 133 sc = (struct flsc_softc *)dp; 134 rp = &sc->sc_regmap; 135 136 rp->FAS216.sfas_tc_low = &fas[0x00]; 137 rp->FAS216.sfas_tc_mid = &fas[0x04]; 138 rp->FAS216.sfas_fifo = &fas[0x08]; 139 rp->FAS216.sfas_command = &fas[0x0C]; 140 rp->FAS216.sfas_dest_id = &fas[0x10]; 141 rp->FAS216.sfas_timeout = &fas[0x14]; 142 rp->FAS216.sfas_syncper = &fas[0x18]; 143 rp->FAS216.sfas_syncoff = &fas[0x1C]; 144 rp->FAS216.sfas_config1 = &fas[0x20]; 145 rp->FAS216.sfas_clkconv = &fas[0x24]; 146 rp->FAS216.sfas_test = &fas[0x28]; 147 rp->FAS216.sfas_config2 = &fas[0x2C]; 148 rp->FAS216.sfas_config3 = &fas[0x30]; 149 rp->FAS216.sfas_tc_high = &fas[0x38]; 150 rp->FAS216.sfas_fifo_bot = &fas[0x3C]; 151 rp->hardbits = &fas[0x40]; 152 rp->clear = &fas[0x80]; 153 rp->dmabase = zap->va; 154 155 sc->sc_softc.sc_fas = (sfas_regmap_p)rp; 156 sc->sc_softc.sc_spec = &sc->sc_specific; 157 158 sc->sc_softc.sc_led = flsc_led; 159 160 sc->sc_softc.sc_setup_dma = flsc_setup_dma; 161 sc->sc_softc.sc_build_dma_chain = flsc_build_dma_chain; 162 sc->sc_softc.sc_need_bump = flsc_need_bump; 163 164 sc->sc_softc.sc_clock_freq = 40; /* FastlaneZ3 runs at 40MHz */ 165 sc->sc_softc.sc_timeout = 250; /* Set default timeout to 250ms */ 166 sc->sc_softc.sc_config_flags = 0; /* No config flags yet */ 167 sc->sc_softc.sc_host_id = 7; /* Should check the jumpers */ 168 169 sc->sc_specific.portbits = 0xA0 | FLSC_PB_EDI | FLSC_PB_ESI; 170 sc->sc_specific.hardbits = *rp->hardbits; 171 172 sc->sc_softc.sc_bump_sz = NBPG; 173 sc->sc_softc.sc_bump_pa = 0x0; 174 175 sfasinitialize((struct sfas_softc *)sc); 176 177 sc->sc_softc.sc_link.scsipi_scsi.channel = SCSI_CHANNEL_ONLY_ONE; 178 sc->sc_softc.sc_link.adapter_softc = sc; 179 sc->sc_softc.sc_link.scsipi_scsi.adapter_target = sc->sc_softc.sc_host_id; 180 sc->sc_softc.sc_link.adapter = &flsc_scsiswitch; 181 sc->sc_softc.sc_link.device = &flsc_scsidev; 182 sc->sc_softc.sc_link.openings = 1; 183 sc->sc_softc.sc_link.scsipi_scsi.max_target = 7; 184 sc->sc_softc.sc_link.type = BUS_SCSI; 185 186 sc->sc_softc.sc_isr.isr_intr = flsc_intr; 187 sc->sc_softc.sc_isr.isr_arg = &sc->sc_softc; 188 sc->sc_softc.sc_isr.isr_ipl = 2; 189 add_isr(&sc->sc_softc.sc_isr); 190 191 /* We don't want interrupt until we're initialized! */ 192 *rp->hardbits = sc->sc_specific.portbits; 193 194 printf("\n"); 195 196 /* attach all scsi units on us */ 197 config_found(dp, &sc->sc_softc.sc_link, scsiprint); 198 } 199 200 int 201 flsc_intr(arg) 202 void *arg; 203 { 204 struct sfas_softc *dev = arg; 205 flsc_regmap_p rp; 206 struct flsc_specific *flspec; 207 int quickints; 208 u_char hb; 209 210 flspec = dev->sc_spec; 211 rp = (flsc_regmap_p)dev->sc_fas; 212 hb = *rp->hardbits; 213 214 if (hb & FLSC_HB_IACT) 215 return(0); 216 217 flspec->hardbits = hb; 218 if ((hb & FLSC_HB_CREQ) && 219 !(hb & FLSC_HB_MINT) && 220 (*rp->FAS216.sfas_status & SFAS_STAT_INTERRUPT_PENDING)) { 221 quickints = 16; 222 do { 223 dev->sc_status = *rp->FAS216.sfas_status; 224 dev->sc_interrupt = *rp->FAS216.sfas_interrupt; 225 226 if (dev->sc_interrupt & SFAS_INT_RESELECTED) { 227 dev->sc_resel[0] = *rp->FAS216.sfas_fifo; 228 dev->sc_resel[1] = *rp->FAS216.sfas_fifo; 229 } 230 sfasintr(dev); 231 232 } while((*rp->FAS216.sfas_status & SFAS_STAT_INTERRUPT_PENDING) 233 && --quickints); 234 } 235 236 /* Reset fastlane interrupt bits */ 237 *rp->hardbits = flspec->portbits & ~FLSC_PB_INT_BITS; 238 *rp->hardbits = flspec->portbits; 239 240 return(1); 241 } 242 243 /* Load transfer adress into dma register */ 244 void 245 flsc_set_dma_adr(sc, ptr) 246 struct sfas_softc *sc; 247 vm_offset_t ptr; 248 { 249 flsc_regmap_p rp; 250 unsigned int *p; 251 unsigned int d; 252 253 rp = (flsc_regmap_p)sc->sc_fas; 254 255 d = (unsigned int)ptr; 256 p = (unsigned int *)((d & 0xFFFFFF) + (int)rp->dmabase); 257 258 *rp->clear=0; 259 *p = d; 260 } 261 262 /* Set DMA transfer counter */ 263 void 264 flsc_set_dma_tc(sc, len) 265 struct sfas_softc *sc; 266 unsigned int len; 267 { 268 *sc->sc_fas->sfas_tc_low = len; len >>= 8; 269 *sc->sc_fas->sfas_tc_mid = len; len >>= 8; 270 *sc->sc_fas->sfas_tc_high = len; 271 } 272 273 /* Set DMA mode */ 274 void 275 flsc_set_dma_mode(sc, mode) 276 struct sfas_softc *sc; 277 int mode; 278 { 279 struct flsc_specific *spec; 280 281 spec = sc->sc_spec; 282 283 spec->portbits = (spec->portbits & ~FLSC_PB_DMA_BITS) | mode; 284 *((flsc_regmap_p)sc->sc_fas)->hardbits = spec->portbits; 285 } 286 287 /* Initialize DMA for transfer */ 288 int 289 flsc_setup_dma(sc, ptr, len, mode) 290 struct sfas_softc *sc; 291 vm_offset_t ptr; 292 int len; 293 int mode; 294 { 295 int retval; 296 297 retval = 0; 298 299 switch(mode) { 300 case SFAS_DMA_READ: 301 case SFAS_DMA_WRITE: 302 flsc_set_dma_adr(sc, ptr); 303 if (mode == SFAS_DMA_READ) 304 flsc_set_dma_mode(sc,FLSC_PB_ENABLE_DMA | FLSC_PB_DMA_READ); 305 else 306 flsc_set_dma_mode(sc,FLSC_PB_ENABLE_DMA | FLSC_PB_DMA_WRITE); 307 308 flsc_set_dma_tc(sc, len); 309 break; 310 311 case SFAS_DMA_CLEAR: 312 default: 313 flsc_set_dma_mode(sc, FLSC_PB_DISABLE_DMA); 314 flsc_set_dma_adr(sc, 0); 315 316 retval = (*sc->sc_fas->sfas_tc_high << 16) | 317 (*sc->sc_fas->sfas_tc_mid << 8) | 318 *sc->sc_fas->sfas_tc_low; 319 320 flsc_set_dma_tc(sc, 0); 321 break; 322 } 323 324 return(retval); 325 } 326 327 /* Check if address and len is ok for DMA transfer */ 328 int 329 flsc_need_bump(sc, ptr, len) 330 struct sfas_softc *sc; 331 vm_offset_t ptr; 332 int len; 333 { 334 int p; 335 336 if (((int)ptr & 0x03) || (len & 0x03)) { 337 if (len < 256) 338 p = len; 339 else 340 p = 256; 341 } else 342 p = 0; 343 344 return(p); 345 } 346 347 /* Interrupt driven routines */ 348 int 349 flsc_build_dma_chain(sc, chain, p, l) 350 struct sfas_softc *sc; 351 struct sfas_dma_chain *chain; 352 void *p; 353 int l; 354 { 355 vm_offset_t pa, lastpa; 356 char *ptr; 357 int len, prelen, max_t, n; 358 359 if (l == 0) 360 return(0); 361 362 #define set_link(n, p, l, f)\ 363 do { chain[n].ptr = (p); chain[n].len = (l); chain[n++].flg = (f); } while(0) 364 365 n = 0; 366 367 if (l < 512) 368 set_link(n, (vm_offset_t)p, l, SFAS_CHAIN_BUMP); 369 else if ((p >= (void *)0xFF000000) 370 #if defined(M68040) || defined(M68060) 371 && ((mmutype == MMU_68040) && (p >= (void *)0xFFFC0000)) 372 #endif 373 ) { 374 while(l != 0) { 375 len = ((l > sc->sc_bump_sz) ? sc->sc_bump_sz : l); 376 377 set_link(n, (vm_offset_t)p, len, SFAS_CHAIN_BUMP); 378 379 p += len; 380 l -= len; 381 } 382 } else { 383 ptr = p; 384 len = l; 385 386 pa = kvtop(ptr); 387 prelen = ((int)ptr & 0x03); 388 389 if (prelen) { 390 prelen = 4-prelen; 391 set_link(n, (vm_offset_t)ptr, prelen, SFAS_CHAIN_BUMP); 392 ptr += prelen; 393 len -= prelen; 394 } 395 396 lastpa = 0; 397 while(len > 3) { 398 pa = kvtop(ptr); 399 max_t = NBPG - (pa & PGOFSET); 400 if (max_t > len) 401 max_t = len; 402 403 max_t &= ~3; 404 405 if (lastpa == pa) 406 sc->sc_chain[n-1].len += max_t; 407 else 408 set_link(n, pa, max_t, SFAS_CHAIN_DMA); 409 410 lastpa = pa+max_t; 411 412 ptr += max_t; 413 len -= max_t; 414 } 415 416 if (len) 417 set_link(n, (vm_offset_t)ptr, len, SFAS_CHAIN_BUMP); 418 } 419 420 return(n); 421 } 422 423 /* Turn on/off led */ 424 void 425 flsc_led(sc, mode) 426 struct sfas_softc *sc; 427 int mode; 428 { 429 struct flsc_specific *spec; 430 flsc_regmap_p rp; 431 432 spec = sc->sc_spec; 433 rp = (flsc_regmap_p)sc->sc_fas; 434 435 if (mode) { 436 sc->sc_led_status++; 437 438 spec->portbits |= FLSC_PB_LED; 439 *rp->hardbits = spec->portbits; 440 } else { 441 if (sc->sc_led_status) 442 sc->sc_led_status--; 443 444 if (!sc->sc_led_status) { 445 spec->portbits &= ~FLSC_PB_LED; 446 *rp->hardbits = spec->portbits; 447 } 448 } 449 } 450
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