flsc.c revision 1.14.10.2
1 /* $NetBSD: flsc.c,v 1.14.10.2 1997/10/14 08:26:35 thorpej Exp $ */ 2 3 /* 4 * Copyright (c) 1997 Michael L. Hitch 5 * Copyright (c) 1995 Daniel Widenfalk 6 * Copyright (c) 1994 Christian E. Hopps 7 * Copyright (c) 1982, 1990 The Regents of the University of California. 8 * All rights reserved. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 3. All advertising materials mentioning features or use of this software 19 * must display the following acknowledgement: 20 * This product includes software developed by Daniel Widenfalk 21 * and Michael L. Hitch. 22 * 4. Neither the name of the University nor the names of its contributors 23 * may be used to endorse or promote products derived from this software 24 * without specific prior written permission. 25 * 26 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 27 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 28 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 29 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 30 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 31 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 32 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 33 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 34 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 35 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 36 * SUCH DAMAGE. 37 */ 38 39 /* 40 * Initial amiga Fastlane driver by Daniel Widenfalk. Conversion to 41 * 53c9x MI driver by Michael L. Hitch (mhitch (at) montana.edu). 42 */ 43 44 #include <sys/types.h> 45 #include <sys/param.h> 46 #include <sys/systm.h> 47 #include <sys/kernel.h> 48 #include <sys/errno.h> 49 #include <sys/ioctl.h> 50 #include <sys/device.h> 51 #include <sys/buf.h> 52 #include <sys/proc.h> 53 #include <sys/user.h> 54 #include <sys/queue.h> 55 56 #include <dev/scsipi/scsi_all.h> 57 #include <dev/scsipi/scsipi_all.h> 58 #include <dev/scsipi/scsiconf.h> 59 #include <dev/scsipi/scsi_message.h> 60 61 #include <machine/cpu.h> 62 #include <machine/param.h> 63 64 #include <dev/ic/ncr53c9xreg.h> 65 #include <dev/ic/ncr53c9xvar.h> 66 67 #include <amiga/amiga/isr.h> 68 #include <amiga/dev/flscvar.h> 69 #include <amiga/dev/zbusvar.h> 70 71 void flscattach __P((struct device *, struct device *, void *)); 72 int flscmatch __P((struct device *, struct cfdata *, void *)); 73 74 /* Linkup to the rest of the kernel */ 75 struct cfattach flsc_ca = { 76 sizeof(struct flsc_softc), flscmatch, flscattach 77 }; 78 79 struct cfdriver flsc_cd = { 80 NULL, "flsc", DV_DULL 81 }; 82 83 struct scsipi_adapter flsc_switch = { 84 ncr53c9x_scsi_cmd, 85 minphys, /* no max at this level; handled by DMA code */ 86 NULL, 87 NULL, 88 }; 89 90 struct scsipi_device flsc_dev = { 91 NULL, /* Use default error handler */ 92 NULL, /* have a queue, served by this */ 93 NULL, /* have no async handler */ 94 NULL, /* Use default 'done' routine */ 95 }; 96 97 /* 98 * Functions and the switch for the MI code. 99 */ 100 u_char flsc_read_reg __P((struct ncr53c9x_softc *, int)); 101 void flsc_write_reg __P((struct ncr53c9x_softc *, int, u_char)); 102 int flsc_dma_isintr __P((struct ncr53c9x_softc *)); 103 void flsc_dma_reset __P((struct ncr53c9x_softc *)); 104 int flsc_dma_intr __P((struct ncr53c9x_softc *)); 105 int flsc_dma_setup __P((struct ncr53c9x_softc *, caddr_t *, 106 size_t *, int, size_t *)); 107 void flsc_dma_go __P((struct ncr53c9x_softc *)); 108 void flsc_dma_stop __P((struct ncr53c9x_softc *)); 109 int flsc_dma_isactive __P((struct ncr53c9x_softc *)); 110 void flsc_clear_latched_intr __P((struct ncr53c9x_softc *)); 111 112 struct ncr53c9x_glue flsc_glue = { 113 flsc_read_reg, 114 flsc_write_reg, 115 flsc_dma_isintr, 116 flsc_dma_reset, 117 flsc_dma_intr, 118 flsc_dma_setup, 119 flsc_dma_go, 120 flsc_dma_stop, 121 flsc_dma_isactive, 122 flsc_clear_latched_intr, 123 }; 124 125 /* Maximum DMA transfer length to reduce impact on high-speed serial input */ 126 u_long flsc_max_dma = 1024; 127 extern int ser_open_speed; 128 129 extern int ncr53c9x_debug; 130 extern u_long scsi_nosync; 131 extern int shift_nosync; 132 133 /* 134 * if we are an Advanced Systems & Software FastlaneZ3 135 */ 136 int 137 flscmatch(parent, cf, aux) 138 struct device *parent; 139 struct cfdata *cf; 140 void *aux; 141 { 142 struct zbus_args *zap; 143 144 if (!is_a4000() && !is_a3000()) 145 return(0); 146 147 zap = aux; 148 if (zap->manid == 0x2140 && zap->prodid == 11 149 && iszthreepa(zap->pa)) 150 return(1); 151 152 return(0); 153 } 154 155 /* 156 * Attach this instance, and then all the sub-devices 157 */ 158 void 159 flscattach(parent, self, aux) 160 struct device *parent, *self; 161 void *aux; 162 { 163 struct flsc_softc *fsc = (void *)self; 164 struct ncr53c9x_softc *sc = &fsc->sc_ncr53c9x; 165 struct zbus_args *zap; 166 167 /* 168 * Set up the glue for MI code early; we use some of it here. 169 */ 170 sc->sc_glue = &flsc_glue; 171 172 /* 173 * Save the regs 174 */ 175 zap = aux; 176 fsc->sc_dmabase = (volatile u_char *)zap->va; 177 fsc->sc_reg = &((volatile u_char *)zap->va)[0x1000001]; 178 179 sc->sc_freq = 40; /* Clocked at 40Mhz */ 180 181 printf(": address %p", fsc->sc_reg); 182 183 sc->sc_id = 7; 184 185 /* 186 * It is necessary to try to load the 2nd config register here, 187 * to find out what rev the flsc chip is, else the flsc_reset 188 * will not set up the defaults correctly. 189 */ 190 sc->sc_cfg1 = sc->sc_id | NCRCFG1_PARENB; 191 sc->sc_cfg2 = NCRCFG2_SCSI2 | NCRCFG2_FE; 192 sc->sc_cfg3 = 0x08 /*FCLK*/ | NCRESPCFG3_FSCSI | NCRESPCFG3_CDB; 193 sc->sc_rev = NCR_VARIANT_FAS216; 194 195 /* 196 * This is the value used to start sync negotiations 197 * Note that the NCR register "SYNCTP" is programmed 198 * in "clocks per byte", and has a minimum value of 4. 199 * The SCSI period used in negotiation is one-fourth 200 * of the time (in nanoseconds) needed to transfer one byte. 201 * Since the chip's clock is given in MHz, we have the following 202 * formula: 4 * period = (1000 / freq) * 4 203 */ 204 sc->sc_minsync = 1000 / sc->sc_freq; 205 206 if (((scsi_nosync >> shift_nosync) & 0xff00) == 0xff00) 207 sc->sc_minsync = 0; 208 209 /* Really no limit, but since we want to fit into the TCR... */ 210 sc->sc_maxxfer = 64 * 1024; 211 212 fsc->sc_portbits = 0xa0 | FLSC_PB_EDI | FLSC_PB_ESI; 213 fsc->sc_hardbits = fsc->sc_reg[0x40]; 214 215 sc->sc_dev.dv_cfdata->cf_flags |= (scsi_nosync >> shift_nosync) & 0xffff; 216 shift_nosync += 16; 217 ncr53c9x_debug |= (scsi_nosync >> shift_nosync) & 0xffff; 218 shift_nosync += 16; 219 220 /* 221 * Configure interrupts. 222 */ 223 fsc->sc_isr.isr_intr = (int (*)(void *))ncr53c9x_intr; 224 fsc->sc_isr.isr_arg = sc; 225 fsc->sc_isr.isr_ipl = 2; 226 add_isr(&fsc->sc_isr); 227 228 fsc->sc_reg[0x40] = fsc->sc_portbits; 229 230 /* 231 * Now try to attach all the sub-devices 232 */ 233 ncr53c9x_attach(sc, &flsc_switch, &flsc_dev); 234 } 235 236 /* 237 * Glue functions. 238 */ 239 240 u_char 241 flsc_read_reg(sc, reg) 242 struct ncr53c9x_softc *sc; 243 int reg; 244 { 245 struct flsc_softc *fsc = (struct flsc_softc *)sc; 246 247 return fsc->sc_reg[reg * 4]; 248 } 249 250 void 251 flsc_write_reg(sc, reg, val) 252 struct ncr53c9x_softc *sc; 253 int reg; 254 u_char val; 255 { 256 struct flsc_softc *fsc = (struct flsc_softc *)sc; 257 struct ncr53c9x_tinfo *ti; 258 u_char v = val; 259 260 if (fsc->sc_piomode && reg == NCR_CMD && 261 v == (NCRCMD_TRANS|NCRCMD_DMA)) { 262 v = NCRCMD_TRANS; 263 } 264 /* 265 * Can't do synchronous transfers in SCSI_POLL mode: 266 * If starting SCSI_POLL command, clear defer sync negotiation 267 * by clearing the T_NEGOTIATE flag. If starting SCSI_POLL and 268 * the device is currently running synchronous, force another 269 * T_NEGOTIATE with 0 offset. 270 */ 271 if (reg == NCR_SELID) { 272 ti = &sc->sc_tinfo[ 273 sc->sc_nexus->xs->sc_link->scsipi_scsi.target]; 274 if (sc->sc_nexus->xs->flags & SCSI_POLL) { 275 if (ti->flags & T_SYNCMODE) { 276 ti->flags ^= T_SYNCMODE | T_NEGOTIATE; 277 } else if (ti->flags & T_NEGOTIATE) { 278 ti->flags ^= T_NEGOTIATE | T_SYNCHOFF; 279 /* save T_NEGOTIATE in private flags? */ 280 } 281 } else { 282 /* 283 * If we haven't attempted sync negotiation yet, 284 * do it now. 285 */ 286 if ((ti->flags & (T_SYNCMODE | T_SYNCHOFF)) == 287 T_SYNCHOFF && 288 sc->sc_minsync != 0) /* XXX */ 289 ti->flags ^= T_NEGOTIATE | T_SYNCHOFF; 290 } 291 } 292 if (reg == NCR_CMD && v == NCRCMD_SETATN && 293 sc->sc_flags & NCR_SYNCHNEGO && 294 sc->sc_nexus->xs->flags & SCSI_POLL) { 295 ti = &sc->sc_tinfo[ 296 sc->sc_nexus->xs->sc_link->scsipi_scsi.target]; 297 ti->offset = 0; 298 } 299 fsc->sc_reg[reg * 4] = v; 300 } 301 302 int 303 flsc_dma_isintr(sc) 304 struct ncr53c9x_softc *sc; 305 { 306 struct flsc_softc *fsc = (struct flsc_softc *)sc; 307 unsigned hardbits; 308 309 hardbits = fsc->sc_reg[0x40]; 310 if (hardbits & FLSC_HB_IACT) 311 return (fsc->sc_csr = 0); 312 313 if (sc->sc_state == NCR_CONNECTED || sc->sc_state == NCR_SELECTING) 314 fsc->sc_portbits |= FLSC_PB_LED; 315 else 316 fsc->sc_portbits &= ~FLSC_PB_LED; 317 318 if ((hardbits & FLSC_HB_CREQ) && !(hardbits & FLSC_HB_MINT) && 319 fsc->sc_reg[NCR_STAT * 4] & NCRSTAT_INT) { 320 return 1; 321 } 322 /* Do I still need this? */ 323 if (fsc->sc_piomode && fsc->sc_reg[NCR_STAT * 4] & NCRSTAT_INT && 324 !(hardbits & FLSC_HB_MINT)) 325 return 1; 326 327 fsc->sc_reg[0x40] = fsc->sc_portbits & ~FLSC_PB_INT_BITS; 328 fsc->sc_reg[0x40] = fsc->sc_portbits; 329 return 0; 330 } 331 332 void 333 flsc_clear_latched_intr(sc) 334 struct ncr53c9x_softc *sc; 335 { 336 struct flsc_softc *fsc = (struct flsc_softc *)sc; 337 338 fsc->sc_reg[0x40] = fsc->sc_portbits & ~FLSC_PB_INT_BITS; 339 fsc->sc_reg[0x40] = fsc->sc_portbits; 340 } 341 342 void 343 flsc_dma_reset(sc) 344 struct ncr53c9x_softc *sc; 345 { 346 struct flsc_softc *fsc = (struct flsc_softc *)sc; 347 struct ncr53c9x_tinfo *ti; 348 349 if (sc->sc_nexus) 350 ti = &sc->sc_tinfo[sc->sc_nexus->xs->sc_link->scsipi_scsi.target]; 351 else 352 ti = &sc->sc_tinfo[1]; /* XXX */ 353 if (fsc->sc_active) { 354 printf("dmaaddr %p dmasize %d stat %x flags %x off %d per %d ff %x", 355 *fsc->sc_dmaaddr, fsc->sc_dmasize, fsc->sc_reg[NCR_STAT * 4], 356 ti->flags, ti->offset, ti->period, fsc->sc_reg[NCR_FFLAG * 4]); 357 printf(" intr %x\n", fsc->sc_reg[NCR_INTR * 4]); 358 #ifdef DDB 359 Debugger(); 360 #endif 361 } 362 fsc->sc_portbits &= ~FLSC_PB_DMA_BITS; 363 fsc->sc_reg[0x40] = fsc->sc_portbits; 364 fsc->sc_reg[0x80] = 0; 365 *((u_long *)fsc->sc_dmabase) = 0; 366 fsc->sc_active = 0; 367 fsc->sc_piomode = 0; 368 } 369 370 int 371 flsc_dma_intr(sc) 372 struct ncr53c9x_softc *sc; 373 { 374 register struct flsc_softc *fsc = (struct flsc_softc *)sc; 375 register u_char *p; 376 volatile u_char *cmdreg, *intrreg, *statreg, *fiforeg; 377 register u_int flscphase, flscstat, flscintr; 378 register int cnt; 379 380 NCR_DMA(("flsc_dma_intr: pio %d cnt %d int %x stat %x fifo %d ", 381 fsc->sc_piomode, fsc->sc_dmasize, sc->sc_espintr, sc->sc_espstat, 382 fsc->sc_reg[NCR_FFLAG * 4] & NCRFIFO_FF)); 383 if (!(fsc->sc_reg[0x40] & FLSC_HB_CREQ)) 384 printf("flsc_dma_intr: csr %x stat %x intr %x\n", fsc->sc_csr, 385 sc->sc_espstat, sc->sc_espintr); 386 if (fsc->sc_active == 0) { 387 printf("flsc_intr--inactive DMA\n"); 388 return -1; 389 } 390 391 /* if DMA transfer, update sc_dmaaddr and sc_pdmalen, else PIO xfer */ 392 if (fsc->sc_piomode == 0) { 393 fsc->sc_portbits &= ~FLSC_PB_DMA_BITS; 394 fsc->sc_reg[0x40] = fsc->sc_portbits; 395 fsc->sc_reg[0x80] = 0; 396 *((u_long *)fsc->sc_dmabase) = 0; 397 cnt = fsc->sc_reg[NCR_TCL * 4]; 398 cnt += fsc->sc_reg[NCR_TCM * 4] << 8; 399 cnt += fsc->sc_reg[NCR_TCH * 4] << 16; 400 if (!fsc->sc_datain) { 401 cnt += fsc->sc_reg[NCR_FFLAG * 4] & NCRFIFO_FF; 402 fsc->sc_reg[NCR_CMD * 4] = NCRCMD_FLUSH; 403 } 404 cnt = fsc->sc_dmasize - cnt; /* number of bytes transferred */ 405 NCR_DMA(("DMA xferred %d\n", cnt)); 406 if (fsc->sc_xfr_align) { 407 int i; 408 for (i = 0; i < cnt; ++i) 409 (*fsc->sc_dmaaddr)[i] = fsc->sc_alignbuf[i]; 410 fsc->sc_xfr_align = 0; 411 } 412 *fsc->sc_dmaaddr += cnt; 413 *fsc->sc_pdmalen -= cnt; 414 fsc->sc_active = 0; 415 return 0; 416 } 417 418 if ((sc->sc_espintr & NCRINTR_BS) == 0) { 419 fsc->sc_active = 0; 420 fsc->sc_piomode = 0; 421 NCR_DMA(("no NCRINTR_BS\n")); 422 return 0; 423 } 424 425 cnt = fsc->sc_dmasize; 426 #if 0 427 if (cnt == 0) { 428 printf("data interrupt, but no count left."); 429 } 430 #endif 431 432 p = *fsc->sc_dmaaddr; 433 flscphase = sc->sc_phase; 434 flscstat = (u_int) sc->sc_espstat; 435 flscintr = (u_int) sc->sc_espintr; 436 cmdreg = fsc->sc_reg + NCR_CMD * 4; 437 fiforeg = fsc->sc_reg + NCR_FIFO * 4; 438 statreg = fsc->sc_reg + NCR_STAT * 4; 439 intrreg = fsc->sc_reg + NCR_INTR * 4; 440 NCR_DMA(("PIO %d datain %d phase %d stat %x intr %x\n", 441 cnt, fsc->sc_datain, flscphase, flscstat, flscintr)); 442 do { 443 if (fsc->sc_datain) { 444 *p++ = *fiforeg; 445 cnt--; 446 if (flscphase == DATA_IN_PHASE) { 447 *cmdreg = NCRCMD_TRANS; 448 } else { 449 fsc->sc_active = 0; 450 } 451 } else { 452 NCR_DMA(("flsc_dma_intr: PIO out- phase %d cnt %d active %d\n", flscphase, cnt, 453 fsc->sc_active)); 454 if ( (flscphase == DATA_OUT_PHASE) 455 || (flscphase == MESSAGE_OUT_PHASE)) { 456 int n; 457 n = 16 - (fsc->sc_reg[NCR_FFLAG * 4] & NCRFIFO_FF); 458 if (n > cnt) 459 n = cnt; 460 cnt -= n; 461 while (n-- > 0) 462 *fiforeg = *p++; 463 *cmdreg = NCRCMD_TRANS; 464 } else { 465 fsc->sc_active = 0; 466 } 467 } 468 469 if (fsc->sc_active && cnt) { 470 while (!(*statreg & 0x80)); 471 flscstat = *statreg; 472 flscintr = *intrreg; 473 flscphase = (flscintr & NCRINTR_DIS) 474 ? /* Disconnected */ BUSFREE_PHASE 475 : flscstat & PHASE_MASK; 476 } 477 } while (cnt && fsc->sc_active && (flscintr & NCRINTR_BS)); 478 #if 1 479 if (fsc->sc_dmasize < 8 && cnt) 480 printf("flsc_dma_intr: short transfer: dmasize %d cnt %d\n", 481 fsc->sc_dmasize, cnt); 482 #endif 483 NCR_DMA(("flsc_dma_intr: PIO transfer [%d], %d->%d phase %d stat %x intr %x\n", 484 *fsc->sc_pdmalen, fsc->sc_dmasize, cnt, flscphase, flscstat, flscintr)); 485 sc->sc_phase = flscphase; 486 sc->sc_espstat = (u_char) flscstat; 487 sc->sc_espintr = (u_char) flscintr; 488 *fsc->sc_dmaaddr = p; 489 *fsc->sc_pdmalen -= fsc->sc_dmasize - cnt; 490 fsc->sc_dmasize = cnt; 491 492 if (*fsc->sc_pdmalen == 0) { 493 sc->sc_espstat |= NCRSTAT_TC; 494 fsc->sc_piomode = 0; 495 } 496 return 0; 497 } 498 499 int 500 flsc_dma_setup(sc, addr, len, datain, dmasize) 501 struct ncr53c9x_softc *sc; 502 caddr_t *addr; 503 size_t *len; 504 int datain; 505 size_t *dmasize; 506 { 507 struct flsc_softc *fsc = (struct flsc_softc *)sc; 508 vm_offset_t pa; 509 u_char *ptr; 510 size_t xfer; 511 512 fsc->sc_dmaaddr = addr; 513 fsc->sc_pdmalen = len; 514 fsc->sc_datain = datain; 515 fsc->sc_dmasize = *dmasize; 516 if (sc->sc_nexus->xs->flags & SCSI_POLL) { 517 /* polling mode, use PIO */ 518 *dmasize = fsc->sc_dmasize; 519 NCR_DMA(("pfsc_dma_setup: PIO %p/%d [%d]\n", *addr, 520 fsc->sc_dmasize, *len)); 521 fsc->sc_piomode = 1; 522 if (datain == 0) { 523 int n; 524 n = fsc->sc_dmasize; 525 if (n > 16) 526 n = 16; 527 while (n-- > 0) { 528 fsc->sc_reg[NCR_FIFO * 4] = **fsc->sc_dmaaddr; 529 (*fsc->sc_pdmalen)--; 530 (*fsc->sc_dmaaddr)++; 531 --fsc->sc_dmasize; 532 } 533 } 534 return 0; 535 } 536 /* 537 * DMA can be nasty for high-speed serial input, so limit the 538 * size of this DMA operation if the serial port is running at 539 * a high speed (higher than 19200 for now - should be adjusted 540 * based on cpu type and speed?). 541 * XXX - add serial speed check XXX 542 */ 543 if (ser_open_speed > 19200 && flsc_max_dma != 0 && 544 fsc->sc_dmasize > flsc_max_dma) 545 fsc->sc_dmasize = flsc_max_dma; 546 ptr = *addr; /* Kernel virtual address */ 547 pa = kvtop(ptr); /* Physical address of DMA */ 548 xfer = min(fsc->sc_dmasize, NBPG - (pa & (NBPG - 1))); 549 fsc->sc_xfr_align = 0; 550 fsc->sc_piomode = 0; 551 fsc->sc_portbits &= ~FLSC_PB_DMA_BITS; 552 fsc->sc_reg[0x40] = fsc->sc_portbits; 553 fsc->sc_reg[0x80] = 0; 554 *((u_long *)fsc->sc_dmabase) = 0; 555 556 /* 557 * If output and length < 16, copy to fifo 558 */ 559 if (datain == 0 && fsc->sc_dmasize < 16) { 560 int n; 561 for (n = 0; n < fsc->sc_dmasize; ++n) 562 fsc->sc_reg[NCR_FIFO * 4] = *ptr++; 563 NCR_DMA(("flsc_dma_setup: %d bytes written to fifo\n", n)); 564 fsc->sc_piomode = 1; 565 fsc->sc_active = 1; 566 *fsc->sc_pdmalen -= fsc->sc_dmasize; 567 *fsc->sc_dmaaddr += fsc->sc_dmasize; 568 *dmasize = fsc->sc_dmasize; 569 fsc->sc_dmasize = 0; 570 return 0; /* All done */ 571 } 572 /* 573 * If output and unaligned, copy unaligned data to fifo 574 */ 575 else if (datain == 0 && (int)ptr & 3) { 576 int n = 4 - ((int)ptr & 3); 577 NCR_DMA(("flsc_dma_setup: align %d bytes written to fifo\n", n)); 578 pa += n; 579 xfer -= n; 580 while (n--) 581 fsc->sc_reg[NCR_FIFO * 4] = *ptr++; 582 } 583 /* 584 * If unaligned address, read unaligned bytes into alignment buffer 585 */ 586 else if ((int)ptr & 3 || xfer & 3) { 587 pa = kvtop((caddr_t)&fsc->sc_alignbuf); 588 xfer = fsc->sc_dmasize = min(xfer, sizeof (fsc->sc_alignbuf)); 589 NCR_DMA(("flsc_dma_setup: align read by %d bytes\n", xfer)); 590 fsc->sc_xfr_align = 1; 591 } 592 /* 593 * If length smaller than longword, read into alignment buffer 594 * XXX doesn't work for 1 or 2 bytes !!!! 595 */ 596 else if (fsc->sc_dmasize < 4) { 597 NCR_DMA(("flsc_dma_setup: read remaining %d bytes\n", 598 fsc->sc_dmasize)); 599 pa = kvtop((caddr_t)&fsc->sc_alignbuf); 600 fsc->sc_xfr_align = 1; 601 } 602 /* 603 * Finally, limit transfer length to multiple of 4 bytes. 604 */ 605 else { 606 fsc->sc_dmasize &= -4; 607 xfer &= -4; 608 } 609 610 while (xfer < fsc->sc_dmasize) { 611 if ((pa + xfer) != kvtop(*addr + xfer)) 612 break; 613 if ((fsc->sc_dmasize - xfer) < NBPG) 614 xfer = fsc->sc_dmasize; 615 else 616 xfer += NBPG; 617 } 618 619 fsc->sc_dmasize = xfer; 620 *dmasize = fsc->sc_dmasize; 621 fsc->sc_pa = pa; 622 #if defined(M68040) || defined(M68060) 623 if (mmutype == MMU_68040) { 624 if (fsc->sc_xfr_align) { 625 int n; 626 for (n = 0; n < sizeof (fsc->sc_alignbuf); ++n) 627 fsc->sc_alignbuf[n] = n | 0x80; 628 dma_cachectl(fsc->sc_alignbuf, 629 sizeof(fsc->sc_alignbuf)); 630 } 631 else 632 dma_cachectl(*fsc->sc_dmaaddr, fsc->sc_dmasize); 633 } 634 #endif 635 fsc->sc_reg[0x80] = 0; 636 *((u_long *)(fsc->sc_dmabase + (pa & 0x00fffffc))) = pa; 637 fsc->sc_portbits &= ~FLSC_PB_DMA_BITS; 638 fsc->sc_portbits |= FLSC_PB_ENABLE_DMA | 639 (fsc->sc_datain ? FLSC_PB_DMA_READ : FLSC_PB_DMA_WRITE); 640 fsc->sc_reg[0x40] = fsc->sc_portbits; 641 NCR_DMA(("flsc_dma_setup: DMA %p->%lx/%d [%d]\n", 642 ptr, pa, fsc->sc_dmasize, *len)); 643 fsc->sc_active = 1; 644 return 0; 645 } 646 647 void 648 flsc_dma_go(sc) 649 struct ncr53c9x_softc *sc; 650 { 651 struct flsc_softc *fsc = (struct flsc_softc *)sc; 652 653 NCR_DMA(("flsc_dma_go: datain %d size %d\n", fsc->sc_datain, 654 fsc->sc_dmasize)); 655 if (sc->sc_nexus->xs->flags & SCSI_POLL) { 656 fsc->sc_active = 1; 657 return; 658 } else if (fsc->sc_piomode == 0) { 659 fsc->sc_portbits &= ~FLSC_PB_DMA_BITS; 660 fsc->sc_portbits |= FLSC_PB_ENABLE_DMA | 661 (fsc->sc_datain ? FLSC_PB_DMA_READ : FLSC_PB_DMA_WRITE); 662 fsc->sc_reg[0x40] = fsc->sc_portbits; 663 } 664 } 665 666 void 667 flsc_dma_stop(sc) 668 struct ncr53c9x_softc *sc; 669 { 670 struct flsc_softc *fsc = (struct flsc_softc *)sc; 671 672 fsc->sc_portbits &= ~FLSC_PB_DMA_BITS; 673 fsc->sc_reg[0x40] = fsc->sc_portbits; 674 675 fsc->sc_reg[0x80] = 0; 676 *((u_long *)fsc->sc_dmabase) = 0; 677 fsc->sc_piomode = 0; 678 } 679 680 int 681 flsc_dma_isactive(sc) 682 struct ncr53c9x_softc *sc; 683 { 684 struct flsc_softc *fsc = (struct flsc_softc *)sc; 685 686 return fsc->sc_active; 687 } 688
Indexes created Thu Oct 02 14:10:14 GMT 2025