flsc.c revision 1.18
1 /* $NetBSD: flsc.c,v 1.18 1998/01/12 10:39:27 thorpej Exp $ */ 2 3 /* 4 * Copyright (c) 1997 Michael L. Hitch 5 * Copyright (c) 1995 Daniel Widenfalk 6 * Copyright (c) 1994 Christian E. Hopps 7 * Copyright (c) 1982, 1990 The Regents of the University of California. 8 * All rights reserved. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 3. All advertising materials mentioning features or use of this software 19 * must display the following acknowledgement: 20 * This product includes software developed by Daniel Widenfalk 21 * and Michael L. Hitch. 22 * 4. Neither the name of the University nor the names of its contributors 23 * may be used to endorse or promote products derived from this software 24 * without specific prior written permission. 25 * 26 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 27 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 28 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 29 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 30 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 31 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 32 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 33 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 34 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 35 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 36 * SUCH DAMAGE. 37 */ 38 39 /* 40 * Initial amiga Fastlane driver by Daniel Widenfalk. Conversion to 41 * 53c9x MI driver by Michael L. Hitch (mhitch (at) montana.edu). 42 */ 43 44 #include <sys/types.h> 45 #include <sys/param.h> 46 #include <sys/systm.h> 47 #include <sys/kernel.h> 48 #include <sys/errno.h> 49 #include <sys/ioctl.h> 50 #include <sys/device.h> 51 #include <sys/buf.h> 52 #include <sys/proc.h> 53 #include <sys/user.h> 54 #include <sys/queue.h> 55 56 #include <dev/scsipi/scsi_all.h> 57 #include <dev/scsipi/scsipi_all.h> 58 #include <dev/scsipi/scsiconf.h> 59 #include <dev/scsipi/scsi_message.h> 60 61 #include <machine/cpu.h> 62 #include <machine/param.h> 63 64 #include <dev/ic/ncr53c9xreg.h> 65 #include <dev/ic/ncr53c9xvar.h> 66 67 #include <amiga/amiga/isr.h> 68 #include <amiga/dev/flscvar.h> 69 #include <amiga/dev/zbusvar.h> 70 71 void flscattach __P((struct device *, struct device *, void *)); 72 int flscmatch __P((struct device *, struct cfdata *, void *)); 73 74 /* Linkup to the rest of the kernel */ 75 struct cfattach flsc_ca = { 76 sizeof(struct flsc_softc), flscmatch, flscattach 77 }; 78 79 struct scsipi_adapter flsc_switch = { 80 ncr53c9x_scsi_cmd, 81 minphys, /* no max at this level; handled by DMA code */ 82 NULL, 83 NULL, 84 }; 85 86 struct scsipi_device flsc_dev = { 87 NULL, /* Use default error handler */ 88 NULL, /* have a queue, served by this */ 89 NULL, /* have no async handler */ 90 NULL, /* Use default 'done' routine */ 91 }; 92 93 /* 94 * Functions and the switch for the MI code. 95 */ 96 u_char flsc_read_reg __P((struct ncr53c9x_softc *, int)); 97 void flsc_write_reg __P((struct ncr53c9x_softc *, int, u_char)); 98 int flsc_dma_isintr __P((struct ncr53c9x_softc *)); 99 void flsc_dma_reset __P((struct ncr53c9x_softc *)); 100 int flsc_dma_intr __P((struct ncr53c9x_softc *)); 101 int flsc_dma_setup __P((struct ncr53c9x_softc *, caddr_t *, 102 size_t *, int, size_t *)); 103 void flsc_dma_go __P((struct ncr53c9x_softc *)); 104 void flsc_dma_stop __P((struct ncr53c9x_softc *)); 105 int flsc_dma_isactive __P((struct ncr53c9x_softc *)); 106 void flsc_clear_latched_intr __P((struct ncr53c9x_softc *)); 107 108 struct ncr53c9x_glue flsc_glue = { 109 flsc_read_reg, 110 flsc_write_reg, 111 flsc_dma_isintr, 112 flsc_dma_reset, 113 flsc_dma_intr, 114 flsc_dma_setup, 115 flsc_dma_go, 116 flsc_dma_stop, 117 flsc_dma_isactive, 118 flsc_clear_latched_intr, 119 }; 120 121 /* Maximum DMA transfer length to reduce impact on high-speed serial input */ 122 u_long flsc_max_dma = 1024; 123 extern int ser_open_speed; 124 125 extern int ncr53c9x_debug; 126 extern u_long scsi_nosync; 127 extern int shift_nosync; 128 129 /* 130 * if we are an Advanced Systems & Software FastlaneZ3 131 */ 132 int 133 flscmatch(parent, cf, aux) 134 struct device *parent; 135 struct cfdata *cf; 136 void *aux; 137 { 138 struct zbus_args *zap; 139 140 if (!is_a4000() && !is_a3000()) 141 return(0); 142 143 zap = aux; 144 if (zap->manid == 0x2140 && zap->prodid == 11 145 && iszthreepa(zap->pa)) 146 return(1); 147 148 return(0); 149 } 150 151 /* 152 * Attach this instance, and then all the sub-devices 153 */ 154 void 155 flscattach(parent, self, aux) 156 struct device *parent, *self; 157 void *aux; 158 { 159 struct flsc_softc *fsc = (void *)self; 160 struct ncr53c9x_softc *sc = &fsc->sc_ncr53c9x; 161 struct zbus_args *zap; 162 163 /* 164 * Set up the glue for MI code early; we use some of it here. 165 */ 166 sc->sc_glue = &flsc_glue; 167 168 /* 169 * Save the regs 170 */ 171 zap = aux; 172 fsc->sc_dmabase = (volatile u_char *)zap->va; 173 fsc->sc_reg = &((volatile u_char *)zap->va)[0x1000001]; 174 175 sc->sc_freq = 40; /* Clocked at 40Mhz */ 176 177 printf(": address %p", fsc->sc_reg); 178 179 sc->sc_id = 7; 180 181 /* 182 * It is necessary to try to load the 2nd config register here, 183 * to find out what rev the flsc chip is, else the flsc_reset 184 * will not set up the defaults correctly. 185 */ 186 sc->sc_cfg1 = sc->sc_id | NCRCFG1_PARENB; 187 sc->sc_cfg2 = NCRCFG2_SCSI2 | NCRCFG2_FE; 188 sc->sc_cfg3 = 0x08 /*FCLK*/ | NCRESPCFG3_FSCSI | NCRESPCFG3_CDB; 189 sc->sc_rev = NCR_VARIANT_FAS216; 190 191 /* 192 * This is the value used to start sync negotiations 193 * Note that the NCR register "SYNCTP" is programmed 194 * in "clocks per byte", and has a minimum value of 4. 195 * The SCSI period used in negotiation is one-fourth 196 * of the time (in nanoseconds) needed to transfer one byte. 197 * Since the chip's clock is given in MHz, we have the following 198 * formula: 4 * period = (1000 / freq) * 4 199 */ 200 sc->sc_minsync = 1000 / sc->sc_freq; 201 202 if (((scsi_nosync >> shift_nosync) & 0xff00) == 0xff00) 203 sc->sc_minsync = 0; 204 205 /* Really no limit, but since we want to fit into the TCR... */ 206 sc->sc_maxxfer = 64 * 1024; 207 208 fsc->sc_portbits = 0xa0 | FLSC_PB_EDI | FLSC_PB_ESI; 209 fsc->sc_hardbits = fsc->sc_reg[0x40]; 210 211 fsc->sc_alignbuf = (char *)((u_long)fsc->sc_unalignbuf & -4); 212 213 sc->sc_dev.dv_cfdata->cf_flags |= (scsi_nosync >> shift_nosync) & 0xffff; 214 shift_nosync += 16; 215 ncr53c9x_debug |= (scsi_nosync >> shift_nosync) & 0xffff; 216 shift_nosync += 16; 217 218 /* 219 * Configure interrupts. 220 */ 221 fsc->sc_isr.isr_intr = (int (*)(void *))ncr53c9x_intr; 222 fsc->sc_isr.isr_arg = sc; 223 fsc->sc_isr.isr_ipl = 2; 224 add_isr(&fsc->sc_isr); 225 226 fsc->sc_reg[0x40] = fsc->sc_portbits; 227 228 /* 229 * Now try to attach all the sub-devices 230 */ 231 ncr53c9x_attach(sc, &flsc_switch, &flsc_dev); 232 } 233 234 /* 235 * Glue functions. 236 */ 237 238 u_char 239 flsc_read_reg(sc, reg) 240 struct ncr53c9x_softc *sc; 241 int reg; 242 { 243 struct flsc_softc *fsc = (struct flsc_softc *)sc; 244 245 return fsc->sc_reg[reg * 4]; 246 } 247 248 void 249 flsc_write_reg(sc, reg, val) 250 struct ncr53c9x_softc *sc; 251 int reg; 252 u_char val; 253 { 254 struct flsc_softc *fsc = (struct flsc_softc *)sc; 255 struct ncr53c9x_tinfo *ti; 256 u_char v = val; 257 258 if (fsc->sc_piomode && reg == NCR_CMD && 259 v == (NCRCMD_TRANS|NCRCMD_DMA)) { 260 v = NCRCMD_TRANS; 261 } 262 /* 263 * Can't do synchronous transfers in SCSI_POLL mode: 264 * If starting SCSI_POLL command, clear defer sync negotiation 265 * by clearing the T_NEGOTIATE flag. If starting SCSI_POLL and 266 * the device is currently running synchronous, force another 267 * T_NEGOTIATE with 0 offset. 268 */ 269 if (reg == NCR_SELID) { 270 ti = &sc->sc_tinfo[ 271 sc->sc_nexus->xs->sc_link->scsipi_scsi.target]; 272 if (sc->sc_nexus->xs->flags & SCSI_POLL) { 273 if (ti->flags & T_SYNCMODE) { 274 ti->flags ^= T_SYNCMODE | T_NEGOTIATE; 275 } else if (ti->flags & T_NEGOTIATE) { 276 ti->flags ^= T_NEGOTIATE | T_SYNCHOFF; 277 /* save T_NEGOTIATE in private flags? */ 278 } 279 } else { 280 /* 281 * If we haven't attempted sync negotiation yet, 282 * do it now. 283 */ 284 if ((ti->flags & (T_SYNCMODE | T_SYNCHOFF)) == 285 T_SYNCHOFF && 286 sc->sc_minsync != 0) /* XXX */ 287 ti->flags ^= T_NEGOTIATE | T_SYNCHOFF; 288 } 289 } 290 if (reg == NCR_CMD && v == NCRCMD_SETATN && 291 sc->sc_flags & NCR_SYNCHNEGO && 292 sc->sc_nexus->xs->flags & SCSI_POLL) { 293 ti = &sc->sc_tinfo[ 294 sc->sc_nexus->xs->sc_link->scsipi_scsi.target]; 295 ti->offset = 0; 296 } 297 fsc->sc_reg[reg * 4] = v; 298 } 299 300 int 301 flsc_dma_isintr(sc) 302 struct ncr53c9x_softc *sc; 303 { 304 struct flsc_softc *fsc = (struct flsc_softc *)sc; 305 unsigned hardbits; 306 307 hardbits = fsc->sc_reg[0x40]; 308 if (hardbits & FLSC_HB_IACT) 309 return (fsc->sc_csr = 0); 310 311 if (sc->sc_state == NCR_CONNECTED || sc->sc_state == NCR_SELECTING) 312 fsc->sc_portbits |= FLSC_PB_LED; 313 else 314 fsc->sc_portbits &= ~FLSC_PB_LED; 315 316 if ((hardbits & FLSC_HB_CREQ) && !(hardbits & FLSC_HB_MINT) && 317 fsc->sc_reg[NCR_STAT * 4] & NCRSTAT_INT) { 318 return 1; 319 } 320 /* Do I still need this? */ 321 if (fsc->sc_piomode && fsc->sc_reg[NCR_STAT * 4] & NCRSTAT_INT && 322 !(hardbits & FLSC_HB_MINT)) 323 return 1; 324 325 fsc->sc_reg[0x40] = fsc->sc_portbits & ~FLSC_PB_INT_BITS; 326 fsc->sc_reg[0x40] = fsc->sc_portbits; 327 return 0; 328 } 329 330 void 331 flsc_clear_latched_intr(sc) 332 struct ncr53c9x_softc *sc; 333 { 334 struct flsc_softc *fsc = (struct flsc_softc *)sc; 335 336 fsc->sc_reg[0x40] = fsc->sc_portbits & ~FLSC_PB_INT_BITS; 337 fsc->sc_reg[0x40] = fsc->sc_portbits; 338 } 339 340 void 341 flsc_dma_reset(sc) 342 struct ncr53c9x_softc *sc; 343 { 344 struct flsc_softc *fsc = (struct flsc_softc *)sc; 345 struct ncr53c9x_tinfo *ti; 346 347 if (sc->sc_nexus) 348 ti = &sc->sc_tinfo[sc->sc_nexus->xs->sc_link->scsipi_scsi.target]; 349 else 350 ti = &sc->sc_tinfo[1]; /* XXX */ 351 if (fsc->sc_active) { 352 printf("dmaaddr %p dmasize %d stat %x flags %x off %d per %d ff %x", 353 *fsc->sc_dmaaddr, fsc->sc_dmasize, fsc->sc_reg[NCR_STAT * 4], 354 ti->flags, ti->offset, ti->period, fsc->sc_reg[NCR_FFLAG * 4]); 355 printf(" intr %x\n", fsc->sc_reg[NCR_INTR * 4]); 356 #ifdef DDB 357 Debugger(); 358 #endif 359 } 360 fsc->sc_portbits &= ~FLSC_PB_DMA_BITS; 361 fsc->sc_reg[0x40] = fsc->sc_portbits; 362 fsc->sc_reg[0x80] = 0; 363 *((u_long *)fsc->sc_dmabase) = 0; 364 fsc->sc_active = 0; 365 fsc->sc_piomode = 0; 366 } 367 368 int 369 flsc_dma_intr(sc) 370 struct ncr53c9x_softc *sc; 371 { 372 register struct flsc_softc *fsc = (struct flsc_softc *)sc; 373 register u_char *p; 374 volatile u_char *cmdreg, *intrreg, *statreg, *fiforeg; 375 register u_int flscphase, flscstat, flscintr; 376 register int cnt; 377 378 NCR_DMA(("flsc_dma_intr: pio %d cnt %d int %x stat %x fifo %d ", 379 fsc->sc_piomode, fsc->sc_dmasize, sc->sc_espintr, sc->sc_espstat, 380 fsc->sc_reg[NCR_FFLAG * 4] & NCRFIFO_FF)); 381 if (!(fsc->sc_reg[0x40] & FLSC_HB_CREQ)) 382 printf("flsc_dma_intr: csr %x stat %x intr %x\n", fsc->sc_csr, 383 sc->sc_espstat, sc->sc_espintr); 384 if (fsc->sc_active == 0) { 385 printf("flsc_intr--inactive DMA\n"); 386 return -1; 387 } 388 389 /* if DMA transfer, update sc_dmaaddr and sc_pdmalen, else PIO xfer */ 390 if (fsc->sc_piomode == 0) { 391 fsc->sc_portbits &= ~FLSC_PB_DMA_BITS; 392 fsc->sc_reg[0x40] = fsc->sc_portbits; 393 fsc->sc_reg[0x80] = 0; 394 *((u_long *)fsc->sc_dmabase) = 0; 395 cnt = fsc->sc_reg[NCR_TCL * 4]; 396 cnt += fsc->sc_reg[NCR_TCM * 4] << 8; 397 cnt += fsc->sc_reg[NCR_TCH * 4] << 16; 398 if (!fsc->sc_datain) { 399 cnt += fsc->sc_reg[NCR_FFLAG * 4] & NCRFIFO_FF; 400 fsc->sc_reg[NCR_CMD * 4] = NCRCMD_FLUSH; 401 } 402 cnt = fsc->sc_dmasize - cnt; /* number of bytes transferred */ 403 NCR_DMA(("DMA xferred %d\n", cnt)); 404 if (fsc->sc_xfr_align) { 405 int i; 406 for (i = 0; i < cnt; ++i) 407 (*fsc->sc_dmaaddr)[i] = fsc->sc_alignbuf[i]; 408 fsc->sc_xfr_align = 0; 409 } 410 *fsc->sc_dmaaddr += cnt; 411 *fsc->sc_pdmalen -= cnt; 412 fsc->sc_active = 0; 413 return 0; 414 } 415 416 if ((sc->sc_espintr & NCRINTR_BS) == 0) { 417 fsc->sc_active = 0; 418 fsc->sc_piomode = 0; 419 NCR_DMA(("no NCRINTR_BS\n")); 420 return 0; 421 } 422 423 cnt = fsc->sc_dmasize; 424 #if 0 425 if (cnt == 0) { 426 printf("data interrupt, but no count left."); 427 } 428 #endif 429 430 p = *fsc->sc_dmaaddr; 431 flscphase = sc->sc_phase; 432 flscstat = (u_int) sc->sc_espstat; 433 flscintr = (u_int) sc->sc_espintr; 434 cmdreg = fsc->sc_reg + NCR_CMD * 4; 435 fiforeg = fsc->sc_reg + NCR_FIFO * 4; 436 statreg = fsc->sc_reg + NCR_STAT * 4; 437 intrreg = fsc->sc_reg + NCR_INTR * 4; 438 NCR_DMA(("PIO %d datain %d phase %d stat %x intr %x\n", 439 cnt, fsc->sc_datain, flscphase, flscstat, flscintr)); 440 do { 441 if (fsc->sc_datain) { 442 *p++ = *fiforeg; 443 cnt--; 444 if (flscphase == DATA_IN_PHASE) { 445 *cmdreg = NCRCMD_TRANS; 446 } else { 447 fsc->sc_active = 0; 448 } 449 } else { 450 NCR_DMA(("flsc_dma_intr: PIO out- phase %d cnt %d active %d\n", flscphase, cnt, 451 fsc->sc_active)); 452 if ( (flscphase == DATA_OUT_PHASE) 453 || (flscphase == MESSAGE_OUT_PHASE)) { 454 int n; 455 n = 16 - (fsc->sc_reg[NCR_FFLAG * 4] & NCRFIFO_FF); 456 if (n > cnt) 457 n = cnt; 458 cnt -= n; 459 while (n-- > 0) 460 *fiforeg = *p++; 461 *cmdreg = NCRCMD_TRANS; 462 } else { 463 fsc->sc_active = 0; 464 } 465 } 466 467 if (fsc->sc_active && cnt) { 468 while (!(*statreg & 0x80)); 469 flscstat = *statreg; 470 flscintr = *intrreg; 471 flscphase = (flscintr & NCRINTR_DIS) 472 ? /* Disconnected */ BUSFREE_PHASE 473 : flscstat & PHASE_MASK; 474 } 475 } while (cnt && fsc->sc_active && (flscintr & NCRINTR_BS)); 476 #if 1 477 if (fsc->sc_dmasize < 8 && cnt) 478 printf("flsc_dma_intr: short transfer: dmasize %d cnt %d\n", 479 fsc->sc_dmasize, cnt); 480 #endif 481 NCR_DMA(("flsc_dma_intr: PIO transfer [%d], %d->%d phase %d stat %x intr %x\n", 482 *fsc->sc_pdmalen, fsc->sc_dmasize, cnt, flscphase, flscstat, flscintr)); 483 sc->sc_phase = flscphase; 484 sc->sc_espstat = (u_char) flscstat; 485 sc->sc_espintr = (u_char) flscintr; 486 *fsc->sc_dmaaddr = p; 487 *fsc->sc_pdmalen -= fsc->sc_dmasize - cnt; 488 fsc->sc_dmasize = cnt; 489 490 if (*fsc->sc_pdmalen == 0) { 491 sc->sc_espstat |= NCRSTAT_TC; 492 fsc->sc_piomode = 0; 493 } 494 return 0; 495 } 496 497 int 498 flsc_dma_setup(sc, addr, len, datain, dmasize) 499 struct ncr53c9x_softc *sc; 500 caddr_t *addr; 501 size_t *len; 502 int datain; 503 size_t *dmasize; 504 { 505 struct flsc_softc *fsc = (struct flsc_softc *)sc; 506 vm_offset_t pa; 507 u_char *ptr; 508 size_t xfer; 509 510 fsc->sc_dmaaddr = addr; 511 fsc->sc_pdmalen = len; 512 fsc->sc_datain = datain; 513 fsc->sc_dmasize = *dmasize; 514 if (sc->sc_nexus->xs->flags & SCSI_POLL) { 515 /* polling mode, use PIO */ 516 *dmasize = fsc->sc_dmasize; 517 NCR_DMA(("pfsc_dma_setup: PIO %p/%d [%d]\n", *addr, 518 fsc->sc_dmasize, *len)); 519 fsc->sc_piomode = 1; 520 if (datain == 0) { 521 int n; 522 n = fsc->sc_dmasize; 523 if (n > 16) 524 n = 16; 525 while (n-- > 0) { 526 fsc->sc_reg[NCR_FIFO * 4] = **fsc->sc_dmaaddr; 527 (*fsc->sc_pdmalen)--; 528 (*fsc->sc_dmaaddr)++; 529 --fsc->sc_dmasize; 530 } 531 } 532 return 0; 533 } 534 /* 535 * DMA can be nasty for high-speed serial input, so limit the 536 * size of this DMA operation if the serial port is running at 537 * a high speed (higher than 19200 for now - should be adjusted 538 * based on cpu type and speed?). 539 * XXX - add serial speed check XXX 540 */ 541 if (ser_open_speed > 19200 && flsc_max_dma != 0 && 542 fsc->sc_dmasize > flsc_max_dma) 543 fsc->sc_dmasize = flsc_max_dma; 544 ptr = *addr; /* Kernel virtual address */ 545 pa = kvtop(ptr); /* Physical address of DMA */ 546 xfer = min(fsc->sc_dmasize, NBPG - (pa & (NBPG - 1))); 547 fsc->sc_xfr_align = 0; 548 fsc->sc_piomode = 0; 549 fsc->sc_portbits &= ~FLSC_PB_DMA_BITS; 550 fsc->sc_reg[0x40] = fsc->sc_portbits; 551 fsc->sc_reg[0x80] = 0; 552 *((u_long *)fsc->sc_dmabase) = 0; 553 554 /* 555 * If output and length < 16, copy to fifo 556 */ 557 if (datain == 0 && fsc->sc_dmasize < 16) { 558 int n; 559 for (n = 0; n < fsc->sc_dmasize; ++n) 560 fsc->sc_reg[NCR_FIFO * 4] = *ptr++; 561 NCR_DMA(("flsc_dma_setup: %d bytes written to fifo\n", n)); 562 fsc->sc_piomode = 1; 563 fsc->sc_active = 1; 564 *fsc->sc_pdmalen -= fsc->sc_dmasize; 565 *fsc->sc_dmaaddr += fsc->sc_dmasize; 566 *dmasize = fsc->sc_dmasize; 567 fsc->sc_dmasize = 0; 568 return 0; /* All done */ 569 } 570 /* 571 * If output and unaligned, copy unaligned data to fifo 572 */ 573 else if (datain == 0 && (int)ptr & 3) { 574 int n = 4 - ((int)ptr & 3); 575 NCR_DMA(("flsc_dma_setup: align %d bytes written to fifo\n", n)); 576 pa += n; 577 xfer -= n; 578 while (n--) 579 fsc->sc_reg[NCR_FIFO * 4] = *ptr++; 580 } 581 /* 582 * If unaligned address, read unaligned bytes into alignment buffer 583 */ 584 else if ((int)ptr & 3 || xfer & 3) { 585 pa = kvtop((caddr_t)fsc->sc_alignbuf); 586 xfer = fsc->sc_dmasize = min(xfer, sizeof (fsc->sc_unalignbuf)); 587 NCR_DMA(("flsc_dma_setup: align read by %d bytes\n", xfer)); 588 fsc->sc_xfr_align = 1; 589 } 590 /* 591 * If length smaller than longword, read into alignment buffer 592 * XXX doesn't work for 1 or 2 bytes !!!! 593 */ 594 else if (fsc->sc_dmasize < 4) { 595 NCR_DMA(("flsc_dma_setup: read remaining %d bytes\n", 596 fsc->sc_dmasize)); 597 pa = kvtop((caddr_t)fsc->sc_alignbuf); 598 fsc->sc_xfr_align = 1; 599 } 600 /* 601 * Finally, limit transfer length to multiple of 4 bytes. 602 */ 603 else { 604 fsc->sc_dmasize &= -4; 605 xfer &= -4; 606 } 607 608 while (xfer < fsc->sc_dmasize) { 609 if ((pa + xfer) != kvtop(*addr + xfer)) 610 break; 611 if ((fsc->sc_dmasize - xfer) < NBPG) 612 xfer = fsc->sc_dmasize; 613 else 614 xfer += NBPG; 615 } 616 617 fsc->sc_dmasize = xfer; 618 *dmasize = fsc->sc_dmasize; 619 fsc->sc_pa = pa; 620 #if defined(M68040) || defined(M68060) 621 if (mmutype == MMU_68040) { 622 if (fsc->sc_xfr_align) { 623 int n; 624 for (n = 0; n < sizeof (fsc->sc_unalignbuf); ++n) 625 fsc->sc_alignbuf[n] = n | 0x80; 626 dma_cachectl(fsc->sc_alignbuf, 627 sizeof(fsc->sc_unalignbuf)); 628 } 629 else 630 dma_cachectl(*fsc->sc_dmaaddr, fsc->sc_dmasize); 631 } 632 #endif 633 fsc->sc_reg[0x80] = 0; 634 *((u_long *)(fsc->sc_dmabase + (pa & 0x00fffffc))) = pa; 635 fsc->sc_portbits &= ~FLSC_PB_DMA_BITS; 636 fsc->sc_portbits |= FLSC_PB_ENABLE_DMA | 637 (fsc->sc_datain ? FLSC_PB_DMA_READ : FLSC_PB_DMA_WRITE); 638 fsc->sc_reg[0x40] = fsc->sc_portbits; 639 NCR_DMA(("flsc_dma_setup: DMA %p->%lx/%d [%d]\n", 640 ptr, pa, fsc->sc_dmasize, *len)); 641 fsc->sc_active = 1; 642 return 0; 643 } 644 645 void 646 flsc_dma_go(sc) 647 struct ncr53c9x_softc *sc; 648 { 649 struct flsc_softc *fsc = (struct flsc_softc *)sc; 650 651 NCR_DMA(("flsc_dma_go: datain %d size %d\n", fsc->sc_datain, 652 fsc->sc_dmasize)); 653 if (sc->sc_nexus->xs->flags & SCSI_POLL) { 654 fsc->sc_active = 1; 655 return; 656 } else if (fsc->sc_piomode == 0) { 657 fsc->sc_portbits &= ~FLSC_PB_DMA_BITS; 658 fsc->sc_portbits |= FLSC_PB_ENABLE_DMA | 659 (fsc->sc_datain ? FLSC_PB_DMA_READ : FLSC_PB_DMA_WRITE); 660 fsc->sc_reg[0x40] = fsc->sc_portbits; 661 } 662 } 663 664 void 665 flsc_dma_stop(sc) 666 struct ncr53c9x_softc *sc; 667 { 668 struct flsc_softc *fsc = (struct flsc_softc *)sc; 669 670 fsc->sc_portbits &= ~FLSC_PB_DMA_BITS; 671 fsc->sc_reg[0x40] = fsc->sc_portbits; 672 673 fsc->sc_reg[0x80] = 0; 674 *((u_long *)fsc->sc_dmabase) = 0; 675 fsc->sc_piomode = 0; 676 } 677 678 int 679 flsc_dma_isactive(sc) 680 struct ncr53c9x_softc *sc; 681 { 682 struct flsc_softc *fsc = (struct flsc_softc *)sc; 683 684 return fsc->sc_active; 685 } 686
Indexes created Thu Oct 02 14:10:14 GMT 2025