flsc.c revision 1.22
1 /* $NetBSD: flsc.c,v 1.22 1998/10/10 00:28:36 thorpej Exp $ */ 2 3 /* 4 * Copyright (c) 1997 Michael L. Hitch 5 * Copyright (c) 1995 Daniel Widenfalk 6 * Copyright (c) 1994 Christian E. Hopps 7 * Copyright (c) 1982, 1990 The Regents of the University of California. 8 * All rights reserved. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 3. All advertising materials mentioning features or use of this software 19 * must display the following acknowledgement: 20 * This product includes software developed by Daniel Widenfalk 21 * and Michael L. Hitch. 22 * 4. Neither the name of the University nor the names of its contributors 23 * may be used to endorse or promote products derived from this software 24 * without specific prior written permission. 25 * 26 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 27 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 28 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 29 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 30 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 31 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 32 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 33 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 34 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 35 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 36 * SUCH DAMAGE. 37 */ 38 39 /* 40 * Initial amiga Fastlane driver by Daniel Widenfalk. Conversion to 41 * 53c9x MI driver by Michael L. Hitch (mhitch (at) montana.edu). 42 */ 43 44 #include "opt_ddb.h" 45 46 #include <sys/types.h> 47 #include <sys/param.h> 48 #include <sys/systm.h> 49 #include <sys/kernel.h> 50 #include <sys/errno.h> 51 #include <sys/ioctl.h> 52 #include <sys/device.h> 53 #include <sys/buf.h> 54 #include <sys/proc.h> 55 #include <sys/user.h> 56 #include <sys/queue.h> 57 58 #include <dev/scsipi/scsi_all.h> 59 #include <dev/scsipi/scsipi_all.h> 60 #include <dev/scsipi/scsiconf.h> 61 #include <dev/scsipi/scsi_message.h> 62 63 #include <machine/cpu.h> 64 #include <machine/param.h> 65 66 #include <dev/ic/ncr53c9xreg.h> 67 #include <dev/ic/ncr53c9xvar.h> 68 69 #include <amiga/amiga/isr.h> 70 #include <amiga/dev/flscvar.h> 71 #include <amiga/dev/zbusvar.h> 72 73 void flscattach __P((struct device *, struct device *, void *)); 74 int flscmatch __P((struct device *, struct cfdata *, void *)); 75 76 /* Linkup to the rest of the kernel */ 77 struct cfattach flsc_ca = { 78 sizeof(struct flsc_softc), flscmatch, flscattach 79 }; 80 81 struct scsipi_adapter flsc_switch = { 82 ncr53c9x_scsi_cmd, 83 minphys, /* no max at this level; handled by DMA code */ 84 NULL, /* scsipi_ioctl */ 85 }; 86 87 struct scsipi_device flsc_dev = { 88 NULL, /* Use default error handler */ 89 NULL, /* have a queue, served by this */ 90 NULL, /* have no async handler */ 91 NULL, /* Use default 'done' routine */ 92 }; 93 94 /* 95 * Functions and the switch for the MI code. 96 */ 97 u_char flsc_read_reg __P((struct ncr53c9x_softc *, int)); 98 void flsc_write_reg __P((struct ncr53c9x_softc *, int, u_char)); 99 int flsc_dma_isintr __P((struct ncr53c9x_softc *)); 100 void flsc_dma_reset __P((struct ncr53c9x_softc *)); 101 int flsc_dma_intr __P((struct ncr53c9x_softc *)); 102 int flsc_dma_setup __P((struct ncr53c9x_softc *, caddr_t *, 103 size_t *, int, size_t *)); 104 void flsc_dma_go __P((struct ncr53c9x_softc *)); 105 void flsc_dma_stop __P((struct ncr53c9x_softc *)); 106 int flsc_dma_isactive __P((struct ncr53c9x_softc *)); 107 void flsc_clear_latched_intr __P((struct ncr53c9x_softc *)); 108 109 struct ncr53c9x_glue flsc_glue = { 110 flsc_read_reg, 111 flsc_write_reg, 112 flsc_dma_isintr, 113 flsc_dma_reset, 114 flsc_dma_intr, 115 flsc_dma_setup, 116 flsc_dma_go, 117 flsc_dma_stop, 118 flsc_dma_isactive, 119 flsc_clear_latched_intr, 120 }; 121 122 /* Maximum DMA transfer length to reduce impact on high-speed serial input */ 123 u_long flsc_max_dma = 1024; 124 extern int ser_open_speed; 125 126 extern int ncr53c9x_debug; 127 extern u_long scsi_nosync; 128 extern int shift_nosync; 129 130 /* 131 * if we are an Advanced Systems & Software FastlaneZ3 132 */ 133 int 134 flscmatch(parent, cf, aux) 135 struct device *parent; 136 struct cfdata *cf; 137 void *aux; 138 { 139 struct zbus_args *zap; 140 141 if (!is_a4000() && !is_a3000()) 142 return(0); 143 144 zap = aux; 145 if (zap->manid == 0x2140 && zap->prodid == 11 146 && iszthreepa(zap->pa)) 147 return(1); 148 149 return(0); 150 } 151 152 /* 153 * Attach this instance, and then all the sub-devices 154 */ 155 void 156 flscattach(parent, self, aux) 157 struct device *parent, *self; 158 void *aux; 159 { 160 struct flsc_softc *fsc = (void *)self; 161 struct ncr53c9x_softc *sc = &fsc->sc_ncr53c9x; 162 struct zbus_args *zap; 163 164 /* 165 * Set up the glue for MI code early; we use some of it here. 166 */ 167 sc->sc_glue = &flsc_glue; 168 169 /* 170 * Save the regs 171 */ 172 zap = aux; 173 fsc->sc_dmabase = (volatile u_char *)zap->va; 174 fsc->sc_reg = &((volatile u_char *)zap->va)[0x1000001]; 175 176 sc->sc_freq = 40; /* Clocked at 40Mhz */ 177 178 printf(": address %p", fsc->sc_reg); 179 180 sc->sc_id = 7; 181 182 /* 183 * It is necessary to try to load the 2nd config register here, 184 * to find out what rev the flsc chip is, else the flsc_reset 185 * will not set up the defaults correctly. 186 */ 187 sc->sc_cfg1 = sc->sc_id | NCRCFG1_PARENB; 188 sc->sc_cfg2 = NCRCFG2_SCSI2 | NCRCFG2_FE; 189 sc->sc_cfg3 = 0x08 /*FCLK*/ | NCRESPCFG3_FSCSI | NCRESPCFG3_CDB; 190 sc->sc_rev = NCR_VARIANT_FAS216; 191 192 /* 193 * This is the value used to start sync negotiations 194 * Note that the NCR register "SYNCTP" is programmed 195 * in "clocks per byte", and has a minimum value of 4. 196 * The SCSI period used in negotiation is one-fourth 197 * of the time (in nanoseconds) needed to transfer one byte. 198 * Since the chip's clock is given in MHz, we have the following 199 * formula: 4 * period = (1000 / freq) * 4 200 */ 201 sc->sc_minsync = 1000 / sc->sc_freq; 202 203 if (((scsi_nosync >> shift_nosync) & 0xff00) == 0xff00) 204 sc->sc_minsync = 0; 205 206 /* Really no limit, but since we want to fit into the TCR... */ 207 sc->sc_maxxfer = 64 * 1024; 208 209 fsc->sc_portbits = 0xa0 | FLSC_PB_EDI | FLSC_PB_ESI; 210 fsc->sc_hardbits = fsc->sc_reg[0x40]; 211 212 fsc->sc_alignbuf = (char *)((u_long)fsc->sc_unalignbuf & -4); 213 214 sc->sc_dev.dv_cfdata->cf_flags |= (scsi_nosync >> shift_nosync) & 0xffff; 215 shift_nosync += 16; 216 ncr53c9x_debug |= (scsi_nosync >> shift_nosync) & 0xffff; 217 shift_nosync += 16; 218 219 /* 220 * Configure interrupts. 221 */ 222 fsc->sc_isr.isr_intr = (int (*)(void *))ncr53c9x_intr; 223 fsc->sc_isr.isr_arg = sc; 224 fsc->sc_isr.isr_ipl = 2; 225 add_isr(&fsc->sc_isr); 226 227 fsc->sc_reg[0x40] = fsc->sc_portbits; 228 229 /* 230 * Now try to attach all the sub-devices 231 */ 232 ncr53c9x_attach(sc, &flsc_switch, &flsc_dev); 233 } 234 235 /* 236 * Glue functions. 237 */ 238 239 u_char 240 flsc_read_reg(sc, reg) 241 struct ncr53c9x_softc *sc; 242 int reg; 243 { 244 struct flsc_softc *fsc = (struct flsc_softc *)sc; 245 246 return fsc->sc_reg[reg * 4]; 247 } 248 249 void 250 flsc_write_reg(sc, reg, val) 251 struct ncr53c9x_softc *sc; 252 int reg; 253 u_char val; 254 { 255 struct flsc_softc *fsc = (struct flsc_softc *)sc; 256 struct ncr53c9x_tinfo *ti; 257 u_char v = val; 258 259 if (fsc->sc_piomode && reg == NCR_CMD && 260 v == (NCRCMD_TRANS|NCRCMD_DMA)) { 261 v = NCRCMD_TRANS; 262 } 263 /* 264 * Can't do synchronous transfers in SCSI_POLL mode: 265 * If starting SCSI_POLL command, clear defer sync negotiation 266 * by clearing the T_NEGOTIATE flag. If starting SCSI_POLL and 267 * the device is currently running synchronous, force another 268 * T_NEGOTIATE with 0 offset. 269 */ 270 if (reg == NCR_SELID) { 271 ti = &sc->sc_tinfo[ 272 sc->sc_nexus->xs->sc_link->scsipi_scsi.target]; 273 if (sc->sc_nexus->xs->flags & SCSI_POLL) { 274 if (ti->flags & T_SYNCMODE) { 275 ti->flags ^= T_SYNCMODE | T_NEGOTIATE; 276 } else if (ti->flags & T_NEGOTIATE) { 277 ti->flags ^= T_NEGOTIATE | T_SYNCHOFF; 278 /* save T_NEGOTIATE in private flags? */ 279 } 280 } else { 281 /* 282 * If we haven't attempted sync negotiation yet, 283 * do it now. 284 */ 285 if ((ti->flags & (T_SYNCMODE | T_SYNCHOFF)) == 286 T_SYNCHOFF && 287 sc->sc_minsync != 0) /* XXX */ 288 ti->flags ^= T_NEGOTIATE | T_SYNCHOFF; 289 } 290 } 291 if (reg == NCR_CMD && v == NCRCMD_SETATN && 292 sc->sc_flags & NCR_SYNCHNEGO && 293 sc->sc_nexus->xs->flags & SCSI_POLL) { 294 ti = &sc->sc_tinfo[ 295 sc->sc_nexus->xs->sc_link->scsipi_scsi.target]; 296 ti->offset = 0; 297 } 298 fsc->sc_reg[reg * 4] = v; 299 } 300 301 int 302 flsc_dma_isintr(sc) 303 struct ncr53c9x_softc *sc; 304 { 305 struct flsc_softc *fsc = (struct flsc_softc *)sc; 306 unsigned hardbits; 307 308 hardbits = fsc->sc_reg[0x40]; 309 if (hardbits & FLSC_HB_IACT) 310 return (fsc->sc_csr = 0); 311 312 if (sc->sc_state == NCR_CONNECTED || sc->sc_state == NCR_SELECTING) 313 fsc->sc_portbits |= FLSC_PB_LED; 314 else 315 fsc->sc_portbits &= ~FLSC_PB_LED; 316 317 if ((hardbits & FLSC_HB_CREQ) && !(hardbits & FLSC_HB_MINT) && 318 fsc->sc_reg[NCR_STAT * 4] & NCRSTAT_INT) { 319 return 1; 320 } 321 /* Do I still need this? */ 322 if (fsc->sc_piomode && fsc->sc_reg[NCR_STAT * 4] & NCRSTAT_INT && 323 !(hardbits & FLSC_HB_MINT)) 324 return 1; 325 326 fsc->sc_reg[0x40] = fsc->sc_portbits & ~FLSC_PB_INT_BITS; 327 fsc->sc_reg[0x40] = fsc->sc_portbits; 328 return 0; 329 } 330 331 void 332 flsc_clear_latched_intr(sc) 333 struct ncr53c9x_softc *sc; 334 { 335 struct flsc_softc *fsc = (struct flsc_softc *)sc; 336 337 fsc->sc_reg[0x40] = fsc->sc_portbits & ~FLSC_PB_INT_BITS; 338 fsc->sc_reg[0x40] = fsc->sc_portbits; 339 } 340 341 void 342 flsc_dma_reset(sc) 343 struct ncr53c9x_softc *sc; 344 { 345 struct flsc_softc *fsc = (struct flsc_softc *)sc; 346 struct ncr53c9x_tinfo *ti; 347 348 if (sc->sc_nexus) 349 ti = &sc->sc_tinfo[sc->sc_nexus->xs->sc_link->scsipi_scsi.target]; 350 else 351 ti = &sc->sc_tinfo[1]; /* XXX */ 352 if (fsc->sc_active) { 353 printf("dmaaddr %p dmasize %d stat %x flags %x off %d per %d ff %x", 354 *fsc->sc_dmaaddr, fsc->sc_dmasize, fsc->sc_reg[NCR_STAT * 4], 355 ti->flags, ti->offset, ti->period, fsc->sc_reg[NCR_FFLAG * 4]); 356 printf(" intr %x\n", fsc->sc_reg[NCR_INTR * 4]); 357 #ifdef DDB 358 Debugger(); 359 #endif 360 } 361 fsc->sc_portbits &= ~FLSC_PB_DMA_BITS; 362 fsc->sc_reg[0x40] = fsc->sc_portbits; 363 fsc->sc_reg[0x80] = 0; 364 *((u_long *)fsc->sc_dmabase) = 0; 365 fsc->sc_active = 0; 366 fsc->sc_piomode = 0; 367 } 368 369 int 370 flsc_dma_intr(sc) 371 struct ncr53c9x_softc *sc; 372 { 373 register struct flsc_softc *fsc = (struct flsc_softc *)sc; 374 register u_char *p; 375 volatile u_char *cmdreg, *intrreg, *statreg, *fiforeg; 376 register u_int flscphase, flscstat, flscintr; 377 register int cnt; 378 379 NCR_DMA(("flsc_dma_intr: pio %d cnt %d int %x stat %x fifo %d ", 380 fsc->sc_piomode, fsc->sc_dmasize, sc->sc_espintr, sc->sc_espstat, 381 fsc->sc_reg[NCR_FFLAG * 4] & NCRFIFO_FF)); 382 if (!(fsc->sc_reg[0x40] & FLSC_HB_CREQ)) 383 printf("flsc_dma_intr: csr %x stat %x intr %x\n", fsc->sc_csr, 384 sc->sc_espstat, sc->sc_espintr); 385 if (fsc->sc_active == 0) { 386 printf("flsc_intr--inactive DMA\n"); 387 return -1; 388 } 389 390 /* if DMA transfer, update sc_dmaaddr and sc_pdmalen, else PIO xfer */ 391 if (fsc->sc_piomode == 0) { 392 fsc->sc_portbits &= ~FLSC_PB_DMA_BITS; 393 fsc->sc_reg[0x40] = fsc->sc_portbits; 394 fsc->sc_reg[0x80] = 0; 395 *((u_long *)fsc->sc_dmabase) = 0; 396 cnt = fsc->sc_reg[NCR_TCL * 4]; 397 cnt += fsc->sc_reg[NCR_TCM * 4] << 8; 398 cnt += fsc->sc_reg[NCR_TCH * 4] << 16; 399 if (!fsc->sc_datain) { 400 cnt += fsc->sc_reg[NCR_FFLAG * 4] & NCRFIFO_FF; 401 fsc->sc_reg[NCR_CMD * 4] = NCRCMD_FLUSH; 402 } 403 cnt = fsc->sc_dmasize - cnt; /* number of bytes transferred */ 404 NCR_DMA(("DMA xferred %d\n", cnt)); 405 if (fsc->sc_xfr_align) { 406 int i; 407 for (i = 0; i < cnt; ++i) 408 (*fsc->sc_dmaaddr)[i] = fsc->sc_alignbuf[i]; 409 fsc->sc_xfr_align = 0; 410 } 411 *fsc->sc_dmaaddr += cnt; 412 *fsc->sc_pdmalen -= cnt; 413 fsc->sc_active = 0; 414 return 0; 415 } 416 417 if ((sc->sc_espintr & NCRINTR_BS) == 0) { 418 fsc->sc_active = 0; 419 fsc->sc_piomode = 0; 420 NCR_DMA(("no NCRINTR_BS\n")); 421 return 0; 422 } 423 424 cnt = fsc->sc_dmasize; 425 #if 0 426 if (cnt == 0) { 427 printf("data interrupt, but no count left."); 428 } 429 #endif 430 431 p = *fsc->sc_dmaaddr; 432 flscphase = sc->sc_phase; 433 flscstat = (u_int) sc->sc_espstat; 434 flscintr = (u_int) sc->sc_espintr; 435 cmdreg = fsc->sc_reg + NCR_CMD * 4; 436 fiforeg = fsc->sc_reg + NCR_FIFO * 4; 437 statreg = fsc->sc_reg + NCR_STAT * 4; 438 intrreg = fsc->sc_reg + NCR_INTR * 4; 439 NCR_DMA(("PIO %d datain %d phase %d stat %x intr %x\n", 440 cnt, fsc->sc_datain, flscphase, flscstat, flscintr)); 441 do { 442 if (fsc->sc_datain) { 443 *p++ = *fiforeg; 444 cnt--; 445 if (flscphase == DATA_IN_PHASE) { 446 *cmdreg = NCRCMD_TRANS; 447 } else { 448 fsc->sc_active = 0; 449 } 450 } else { 451 NCR_DMA(("flsc_dma_intr: PIO out- phase %d cnt %d active %d\n", flscphase, cnt, 452 fsc->sc_active)); 453 if ( (flscphase == DATA_OUT_PHASE) 454 || (flscphase == MESSAGE_OUT_PHASE)) { 455 int n; 456 n = 16 - (fsc->sc_reg[NCR_FFLAG * 4] & NCRFIFO_FF); 457 if (n > cnt) 458 n = cnt; 459 cnt -= n; 460 while (n-- > 0) 461 *fiforeg = *p++; 462 *cmdreg = NCRCMD_TRANS; 463 } else { 464 fsc->sc_active = 0; 465 } 466 } 467 468 if (fsc->sc_active && cnt) { 469 while (!(*statreg & 0x80)); 470 flscstat = *statreg; 471 flscintr = *intrreg; 472 flscphase = (flscintr & NCRINTR_DIS) 473 ? /* Disconnected */ BUSFREE_PHASE 474 : flscstat & PHASE_MASK; 475 } 476 } while (cnt && fsc->sc_active && (flscintr & NCRINTR_BS)); 477 #if 1 478 if (fsc->sc_dmasize < 8 && cnt) 479 printf("flsc_dma_intr: short transfer: dmasize %d cnt %d\n", 480 fsc->sc_dmasize, cnt); 481 #endif 482 NCR_DMA(("flsc_dma_intr: PIO transfer [%d], %d->%d phase %d stat %x intr %x\n", 483 *fsc->sc_pdmalen, fsc->sc_dmasize, cnt, flscphase, flscstat, flscintr)); 484 sc->sc_phase = flscphase; 485 sc->sc_espstat = (u_char) flscstat; 486 sc->sc_espintr = (u_char) flscintr; 487 *fsc->sc_dmaaddr = p; 488 *fsc->sc_pdmalen -= fsc->sc_dmasize - cnt; 489 fsc->sc_dmasize = cnt; 490 491 if (*fsc->sc_pdmalen == 0) { 492 sc->sc_espstat |= NCRSTAT_TC; 493 fsc->sc_piomode = 0; 494 } 495 return 0; 496 } 497 498 int 499 flsc_dma_setup(sc, addr, len, datain, dmasize) 500 struct ncr53c9x_softc *sc; 501 caddr_t *addr; 502 size_t *len; 503 int datain; 504 size_t *dmasize; 505 { 506 struct flsc_softc *fsc = (struct flsc_softc *)sc; 507 vm_offset_t pa; 508 u_char *ptr; 509 size_t xfer; 510 511 fsc->sc_dmaaddr = addr; 512 fsc->sc_pdmalen = len; 513 fsc->sc_datain = datain; 514 fsc->sc_dmasize = *dmasize; 515 if (sc->sc_nexus->xs->flags & SCSI_POLL) { 516 /* polling mode, use PIO */ 517 *dmasize = fsc->sc_dmasize; 518 NCR_DMA(("pfsc_dma_setup: PIO %p/%d [%d]\n", *addr, 519 fsc->sc_dmasize, *len)); 520 fsc->sc_piomode = 1; 521 if (datain == 0) { 522 int n; 523 n = fsc->sc_dmasize; 524 if (n > 16) 525 n = 16; 526 while (n-- > 0) { 527 fsc->sc_reg[NCR_FIFO * 4] = **fsc->sc_dmaaddr; 528 (*fsc->sc_pdmalen)--; 529 (*fsc->sc_dmaaddr)++; 530 --fsc->sc_dmasize; 531 } 532 } 533 return 0; 534 } 535 /* 536 * DMA can be nasty for high-speed serial input, so limit the 537 * size of this DMA operation if the serial port is running at 538 * a high speed (higher than 19200 for now - should be adjusted 539 * based on cpu type and speed?). 540 * XXX - add serial speed check XXX 541 */ 542 if (ser_open_speed > 19200 && flsc_max_dma != 0 && 543 fsc->sc_dmasize > flsc_max_dma) 544 fsc->sc_dmasize = flsc_max_dma; 545 ptr = *addr; /* Kernel virtual address */ 546 pa = kvtop(ptr); /* Physical address of DMA */ 547 xfer = min(fsc->sc_dmasize, NBPG - (pa & (NBPG - 1))); 548 fsc->sc_xfr_align = 0; 549 fsc->sc_piomode = 0; 550 fsc->sc_portbits &= ~FLSC_PB_DMA_BITS; 551 fsc->sc_reg[0x40] = fsc->sc_portbits; 552 fsc->sc_reg[0x80] = 0; 553 *((u_long *)fsc->sc_dmabase) = 0; 554 555 /* 556 * If output and length < 16, copy to fifo 557 */ 558 if (datain == 0 && fsc->sc_dmasize < 16) { 559 int n; 560 for (n = 0; n < fsc->sc_dmasize; ++n) 561 fsc->sc_reg[NCR_FIFO * 4] = *ptr++; 562 NCR_DMA(("flsc_dma_setup: %d bytes written to fifo\n", n)); 563 fsc->sc_piomode = 1; 564 fsc->sc_active = 1; 565 *fsc->sc_pdmalen -= fsc->sc_dmasize; 566 *fsc->sc_dmaaddr += fsc->sc_dmasize; 567 *dmasize = fsc->sc_dmasize; 568 fsc->sc_dmasize = 0; 569 return 0; /* All done */ 570 } 571 /* 572 * If output and unaligned, copy unaligned data to fifo 573 */ 574 else if (datain == 0 && (int)ptr & 3) { 575 int n = 4 - ((int)ptr & 3); 576 NCR_DMA(("flsc_dma_setup: align %d bytes written to fifo\n", n)); 577 pa += n; 578 xfer -= n; 579 while (n--) 580 fsc->sc_reg[NCR_FIFO * 4] = *ptr++; 581 } 582 /* 583 * If unaligned address, read unaligned bytes into alignment buffer 584 */ 585 else if ((int)ptr & 3 || xfer & 3) { 586 pa = kvtop((caddr_t)fsc->sc_alignbuf); 587 xfer = fsc->sc_dmasize = min(xfer, sizeof (fsc->sc_unalignbuf)); 588 NCR_DMA(("flsc_dma_setup: align read by %d bytes\n", xfer)); 589 fsc->sc_xfr_align = 1; 590 } 591 /* 592 * If length smaller than longword, read into alignment buffer 593 * XXX doesn't work for 1 or 2 bytes !!!! 594 */ 595 else if (fsc->sc_dmasize < 4) { 596 NCR_DMA(("flsc_dma_setup: read remaining %d bytes\n", 597 fsc->sc_dmasize)); 598 pa = kvtop((caddr_t)fsc->sc_alignbuf); 599 fsc->sc_xfr_align = 1; 600 } 601 /* 602 * Finally, limit transfer length to multiple of 4 bytes. 603 */ 604 else { 605 fsc->sc_dmasize &= -4; 606 xfer &= -4; 607 } 608 609 while (xfer < fsc->sc_dmasize) { 610 if ((pa + xfer) != kvtop(*addr + xfer)) 611 break; 612 if ((fsc->sc_dmasize - xfer) < NBPG) 613 xfer = fsc->sc_dmasize; 614 else 615 xfer += NBPG; 616 } 617 618 fsc->sc_dmasize = xfer; 619 *dmasize = fsc->sc_dmasize; 620 fsc->sc_pa = pa; 621 #if defined(M68040) || defined(M68060) 622 if (mmutype == MMU_68040) { 623 if (fsc->sc_xfr_align) { 624 int n; 625 for (n = 0; n < sizeof (fsc->sc_unalignbuf); ++n) 626 fsc->sc_alignbuf[n] = n | 0x80; 627 dma_cachectl(fsc->sc_alignbuf, 628 sizeof(fsc->sc_unalignbuf)); 629 } 630 else 631 dma_cachectl(*fsc->sc_dmaaddr, fsc->sc_dmasize); 632 } 633 #endif 634 fsc->sc_reg[0x80] = 0; 635 *((u_long *)(fsc->sc_dmabase + (pa & 0x00fffffc))) = pa; 636 fsc->sc_portbits &= ~FLSC_PB_DMA_BITS; 637 fsc->sc_portbits |= FLSC_PB_ENABLE_DMA | 638 (fsc->sc_datain ? FLSC_PB_DMA_READ : FLSC_PB_DMA_WRITE); 639 fsc->sc_reg[0x40] = fsc->sc_portbits; 640 NCR_DMA(("flsc_dma_setup: DMA %p->%lx/%d [%d]\n", 641 ptr, pa, fsc->sc_dmasize, *len)); 642 fsc->sc_active = 1; 643 return 0; 644 } 645 646 void 647 flsc_dma_go(sc) 648 struct ncr53c9x_softc *sc; 649 { 650 struct flsc_softc *fsc = (struct flsc_softc *)sc; 651 652 NCR_DMA(("flsc_dma_go: datain %d size %d\n", fsc->sc_datain, 653 fsc->sc_dmasize)); 654 if (sc->sc_nexus->xs->flags & SCSI_POLL) { 655 fsc->sc_active = 1; 656 return; 657 } else if (fsc->sc_piomode == 0) { 658 fsc->sc_portbits &= ~FLSC_PB_DMA_BITS; 659 fsc->sc_portbits |= FLSC_PB_ENABLE_DMA | 660 (fsc->sc_datain ? FLSC_PB_DMA_READ : FLSC_PB_DMA_WRITE); 661 fsc->sc_reg[0x40] = fsc->sc_portbits; 662 } 663 } 664 665 void 666 flsc_dma_stop(sc) 667 struct ncr53c9x_softc *sc; 668 { 669 struct flsc_softc *fsc = (struct flsc_softc *)sc; 670 671 fsc->sc_portbits &= ~FLSC_PB_DMA_BITS; 672 fsc->sc_reg[0x40] = fsc->sc_portbits; 673 674 fsc->sc_reg[0x80] = 0; 675 *((u_long *)fsc->sc_dmabase) = 0; 676 fsc->sc_piomode = 0; 677 } 678 679 int 680 flsc_dma_isactive(sc) 681 struct ncr53c9x_softc *sc; 682 { 683 struct flsc_softc *fsc = (struct flsc_softc *)sc; 684 685 return fsc->sc_active; 686 } 687
Indexes created Thu Oct 02 14:10:14 GMT 2025