flsc.c revision 1.26
1 /* $NetBSD: flsc.c,v 1.26 2000/06/05 15:08:02 tsutsui Exp $ */ 2 3 /* 4 * Copyright (c) 1997 Michael L. Hitch 5 * Copyright (c) 1995 Daniel Widenfalk 6 * Copyright (c) 1994 Christian E. Hopps 7 * Copyright (c) 1982, 1990 The Regents of the University of California. 8 * All rights reserved. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 3. All advertising materials mentioning features or use of this software 19 * must display the following acknowledgement: 20 * This product includes software developed by Daniel Widenfalk 21 * and Michael L. Hitch. 22 * 4. Neither the name of the University nor the names of its contributors 23 * may be used to endorse or promote products derived from this software 24 * without specific prior written permission. 25 * 26 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 27 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 28 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 29 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 30 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 31 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 32 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 33 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 34 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 35 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 36 * SUCH DAMAGE. 37 */ 38 39 /* 40 * Initial amiga Fastlane driver by Daniel Widenfalk. Conversion to 41 * 53c9x MI driver by Michael L. Hitch (mhitch (at) montana.edu). 42 */ 43 44 #include "opt_ddb.h" 45 46 #include <sys/types.h> 47 #include <sys/param.h> 48 #include <sys/systm.h> 49 #include <sys/kernel.h> 50 #include <sys/errno.h> 51 #include <sys/ioctl.h> 52 #include <sys/device.h> 53 #include <sys/buf.h> 54 #include <sys/proc.h> 55 #include <sys/user.h> 56 #include <sys/queue.h> 57 58 #include <dev/scsipi/scsi_all.h> 59 #include <dev/scsipi/scsipi_all.h> 60 #include <dev/scsipi/scsiconf.h> 61 #include <dev/scsipi/scsi_message.h> 62 63 #include <machine/cpu.h> 64 #include <machine/param.h> 65 66 #include <dev/ic/ncr53c9xreg.h> 67 #include <dev/ic/ncr53c9xvar.h> 68 69 #include <amiga/amiga/isr.h> 70 #include <amiga/dev/flscvar.h> 71 #include <amiga/dev/zbusvar.h> 72 73 void flscattach __P((struct device *, struct device *, void *)); 74 int flscmatch __P((struct device *, struct cfdata *, void *)); 75 76 /* Linkup to the rest of the kernel */ 77 struct cfattach flsc_ca = { 78 sizeof(struct flsc_softc), flscmatch, flscattach 79 }; 80 81 /* 82 * Functions and the switch for the MI code. 83 */ 84 u_char flsc_read_reg __P((struct ncr53c9x_softc *, int)); 85 void flsc_write_reg __P((struct ncr53c9x_softc *, int, u_char)); 86 int flsc_dma_isintr __P((struct ncr53c9x_softc *)); 87 void flsc_dma_reset __P((struct ncr53c9x_softc *)); 88 int flsc_dma_intr __P((struct ncr53c9x_softc *)); 89 int flsc_dma_setup __P((struct ncr53c9x_softc *, caddr_t *, 90 size_t *, int, size_t *)); 91 void flsc_dma_go __P((struct ncr53c9x_softc *)); 92 void flsc_dma_stop __P((struct ncr53c9x_softc *)); 93 int flsc_dma_isactive __P((struct ncr53c9x_softc *)); 94 void flsc_clear_latched_intr __P((struct ncr53c9x_softc *)); 95 96 struct ncr53c9x_glue flsc_glue = { 97 flsc_read_reg, 98 flsc_write_reg, 99 flsc_dma_isintr, 100 flsc_dma_reset, 101 flsc_dma_intr, 102 flsc_dma_setup, 103 flsc_dma_go, 104 flsc_dma_stop, 105 flsc_dma_isactive, 106 flsc_clear_latched_intr, 107 }; 108 109 /* Maximum DMA transfer length to reduce impact on high-speed serial input */ 110 u_long flsc_max_dma = 1024; 111 extern int ser_open_speed; 112 113 extern int ncr53c9x_debug; 114 extern u_long scsi_nosync; 115 extern int shift_nosync; 116 117 /* 118 * if we are an Advanced Systems & Software FastlaneZ3 119 */ 120 int 121 flscmatch(parent, cf, aux) 122 struct device *parent; 123 struct cfdata *cf; 124 void *aux; 125 { 126 struct zbus_args *zap; 127 128 if (!is_a4000() && !is_a3000()) 129 return(0); 130 131 zap = aux; 132 if (zap->manid == 0x2140 && zap->prodid == 11 133 && iszthreepa(zap->pa)) 134 return(1); 135 136 return(0); 137 } 138 139 /* 140 * Attach this instance, and then all the sub-devices 141 */ 142 void 143 flscattach(parent, self, aux) 144 struct device *parent, *self; 145 void *aux; 146 { 147 struct flsc_softc *fsc = (void *)self; 148 struct ncr53c9x_softc *sc = &fsc->sc_ncr53c9x; 149 struct zbus_args *zap; 150 151 /* 152 * Set up the glue for MI code early; we use some of it here. 153 */ 154 sc->sc_glue = &flsc_glue; 155 156 /* 157 * Save the regs 158 */ 159 zap = aux; 160 fsc->sc_dmabase = (volatile u_char *)zap->va; 161 fsc->sc_reg = &((volatile u_char *)zap->va)[0x1000001]; 162 163 sc->sc_freq = 40; /* Clocked at 40Mhz */ 164 165 printf(": address %p", fsc->sc_reg); 166 167 sc->sc_id = 7; 168 169 /* 170 * It is necessary to try to load the 2nd config register here, 171 * to find out what rev the flsc chip is, else the flsc_reset 172 * will not set up the defaults correctly. 173 */ 174 sc->sc_cfg1 = sc->sc_id | NCRCFG1_PARENB; 175 sc->sc_cfg2 = NCRCFG2_SCSI2 | NCRCFG2_FE; 176 sc->sc_cfg3 = 0x08 /*FCLK*/ | NCRESPCFG3_FSCSI | NCRESPCFG3_CDB; 177 sc->sc_rev = NCR_VARIANT_FAS216; 178 179 /* 180 * This is the value used to start sync negotiations 181 * Note that the NCR register "SYNCTP" is programmed 182 * in "clocks per byte", and has a minimum value of 4. 183 * The SCSI period used in negotiation is one-fourth 184 * of the time (in nanoseconds) needed to transfer one byte. 185 * Since the chip's clock is given in MHz, we have the following 186 * formula: 4 * period = (1000 / freq) * 4 187 */ 188 sc->sc_minsync = 1000 / sc->sc_freq; 189 190 if (((scsi_nosync >> shift_nosync) & 0xff00) == 0xff00) 191 sc->sc_minsync = 0; 192 193 /* Really no limit, but since we want to fit into the TCR... */ 194 sc->sc_maxxfer = 64 * 1024; 195 196 fsc->sc_portbits = 0xa0 | FLSC_PB_EDI | FLSC_PB_ESI; 197 fsc->sc_hardbits = fsc->sc_reg[0x40]; 198 199 fsc->sc_alignbuf = (char *)((u_long)fsc->sc_unalignbuf & -4); 200 201 sc->sc_dev.dv_cfdata->cf_flags |= (scsi_nosync >> shift_nosync) & 0xffff; 202 shift_nosync += 16; 203 ncr53c9x_debug |= (scsi_nosync >> shift_nosync) & 0xffff; 204 shift_nosync += 16; 205 206 /* 207 * Configure interrupts. 208 */ 209 fsc->sc_isr.isr_intr = ncr53c9x_intr; 210 fsc->sc_isr.isr_arg = sc; 211 fsc->sc_isr.isr_ipl = 2; 212 add_isr(&fsc->sc_isr); 213 214 fsc->sc_reg[0x40] = fsc->sc_portbits; 215 216 /* 217 * Now try to attach all the sub-devices 218 */ 219 ncr53c9x_attach(sc, NULL, NULL); 220 } 221 222 /* 223 * Glue functions. 224 */ 225 226 u_char 227 flsc_read_reg(sc, reg) 228 struct ncr53c9x_softc *sc; 229 int reg; 230 { 231 struct flsc_softc *fsc = (struct flsc_softc *)sc; 232 233 return fsc->sc_reg[reg * 4]; 234 } 235 236 void 237 flsc_write_reg(sc, reg, val) 238 struct ncr53c9x_softc *sc; 239 int reg; 240 u_char val; 241 { 242 struct flsc_softc *fsc = (struct flsc_softc *)sc; 243 struct ncr53c9x_tinfo *ti; 244 u_char v = val; 245 246 if (fsc->sc_piomode && reg == NCR_CMD && 247 v == (NCRCMD_TRANS|NCRCMD_DMA)) { 248 v = NCRCMD_TRANS; 249 } 250 /* 251 * Can't do synchronous transfers in XS_CTL_POLL mode: 252 * If starting XS_CTL_POLL command, clear defer sync negotiation 253 * by clearing the T_NEGOTIATE flag. If starting XS_CTL_POLL and 254 * the device is currently running synchronous, force another 255 * T_NEGOTIATE with 0 offset. 256 */ 257 if (reg == NCR_SELID) { 258 ti = &sc->sc_tinfo[ 259 sc->sc_nexus->xs->sc_link->scsipi_scsi.target]; 260 if (sc->sc_nexus->xs->xs_control & XS_CTL_POLL) { 261 if (ti->flags & T_SYNCMODE) { 262 ti->flags ^= T_SYNCMODE | T_NEGOTIATE; 263 } else if (ti->flags & T_NEGOTIATE) { 264 ti->flags ^= T_NEGOTIATE | T_SYNCHOFF; 265 /* save T_NEGOTIATE in private flags? */ 266 } 267 } else { 268 /* 269 * If we haven't attempted sync negotiation yet, 270 * do it now. 271 */ 272 if ((ti->flags & (T_SYNCMODE | T_SYNCHOFF)) == 273 T_SYNCHOFF && 274 sc->sc_minsync != 0) /* XXX */ 275 ti->flags ^= T_NEGOTIATE | T_SYNCHOFF; 276 } 277 } 278 if (reg == NCR_CMD && v == NCRCMD_SETATN && 279 sc->sc_flags & NCR_SYNCHNEGO && 280 sc->sc_nexus->xs->xs_control & XS_CTL_POLL) { 281 ti = &sc->sc_tinfo[ 282 sc->sc_nexus->xs->sc_link->scsipi_scsi.target]; 283 ti->offset = 0; 284 } 285 fsc->sc_reg[reg * 4] = v; 286 } 287 288 int 289 flsc_dma_isintr(sc) 290 struct ncr53c9x_softc *sc; 291 { 292 struct flsc_softc *fsc = (struct flsc_softc *)sc; 293 unsigned hardbits; 294 295 hardbits = fsc->sc_reg[0x40]; 296 if (hardbits & FLSC_HB_IACT) 297 return (fsc->sc_csr = 0); 298 299 if (sc->sc_state == NCR_CONNECTED || sc->sc_state == NCR_SELECTING) 300 fsc->sc_portbits |= FLSC_PB_LED; 301 else 302 fsc->sc_portbits &= ~FLSC_PB_LED; 303 304 if ((hardbits & FLSC_HB_CREQ) && !(hardbits & FLSC_HB_MINT) && 305 fsc->sc_reg[NCR_STAT * 4] & NCRSTAT_INT) { 306 return 1; 307 } 308 /* Do I still need this? */ 309 if (fsc->sc_piomode && fsc->sc_reg[NCR_STAT * 4] & NCRSTAT_INT && 310 !(hardbits & FLSC_HB_MINT)) 311 return 1; 312 313 fsc->sc_reg[0x40] = fsc->sc_portbits & ~FLSC_PB_INT_BITS; 314 fsc->sc_reg[0x40] = fsc->sc_portbits; 315 return 0; 316 } 317 318 void 319 flsc_clear_latched_intr(sc) 320 struct ncr53c9x_softc *sc; 321 { 322 struct flsc_softc *fsc = (struct flsc_softc *)sc; 323 324 fsc->sc_reg[0x40] = fsc->sc_portbits & ~FLSC_PB_INT_BITS; 325 fsc->sc_reg[0x40] = fsc->sc_portbits; 326 } 327 328 void 329 flsc_dma_reset(sc) 330 struct ncr53c9x_softc *sc; 331 { 332 struct flsc_softc *fsc = (struct flsc_softc *)sc; 333 struct ncr53c9x_tinfo *ti; 334 335 if (sc->sc_nexus) 336 ti = &sc->sc_tinfo[sc->sc_nexus->xs->sc_link->scsipi_scsi.target]; 337 else 338 ti = &sc->sc_tinfo[1]; /* XXX */ 339 if (fsc->sc_active) { 340 printf("dmaaddr %p dmasize %d stat %x flags %x off %d per %d ff %x", 341 *fsc->sc_dmaaddr, fsc->sc_dmasize, fsc->sc_reg[NCR_STAT * 4], 342 ti->flags, ti->offset, ti->period, fsc->sc_reg[NCR_FFLAG * 4]); 343 printf(" intr %x\n", fsc->sc_reg[NCR_INTR * 4]); 344 #ifdef DDB 345 Debugger(); 346 #endif 347 } 348 fsc->sc_portbits &= ~FLSC_PB_DMA_BITS; 349 fsc->sc_reg[0x40] = fsc->sc_portbits; 350 fsc->sc_reg[0x80] = 0; 351 *((u_long *)fsc->sc_dmabase) = 0; 352 fsc->sc_active = 0; 353 fsc->sc_piomode = 0; 354 } 355 356 int 357 flsc_dma_intr(sc) 358 struct ncr53c9x_softc *sc; 359 { 360 register struct flsc_softc *fsc = (struct flsc_softc *)sc; 361 register u_char *p; 362 volatile u_char *cmdreg, *intrreg, *statreg, *fiforeg; 363 register u_int flscphase, flscstat, flscintr; 364 register int cnt; 365 366 NCR_DMA(("flsc_dma_intr: pio %d cnt %d int %x stat %x fifo %d ", 367 fsc->sc_piomode, fsc->sc_dmasize, sc->sc_espintr, sc->sc_espstat, 368 fsc->sc_reg[NCR_FFLAG * 4] & NCRFIFO_FF)); 369 if (!(fsc->sc_reg[0x40] & FLSC_HB_CREQ)) 370 printf("flsc_dma_intr: csr %x stat %x intr %x\n", fsc->sc_csr, 371 sc->sc_espstat, sc->sc_espintr); 372 if (fsc->sc_active == 0) { 373 printf("flsc_intr--inactive DMA\n"); 374 return -1; 375 } 376 377 /* if DMA transfer, update sc_dmaaddr and sc_pdmalen, else PIO xfer */ 378 if (fsc->sc_piomode == 0) { 379 fsc->sc_portbits &= ~FLSC_PB_DMA_BITS; 380 fsc->sc_reg[0x40] = fsc->sc_portbits; 381 fsc->sc_reg[0x80] = 0; 382 *((u_long *)fsc->sc_dmabase) = 0; 383 cnt = fsc->sc_reg[NCR_TCL * 4]; 384 cnt += fsc->sc_reg[NCR_TCM * 4] << 8; 385 cnt += fsc->sc_reg[NCR_TCH * 4] << 16; 386 if (!fsc->sc_datain) { 387 cnt += fsc->sc_reg[NCR_FFLAG * 4] & NCRFIFO_FF; 388 fsc->sc_reg[NCR_CMD * 4] = NCRCMD_FLUSH; 389 } 390 cnt = fsc->sc_dmasize - cnt; /* number of bytes transferred */ 391 NCR_DMA(("DMA xferred %d\n", cnt)); 392 if (fsc->sc_xfr_align) { 393 int i; 394 for (i = 0; i < cnt; ++i) 395 (*fsc->sc_dmaaddr)[i] = fsc->sc_alignbuf[i]; 396 fsc->sc_xfr_align = 0; 397 } 398 *fsc->sc_dmaaddr += cnt; 399 *fsc->sc_pdmalen -= cnt; 400 fsc->sc_active = 0; 401 return 0; 402 } 403 404 if ((sc->sc_espintr & NCRINTR_BS) == 0) { 405 fsc->sc_active = 0; 406 fsc->sc_piomode = 0; 407 NCR_DMA(("no NCRINTR_BS\n")); 408 return 0; 409 } 410 411 cnt = fsc->sc_dmasize; 412 #if 0 413 if (cnt == 0) { 414 printf("data interrupt, but no count left."); 415 } 416 #endif 417 418 p = *fsc->sc_dmaaddr; 419 flscphase = sc->sc_phase; 420 flscstat = (u_int) sc->sc_espstat; 421 flscintr = (u_int) sc->sc_espintr; 422 cmdreg = fsc->sc_reg + NCR_CMD * 4; 423 fiforeg = fsc->sc_reg + NCR_FIFO * 4; 424 statreg = fsc->sc_reg + NCR_STAT * 4; 425 intrreg = fsc->sc_reg + NCR_INTR * 4; 426 NCR_DMA(("PIO %d datain %d phase %d stat %x intr %x\n", 427 cnt, fsc->sc_datain, flscphase, flscstat, flscintr)); 428 do { 429 if (fsc->sc_datain) { 430 *p++ = *fiforeg; 431 cnt--; 432 if (flscphase == DATA_IN_PHASE) { 433 *cmdreg = NCRCMD_TRANS; 434 } else { 435 fsc->sc_active = 0; 436 } 437 } else { 438 NCR_DMA(("flsc_dma_intr: PIO out- phase %d cnt %d active %d\n", flscphase, cnt, 439 fsc->sc_active)); 440 if ( (flscphase == DATA_OUT_PHASE) 441 || (flscphase == MESSAGE_OUT_PHASE)) { 442 int n; 443 n = 16 - (fsc->sc_reg[NCR_FFLAG * 4] & NCRFIFO_FF); 444 if (n > cnt) 445 n = cnt; 446 cnt -= n; 447 while (n-- > 0) 448 *fiforeg = *p++; 449 *cmdreg = NCRCMD_TRANS; 450 } else { 451 fsc->sc_active = 0; 452 } 453 } 454 455 if (fsc->sc_active && cnt) { 456 while (!(*statreg & 0x80)); 457 flscstat = *statreg; 458 flscintr = *intrreg; 459 flscphase = (flscintr & NCRINTR_DIS) 460 ? /* Disconnected */ BUSFREE_PHASE 461 : flscstat & PHASE_MASK; 462 } 463 } while (cnt && fsc->sc_active && (flscintr & NCRINTR_BS)); 464 #if 1 465 if (fsc->sc_dmasize < 8 && cnt) 466 printf("flsc_dma_intr: short transfer: dmasize %d cnt %d\n", 467 fsc->sc_dmasize, cnt); 468 #endif 469 NCR_DMA(("flsc_dma_intr: PIO transfer [%d], %d->%d phase %d stat %x intr %x\n", 470 *fsc->sc_pdmalen, fsc->sc_dmasize, cnt, flscphase, flscstat, flscintr)); 471 sc->sc_phase = flscphase; 472 sc->sc_espstat = (u_char) flscstat; 473 sc->sc_espintr = (u_char) flscintr; 474 *fsc->sc_dmaaddr = p; 475 *fsc->sc_pdmalen -= fsc->sc_dmasize - cnt; 476 fsc->sc_dmasize = cnt; 477 478 if (*fsc->sc_pdmalen == 0) { 479 sc->sc_espstat |= NCRSTAT_TC; 480 fsc->sc_piomode = 0; 481 } 482 return 0; 483 } 484 485 int 486 flsc_dma_setup(sc, addr, len, datain, dmasize) 487 struct ncr53c9x_softc *sc; 488 caddr_t *addr; 489 size_t *len; 490 int datain; 491 size_t *dmasize; 492 { 493 struct flsc_softc *fsc = (struct flsc_softc *)sc; 494 paddr_t pa; 495 u_char *ptr; 496 size_t xfer; 497 498 fsc->sc_dmaaddr = addr; 499 fsc->sc_pdmalen = len; 500 fsc->sc_datain = datain; 501 fsc->sc_dmasize = *dmasize; 502 if (sc->sc_nexus->xs->xs_control & XS_CTL_POLL) { 503 /* polling mode, use PIO */ 504 *dmasize = fsc->sc_dmasize; 505 NCR_DMA(("pfsc_dma_setup: PIO %p/%d [%d]\n", *addr, 506 fsc->sc_dmasize, *len)); 507 fsc->sc_piomode = 1; 508 if (datain == 0) { 509 int n; 510 n = fsc->sc_dmasize; 511 if (n > 16) 512 n = 16; 513 while (n-- > 0) { 514 fsc->sc_reg[NCR_FIFO * 4] = **fsc->sc_dmaaddr; 515 (*fsc->sc_pdmalen)--; 516 (*fsc->sc_dmaaddr)++; 517 --fsc->sc_dmasize; 518 } 519 } 520 return 0; 521 } 522 /* 523 * DMA can be nasty for high-speed serial input, so limit the 524 * size of this DMA operation if the serial port is running at 525 * a high speed (higher than 19200 for now - should be adjusted 526 * based on cpu type and speed?). 527 * XXX - add serial speed check XXX 528 */ 529 if (ser_open_speed > 19200 && flsc_max_dma != 0 && 530 fsc->sc_dmasize > flsc_max_dma) 531 fsc->sc_dmasize = flsc_max_dma; 532 ptr = *addr; /* Kernel virtual address */ 533 pa = kvtop(ptr); /* Physical address of DMA */ 534 xfer = min(fsc->sc_dmasize, NBPG - (pa & (NBPG - 1))); 535 fsc->sc_xfr_align = 0; 536 fsc->sc_piomode = 0; 537 fsc->sc_portbits &= ~FLSC_PB_DMA_BITS; 538 fsc->sc_reg[0x40] = fsc->sc_portbits; 539 fsc->sc_reg[0x80] = 0; 540 *((u_long *)fsc->sc_dmabase) = 0; 541 542 /* 543 * If output and length < 16, copy to fifo 544 */ 545 if (datain == 0 && fsc->sc_dmasize < 16) { 546 int n; 547 for (n = 0; n < fsc->sc_dmasize; ++n) 548 fsc->sc_reg[NCR_FIFO * 4] = *ptr++; 549 NCR_DMA(("flsc_dma_setup: %d bytes written to fifo\n", n)); 550 fsc->sc_piomode = 1; 551 fsc->sc_active = 1; 552 *fsc->sc_pdmalen -= fsc->sc_dmasize; 553 *fsc->sc_dmaaddr += fsc->sc_dmasize; 554 *dmasize = fsc->sc_dmasize; 555 fsc->sc_dmasize = 0; 556 return 0; /* All done */ 557 } 558 /* 559 * If output and unaligned, copy unaligned data to fifo 560 */ 561 else if (datain == 0 && (int)ptr & 3) { 562 int n = 4 - ((int)ptr & 3); 563 NCR_DMA(("flsc_dma_setup: align %d bytes written to fifo\n", n)); 564 pa += n; 565 xfer -= n; 566 while (n--) 567 fsc->sc_reg[NCR_FIFO * 4] = *ptr++; 568 } 569 /* 570 * If unaligned address, read unaligned bytes into alignment buffer 571 */ 572 else if ((int)ptr & 3 || xfer & 3) { 573 pa = kvtop((caddr_t)fsc->sc_alignbuf); 574 xfer = fsc->sc_dmasize = min(xfer, sizeof (fsc->sc_unalignbuf)); 575 NCR_DMA(("flsc_dma_setup: align read by %d bytes\n", xfer)); 576 fsc->sc_xfr_align = 1; 577 } 578 /* 579 * If length smaller than longword, read into alignment buffer 580 * XXX doesn't work for 1 or 2 bytes !!!! 581 */ 582 else if (fsc->sc_dmasize < 4) { 583 NCR_DMA(("flsc_dma_setup: read remaining %d bytes\n", 584 fsc->sc_dmasize)); 585 pa = kvtop((caddr_t)fsc->sc_alignbuf); 586 fsc->sc_xfr_align = 1; 587 } 588 /* 589 * Finally, limit transfer length to multiple of 4 bytes. 590 */ 591 else { 592 fsc->sc_dmasize &= -4; 593 xfer &= -4; 594 } 595 596 while (xfer < fsc->sc_dmasize) { 597 if ((pa + xfer) != kvtop(*addr + xfer)) 598 break; 599 if ((fsc->sc_dmasize - xfer) < NBPG) 600 xfer = fsc->sc_dmasize; 601 else 602 xfer += NBPG; 603 } 604 605 fsc->sc_dmasize = xfer; 606 *dmasize = fsc->sc_dmasize; 607 fsc->sc_pa = pa; 608 #if defined(M68040) || defined(M68060) 609 if (mmutype == MMU_68040) { 610 if (fsc->sc_xfr_align) { 611 int n; 612 for (n = 0; n < sizeof (fsc->sc_unalignbuf); ++n) 613 fsc->sc_alignbuf[n] = n | 0x80; 614 dma_cachectl(fsc->sc_alignbuf, 615 sizeof(fsc->sc_unalignbuf)); 616 } 617 else 618 dma_cachectl(*fsc->sc_dmaaddr, fsc->sc_dmasize); 619 } 620 #endif 621 fsc->sc_reg[0x80] = 0; 622 *((u_long *)(fsc->sc_dmabase + (pa & 0x00fffffc))) = pa; 623 fsc->sc_portbits &= ~FLSC_PB_DMA_BITS; 624 fsc->sc_portbits |= FLSC_PB_ENABLE_DMA | 625 (fsc->sc_datain ? FLSC_PB_DMA_READ : FLSC_PB_DMA_WRITE); 626 fsc->sc_reg[0x40] = fsc->sc_portbits; 627 NCR_DMA(("flsc_dma_setup: DMA %p->%lx/%d [%d]\n", 628 ptr, pa, fsc->sc_dmasize, *len)); 629 fsc->sc_active = 1; 630 return 0; 631 } 632 633 void 634 flsc_dma_go(sc) 635 struct ncr53c9x_softc *sc; 636 { 637 struct flsc_softc *fsc = (struct flsc_softc *)sc; 638 639 NCR_DMA(("flsc_dma_go: datain %d size %d\n", fsc->sc_datain, 640 fsc->sc_dmasize)); 641 if (sc->sc_nexus->xs->xs_control & XS_CTL_POLL) { 642 fsc->sc_active = 1; 643 return; 644 } else if (fsc->sc_piomode == 0) { 645 fsc->sc_portbits &= ~FLSC_PB_DMA_BITS; 646 fsc->sc_portbits |= FLSC_PB_ENABLE_DMA | 647 (fsc->sc_datain ? FLSC_PB_DMA_READ : FLSC_PB_DMA_WRITE); 648 fsc->sc_reg[0x40] = fsc->sc_portbits; 649 } 650 } 651 652 void 653 flsc_dma_stop(sc) 654 struct ncr53c9x_softc *sc; 655 { 656 struct flsc_softc *fsc = (struct flsc_softc *)sc; 657 658 fsc->sc_portbits &= ~FLSC_PB_DMA_BITS; 659 fsc->sc_reg[0x40] = fsc->sc_portbits; 660 661 fsc->sc_reg[0x80] = 0; 662 *((u_long *)fsc->sc_dmabase) = 0; 663 fsc->sc_piomode = 0; 664 } 665 666 int 667 flsc_dma_isactive(sc) 668 struct ncr53c9x_softc *sc; 669 { 670 struct flsc_softc *fsc = (struct flsc_softc *)sc; 671 672 return fsc->sc_active; 673 } 674
Indexes created Thu Oct 02 14:10:14 GMT 2025