flsc.c revision 1.28
1 /* $NetBSD: flsc.c,v 1.28 2002/01/26 13:40:54 aymeric Exp $ */ 2 3 /* 4 * Copyright (c) 1997 Michael L. Hitch 5 * Copyright (c) 1995 Daniel Widenfalk 6 * Copyright (c) 1994 Christian E. Hopps 7 * Copyright (c) 1982, 1990 The Regents of the University of California. 8 * All rights reserved. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 3. All advertising materials mentioning features or use of this software 19 * must display the following acknowledgement: 20 * This product includes software developed by Daniel Widenfalk 21 * and Michael L. Hitch. 22 * 4. Neither the name of the University nor the names of its contributors 23 * may be used to endorse or promote products derived from this software 24 * without specific prior written permission. 25 * 26 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 27 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 28 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 29 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 30 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 31 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 32 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 33 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 34 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 35 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 36 * SUCH DAMAGE. 37 */ 38 39 /* 40 * Initial amiga Fastlane driver by Daniel Widenfalk. Conversion to 41 * 53c9x MI driver by Michael L. Hitch (mhitch (at) montana.edu). 42 */ 43 44 #include "opt_ddb.h" 45 46 #include <sys/types.h> 47 #include <sys/param.h> 48 #include <sys/systm.h> 49 #include <sys/kernel.h> 50 #include <sys/errno.h> 51 #include <sys/ioctl.h> 52 #include <sys/device.h> 53 #include <sys/buf.h> 54 #include <sys/proc.h> 55 #include <sys/user.h> 56 #include <sys/queue.h> 57 58 #include <dev/scsipi/scsi_all.h> 59 #include <dev/scsipi/scsipi_all.h> 60 #include <dev/scsipi/scsiconf.h> 61 #include <dev/scsipi/scsi_message.h> 62 63 #include <machine/cpu.h> 64 #include <machine/param.h> 65 66 #include <dev/ic/ncr53c9xreg.h> 67 #include <dev/ic/ncr53c9xvar.h> 68 69 #include <amiga/amiga/isr.h> 70 #include <amiga/dev/flscvar.h> 71 #include <amiga/dev/zbusvar.h> 72 73 void flscattach(struct device *, struct device *, void *); 74 int flscmatch(struct device *, struct cfdata *, void *); 75 76 /* Linkup to the rest of the kernel */ 77 struct cfattach flsc_ca = { 78 sizeof(struct flsc_softc), flscmatch, flscattach 79 }; 80 81 /* 82 * Functions and the switch for the MI code. 83 */ 84 u_char flsc_read_reg(struct ncr53c9x_softc *, int); 85 void flsc_write_reg(struct ncr53c9x_softc *, int, u_char); 86 int flsc_dma_isintr(struct ncr53c9x_softc *); 87 void flsc_dma_reset(struct ncr53c9x_softc *); 88 int flsc_dma_intr(struct ncr53c9x_softc *); 89 int flsc_dma_setup(struct ncr53c9x_softc *, caddr_t *, 90 size_t *, int, size_t *); 91 void flsc_dma_go(struct ncr53c9x_softc *); 92 void flsc_dma_stop(struct ncr53c9x_softc *); 93 int flsc_dma_isactive(struct ncr53c9x_softc *); 94 void flsc_clear_latched_intr(struct ncr53c9x_softc *); 95 96 struct ncr53c9x_glue flsc_glue = { 97 flsc_read_reg, 98 flsc_write_reg, 99 flsc_dma_isintr, 100 flsc_dma_reset, 101 flsc_dma_intr, 102 flsc_dma_setup, 103 flsc_dma_go, 104 flsc_dma_stop, 105 flsc_dma_isactive, 106 flsc_clear_latched_intr, 107 }; 108 109 /* Maximum DMA transfer length to reduce impact on high-speed serial input */ 110 u_long flsc_max_dma = 1024; 111 extern int ser_open_speed; 112 113 extern int ncr53c9x_debug; 114 extern u_long scsi_nosync; 115 extern int shift_nosync; 116 117 /* 118 * if we are an Advanced Systems & Software FastlaneZ3 119 */ 120 int 121 flscmatch(struct device *parent, struct cfdata *cf, void *aux) 122 { 123 struct zbus_args *zap; 124 125 if (!is_a4000() && !is_a3000()) 126 return(0); 127 128 zap = aux; 129 if (zap->manid == 0x2140 && zap->prodid == 11 130 && iszthreepa(zap->pa)) 131 return(1); 132 133 return(0); 134 } 135 136 /* 137 * Attach this instance, and then all the sub-devices 138 */ 139 void 140 flscattach(struct device *parent, struct device *self, void *aux) 141 { 142 struct flsc_softc *fsc = (void *)self; 143 struct ncr53c9x_softc *sc = &fsc->sc_ncr53c9x; 144 struct zbus_args *zap; 145 146 /* 147 * Set up the glue for MI code early; we use some of it here. 148 */ 149 sc->sc_glue = &flsc_glue; 150 151 /* 152 * Save the regs 153 */ 154 zap = aux; 155 fsc->sc_dmabase = (volatile u_char *)zap->va; 156 fsc->sc_reg = &((volatile u_char *)zap->va)[0x1000001]; 157 158 sc->sc_freq = 40; /* Clocked at 40Mhz */ 159 160 printf(": address %p", fsc->sc_reg); 161 162 sc->sc_id = 7; 163 164 /* 165 * It is necessary to try to load the 2nd config register here, 166 * to find out what rev the flsc chip is, else the flsc_reset 167 * will not set up the defaults correctly. 168 */ 169 sc->sc_cfg1 = sc->sc_id | NCRCFG1_PARENB; 170 sc->sc_cfg2 = NCRCFG2_SCSI2 | NCRCFG2_FE; 171 sc->sc_cfg3 = 0x08 /*FCLK*/ | NCRESPCFG3_FSCSI | NCRESPCFG3_CDB; 172 sc->sc_rev = NCR_VARIANT_FAS216; 173 174 /* 175 * This is the value used to start sync negotiations 176 * Note that the NCR register "SYNCTP" is programmed 177 * in "clocks per byte", and has a minimum value of 4. 178 * The SCSI period used in negotiation is one-fourth 179 * of the time (in nanoseconds) needed to transfer one byte. 180 * Since the chip's clock is given in MHz, we have the following 181 * formula: 4 * period = (1000 / freq) * 4 182 */ 183 sc->sc_minsync = 1000 / sc->sc_freq; 184 185 if (((scsi_nosync >> shift_nosync) & 0xff00) == 0xff00) 186 sc->sc_minsync = 0; 187 188 /* Really no limit, but since we want to fit into the TCR... */ 189 sc->sc_maxxfer = 64 * 1024; 190 191 fsc->sc_portbits = 0xa0 | FLSC_PB_EDI | FLSC_PB_ESI; 192 fsc->sc_hardbits = fsc->sc_reg[0x40]; 193 194 fsc->sc_alignbuf = (char *)((u_long)fsc->sc_unalignbuf & -4); 195 196 sc->sc_dev.dv_cfdata->cf_flags |= (scsi_nosync >> shift_nosync) & 0xffff; 197 shift_nosync += 16; 198 ncr53c9x_debug |= (scsi_nosync >> shift_nosync) & 0xffff; 199 shift_nosync += 16; 200 201 /* 202 * Configure interrupts. 203 */ 204 fsc->sc_isr.isr_intr = ncr53c9x_intr; 205 fsc->sc_isr.isr_arg = sc; 206 fsc->sc_isr.isr_ipl = 2; 207 add_isr(&fsc->sc_isr); 208 209 fsc->sc_reg[0x40] = fsc->sc_portbits; 210 211 /* 212 * Now try to attach all the sub-devices 213 */ 214 sc->sc_adapter.adapt_request = ncr53c9x_scsipi_request; 215 sc->sc_adapter.adapt_minphys = minphys; 216 ncr53c9x_attach(sc); 217 } 218 219 /* 220 * Glue functions. 221 */ 222 223 u_char 224 flsc_read_reg(struct ncr53c9x_softc *sc, int reg) 225 { 226 struct flsc_softc *fsc = (struct flsc_softc *)sc; 227 228 return fsc->sc_reg[reg * 4]; 229 } 230 231 void 232 flsc_write_reg(struct ncr53c9x_softc *sc, int reg, u_char val) 233 { 234 struct flsc_softc *fsc = (struct flsc_softc *)sc; 235 struct ncr53c9x_tinfo *ti; 236 u_char v = val; 237 238 if (fsc->sc_piomode && reg == NCR_CMD && 239 v == (NCRCMD_TRANS|NCRCMD_DMA)) { 240 v = NCRCMD_TRANS; 241 } 242 /* 243 * Can't do synchronous transfers in XS_CTL_POLL mode: 244 * If starting XS_CTL_POLL command, clear defer sync negotiation 245 * by clearing the T_NEGOTIATE flag. If starting XS_CTL_POLL and 246 * the device is currently running synchronous, force another 247 * T_NEGOTIATE with 0 offset. 248 */ 249 if (reg == NCR_SELID) { 250 ti = &sc->sc_tinfo[ 251 sc->sc_nexus->xs->xs_periph->periph_target]; 252 if (sc->sc_nexus->xs->xs_control & XS_CTL_POLL) { 253 if (ti->flags & T_SYNCMODE) { 254 ti->flags ^= T_SYNCMODE | T_NEGOTIATE; 255 } else if (ti->flags & T_NEGOTIATE) { 256 ti->flags ^= T_NEGOTIATE | T_SYNCHOFF; 257 /* save T_NEGOTIATE in private flags? */ 258 } 259 } else { 260 /* 261 * If we haven't attempted sync negotiation yet, 262 * do it now. 263 */ 264 if ((ti->flags & (T_SYNCMODE | T_SYNCHOFF)) == 265 T_SYNCHOFF && 266 sc->sc_minsync != 0) /* XXX */ 267 ti->flags ^= T_NEGOTIATE | T_SYNCHOFF; 268 } 269 } 270 if (reg == NCR_CMD && v == NCRCMD_SETATN && 271 sc->sc_flags & NCR_SYNCHNEGO && 272 sc->sc_nexus->xs->xs_control & XS_CTL_POLL) { 273 ti = &sc->sc_tinfo[ 274 sc->sc_nexus->xs->xs_periph->periph_target]; 275 ti->offset = 0; 276 } 277 fsc->sc_reg[reg * 4] = v; 278 } 279 280 int 281 flsc_dma_isintr(struct ncr53c9x_softc *sc) 282 { 283 struct flsc_softc *fsc = (struct flsc_softc *)sc; 284 unsigned hardbits; 285 286 hardbits = fsc->sc_reg[0x40]; 287 if (hardbits & FLSC_HB_IACT) 288 return (fsc->sc_csr = 0); 289 290 if (sc->sc_state == NCR_CONNECTED || sc->sc_state == NCR_SELECTING) 291 fsc->sc_portbits |= FLSC_PB_LED; 292 else 293 fsc->sc_portbits &= ~FLSC_PB_LED; 294 295 if ((hardbits & FLSC_HB_CREQ) && !(hardbits & FLSC_HB_MINT) && 296 fsc->sc_reg[NCR_STAT * 4] & NCRSTAT_INT) { 297 return 1; 298 } 299 /* Do I still need this? */ 300 if (fsc->sc_piomode && fsc->sc_reg[NCR_STAT * 4] & NCRSTAT_INT && 301 !(hardbits & FLSC_HB_MINT)) 302 return 1; 303 304 fsc->sc_reg[0x40] = fsc->sc_portbits & ~FLSC_PB_INT_BITS; 305 fsc->sc_reg[0x40] = fsc->sc_portbits; 306 return 0; 307 } 308 309 void 310 flsc_clear_latched_intr(struct ncr53c9x_softc *sc) 311 { 312 struct flsc_softc *fsc = (struct flsc_softc *)sc; 313 314 fsc->sc_reg[0x40] = fsc->sc_portbits & ~FLSC_PB_INT_BITS; 315 fsc->sc_reg[0x40] = fsc->sc_portbits; 316 } 317 318 void 319 flsc_dma_reset(struct ncr53c9x_softc *sc) 320 { 321 struct flsc_softc *fsc = (struct flsc_softc *)sc; 322 struct ncr53c9x_tinfo *ti; 323 324 if (sc->sc_nexus) 325 ti = &sc->sc_tinfo[sc->sc_nexus->xs->xs_periph->periph_target]; 326 else 327 ti = &sc->sc_tinfo[1]; /* XXX */ 328 if (fsc->sc_active) { 329 printf("dmaaddr %p dmasize %d stat %x flags %x off %d per %d ff %x", 330 *fsc->sc_dmaaddr, fsc->sc_dmasize, fsc->sc_reg[NCR_STAT * 4], 331 ti->flags, ti->offset, ti->period, fsc->sc_reg[NCR_FFLAG * 4]); 332 printf(" intr %x\n", fsc->sc_reg[NCR_INTR * 4]); 333 #ifdef DDB 334 Debugger(); 335 #endif 336 } 337 fsc->sc_portbits &= ~FLSC_PB_DMA_BITS; 338 fsc->sc_reg[0x40] = fsc->sc_portbits; 339 fsc->sc_reg[0x80] = 0; 340 *((u_long *)fsc->sc_dmabase) = 0; 341 fsc->sc_active = 0; 342 fsc->sc_piomode = 0; 343 } 344 345 int 346 flsc_dma_intr(struct ncr53c9x_softc *sc) 347 { 348 register struct flsc_softc *fsc = (struct flsc_softc *)sc; 349 register u_char *p; 350 volatile u_char *cmdreg, *intrreg, *statreg, *fiforeg; 351 register u_int flscphase, flscstat, flscintr; 352 register int cnt; 353 354 NCR_DMA(("flsc_dma_intr: pio %d cnt %d int %x stat %x fifo %d ", 355 fsc->sc_piomode, fsc->sc_dmasize, sc->sc_espintr, sc->sc_espstat, 356 fsc->sc_reg[NCR_FFLAG * 4] & NCRFIFO_FF)); 357 if (!(fsc->sc_reg[0x40] & FLSC_HB_CREQ)) 358 printf("flsc_dma_intr: csr %x stat %x intr %x\n", fsc->sc_csr, 359 sc->sc_espstat, sc->sc_espintr); 360 if (fsc->sc_active == 0) { 361 printf("flsc_intr--inactive DMA\n"); 362 return -1; 363 } 364 365 /* if DMA transfer, update sc_dmaaddr and sc_pdmalen, else PIO xfer */ 366 if (fsc->sc_piomode == 0) { 367 fsc->sc_portbits &= ~FLSC_PB_DMA_BITS; 368 fsc->sc_reg[0x40] = fsc->sc_portbits; 369 fsc->sc_reg[0x80] = 0; 370 *((u_long *)fsc->sc_dmabase) = 0; 371 cnt = fsc->sc_reg[NCR_TCL * 4]; 372 cnt += fsc->sc_reg[NCR_TCM * 4] << 8; 373 cnt += fsc->sc_reg[NCR_TCH * 4] << 16; 374 if (!fsc->sc_datain) { 375 cnt += fsc->sc_reg[NCR_FFLAG * 4] & NCRFIFO_FF; 376 fsc->sc_reg[NCR_CMD * 4] = NCRCMD_FLUSH; 377 } 378 cnt = fsc->sc_dmasize - cnt; /* number of bytes transferred */ 379 NCR_DMA(("DMA xferred %d\n", cnt)); 380 if (fsc->sc_xfr_align) { 381 int i; 382 for (i = 0; i < cnt; ++i) 383 (*fsc->sc_dmaaddr)[i] = fsc->sc_alignbuf[i]; 384 fsc->sc_xfr_align = 0; 385 } 386 *fsc->sc_dmaaddr += cnt; 387 *fsc->sc_pdmalen -= cnt; 388 fsc->sc_active = 0; 389 return 0; 390 } 391 392 if ((sc->sc_espintr & NCRINTR_BS) == 0) { 393 fsc->sc_active = 0; 394 fsc->sc_piomode = 0; 395 NCR_DMA(("no NCRINTR_BS\n")); 396 return 0; 397 } 398 399 cnt = fsc->sc_dmasize; 400 #if 0 401 if (cnt == 0) { 402 printf("data interrupt, but no count left."); 403 } 404 #endif 405 406 p = *fsc->sc_dmaaddr; 407 flscphase = sc->sc_phase; 408 flscstat = (u_int) sc->sc_espstat; 409 flscintr = (u_int) sc->sc_espintr; 410 cmdreg = fsc->sc_reg + NCR_CMD * 4; 411 fiforeg = fsc->sc_reg + NCR_FIFO * 4; 412 statreg = fsc->sc_reg + NCR_STAT * 4; 413 intrreg = fsc->sc_reg + NCR_INTR * 4; 414 NCR_DMA(("PIO %d datain %d phase %d stat %x intr %x\n", 415 cnt, fsc->sc_datain, flscphase, flscstat, flscintr)); 416 do { 417 if (fsc->sc_datain) { 418 *p++ = *fiforeg; 419 cnt--; 420 if (flscphase == DATA_IN_PHASE) { 421 *cmdreg = NCRCMD_TRANS; 422 } else { 423 fsc->sc_active = 0; 424 } 425 } else { 426 NCR_DMA(("flsc_dma_intr: PIO out- phase %d cnt %d active %d\n", flscphase, cnt, 427 fsc->sc_active)); 428 if ( (flscphase == DATA_OUT_PHASE) 429 || (flscphase == MESSAGE_OUT_PHASE)) { 430 int n; 431 n = 16 - (fsc->sc_reg[NCR_FFLAG * 4] & NCRFIFO_FF); 432 if (n > cnt) 433 n = cnt; 434 cnt -= n; 435 while (n-- > 0) 436 *fiforeg = *p++; 437 *cmdreg = NCRCMD_TRANS; 438 } else { 439 fsc->sc_active = 0; 440 } 441 } 442 443 if (fsc->sc_active && cnt) { 444 while (!(*statreg & 0x80)); 445 flscstat = *statreg; 446 flscintr = *intrreg; 447 flscphase = (flscintr & NCRINTR_DIS) 448 ? /* Disconnected */ BUSFREE_PHASE 449 : flscstat & PHASE_MASK; 450 } 451 } while (cnt && fsc->sc_active && (flscintr & NCRINTR_BS)); 452 #if 1 453 if (fsc->sc_dmasize < 8 && cnt) 454 printf("flsc_dma_intr: short transfer: dmasize %d cnt %d\n", 455 fsc->sc_dmasize, cnt); 456 #endif 457 NCR_DMA(("flsc_dma_intr: PIO transfer [%d], %d->%d phase %d stat %x intr %x\n", 458 *fsc->sc_pdmalen, fsc->sc_dmasize, cnt, flscphase, flscstat, flscintr)); 459 sc->sc_phase = flscphase; 460 sc->sc_espstat = (u_char) flscstat; 461 sc->sc_espintr = (u_char) flscintr; 462 *fsc->sc_dmaaddr = p; 463 *fsc->sc_pdmalen -= fsc->sc_dmasize - cnt; 464 fsc->sc_dmasize = cnt; 465 466 if (*fsc->sc_pdmalen == 0) { 467 sc->sc_espstat |= NCRSTAT_TC; 468 fsc->sc_piomode = 0; 469 } 470 return 0; 471 } 472 473 int 474 flsc_dma_setup(struct ncr53c9x_softc *sc, caddr_t *addr, size_t *len, 475 int datain, size_t *dmasize) 476 { 477 struct flsc_softc *fsc = (struct flsc_softc *)sc; 478 paddr_t pa; 479 u_char *ptr; 480 size_t xfer; 481 482 fsc->sc_dmaaddr = addr; 483 fsc->sc_pdmalen = len; 484 fsc->sc_datain = datain; 485 fsc->sc_dmasize = *dmasize; 486 if (sc->sc_nexus->xs->xs_control & XS_CTL_POLL) { 487 /* polling mode, use PIO */ 488 *dmasize = fsc->sc_dmasize; 489 NCR_DMA(("pfsc_dma_setup: PIO %p/%d [%d]\n", *addr, 490 fsc->sc_dmasize, *len)); 491 fsc->sc_piomode = 1; 492 if (datain == 0) { 493 int n; 494 n = fsc->sc_dmasize; 495 if (n > 16) 496 n = 16; 497 while (n-- > 0) { 498 fsc->sc_reg[NCR_FIFO * 4] = **fsc->sc_dmaaddr; 499 (*fsc->sc_pdmalen)--; 500 (*fsc->sc_dmaaddr)++; 501 --fsc->sc_dmasize; 502 } 503 } 504 return 0; 505 } 506 /* 507 * DMA can be nasty for high-speed serial input, so limit the 508 * size of this DMA operation if the serial port is running at 509 * a high speed (higher than 19200 for now - should be adjusted 510 * based on cpu type and speed?). 511 * XXX - add serial speed check XXX 512 */ 513 if (ser_open_speed > 19200 && flsc_max_dma != 0 && 514 fsc->sc_dmasize > flsc_max_dma) 515 fsc->sc_dmasize = flsc_max_dma; 516 ptr = *addr; /* Kernel virtual address */ 517 pa = kvtop(ptr); /* Physical address of DMA */ 518 xfer = min(fsc->sc_dmasize, NBPG - (pa & (NBPG - 1))); 519 fsc->sc_xfr_align = 0; 520 fsc->sc_piomode = 0; 521 fsc->sc_portbits &= ~FLSC_PB_DMA_BITS; 522 fsc->sc_reg[0x40] = fsc->sc_portbits; 523 fsc->sc_reg[0x80] = 0; 524 *((u_long *)fsc->sc_dmabase) = 0; 525 526 /* 527 * If output and length < 16, copy to fifo 528 */ 529 if (datain == 0 && fsc->sc_dmasize < 16) { 530 int n; 531 for (n = 0; n < fsc->sc_dmasize; ++n) 532 fsc->sc_reg[NCR_FIFO * 4] = *ptr++; 533 NCR_DMA(("flsc_dma_setup: %d bytes written to fifo\n", n)); 534 fsc->sc_piomode = 1; 535 fsc->sc_active = 1; 536 *fsc->sc_pdmalen -= fsc->sc_dmasize; 537 *fsc->sc_dmaaddr += fsc->sc_dmasize; 538 *dmasize = fsc->sc_dmasize; 539 fsc->sc_dmasize = 0; 540 return 0; /* All done */ 541 } 542 /* 543 * If output and unaligned, copy unaligned data to fifo 544 */ 545 else if (datain == 0 && (int)ptr & 3) { 546 int n = 4 - ((int)ptr & 3); 547 NCR_DMA(("flsc_dma_setup: align %d bytes written to fifo\n", n)); 548 pa += n; 549 xfer -= n; 550 while (n--) 551 fsc->sc_reg[NCR_FIFO * 4] = *ptr++; 552 } 553 /* 554 * If unaligned address, read unaligned bytes into alignment buffer 555 */ 556 else if ((int)ptr & 3 || xfer & 3) { 557 pa = kvtop((caddr_t)fsc->sc_alignbuf); 558 xfer = fsc->sc_dmasize = min(xfer, sizeof (fsc->sc_unalignbuf)); 559 NCR_DMA(("flsc_dma_setup: align read by %d bytes\n", xfer)); 560 fsc->sc_xfr_align = 1; 561 } 562 /* 563 * If length smaller than longword, read into alignment buffer 564 * XXX doesn't work for 1 or 2 bytes !!!! 565 */ 566 else if (fsc->sc_dmasize < 4) { 567 NCR_DMA(("flsc_dma_setup: read remaining %d bytes\n", 568 fsc->sc_dmasize)); 569 pa = kvtop((caddr_t)fsc->sc_alignbuf); 570 fsc->sc_xfr_align = 1; 571 } 572 /* 573 * Finally, limit transfer length to multiple of 4 bytes. 574 */ 575 else { 576 fsc->sc_dmasize &= -4; 577 xfer &= -4; 578 } 579 580 while (xfer < fsc->sc_dmasize) { 581 if ((pa + xfer) != kvtop(*addr + xfer)) 582 break; 583 if ((fsc->sc_dmasize - xfer) < NBPG) 584 xfer = fsc->sc_dmasize; 585 else 586 xfer += NBPG; 587 } 588 589 fsc->sc_dmasize = xfer; 590 *dmasize = fsc->sc_dmasize; 591 fsc->sc_pa = pa; 592 #if defined(M68040) || defined(M68060) 593 if (mmutype == MMU_68040) { 594 if (fsc->sc_xfr_align) { 595 int n; 596 for (n = 0; n < sizeof (fsc->sc_unalignbuf); ++n) 597 fsc->sc_alignbuf[n] = n | 0x80; 598 dma_cachectl(fsc->sc_alignbuf, 599 sizeof(fsc->sc_unalignbuf)); 600 } 601 else 602 dma_cachectl(*fsc->sc_dmaaddr, fsc->sc_dmasize); 603 } 604 #endif 605 fsc->sc_reg[0x80] = 0; 606 *((u_long *)(fsc->sc_dmabase + (pa & 0x00fffffc))) = pa; 607 fsc->sc_portbits &= ~FLSC_PB_DMA_BITS; 608 fsc->sc_portbits |= FLSC_PB_ENABLE_DMA | 609 (fsc->sc_datain ? FLSC_PB_DMA_READ : FLSC_PB_DMA_WRITE); 610 fsc->sc_reg[0x40] = fsc->sc_portbits; 611 NCR_DMA(("flsc_dma_setup: DMA %p->%lx/%d [%d]\n", 612 ptr, pa, fsc->sc_dmasize, *len)); 613 fsc->sc_active = 1; 614 return 0; 615 } 616 617 void 618 flsc_dma_go(struct ncr53c9x_softc *sc) 619 { 620 struct flsc_softc *fsc = (struct flsc_softc *)sc; 621 622 NCR_DMA(("flsc_dma_go: datain %d size %d\n", fsc->sc_datain, 623 fsc->sc_dmasize)); 624 if (sc->sc_nexus->xs->xs_control & XS_CTL_POLL) { 625 fsc->sc_active = 1; 626 return; 627 } else if (fsc->sc_piomode == 0) { 628 fsc->sc_portbits &= ~FLSC_PB_DMA_BITS; 629 fsc->sc_portbits |= FLSC_PB_ENABLE_DMA | 630 (fsc->sc_datain ? FLSC_PB_DMA_READ : FLSC_PB_DMA_WRITE); 631 fsc->sc_reg[0x40] = fsc->sc_portbits; 632 } 633 } 634 635 void 636 flsc_dma_stop(struct ncr53c9x_softc *sc) 637 { 638 struct flsc_softc *fsc = (struct flsc_softc *)sc; 639 640 fsc->sc_portbits &= ~FLSC_PB_DMA_BITS; 641 fsc->sc_reg[0x40] = fsc->sc_portbits; 642 643 fsc->sc_reg[0x80] = 0; 644 *((u_long *)fsc->sc_dmabase) = 0; 645 fsc->sc_piomode = 0; 646 } 647 648 int 649 flsc_dma_isactive(struct ncr53c9x_softc *sc) 650 { 651 struct flsc_softc *fsc = (struct flsc_softc *)sc; 652 653 return fsc->sc_active; 654 } 655
Indexes created Thu Oct 02 14:10:14 GMT 2025