flsc.c revision 1.4
1 /* 2 * Copyright (c) 1995 Daniel Widenfalk 3 * Copyright (c) 1994 Christian E. Hopps 4 * Copyright (c) 1982, 1990 The Regents of the University of California. 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 3. All advertising materials mentioning features or use of this software 16 * must display the following acknowledgement: 17 * This product includes software developed by the University of 18 * California, Berkeley and its contributors. 19 * 4. Neither the name of the University nor the names of its contributors 20 * may be used to endorse or promote products derived from this software 21 * without specific prior written permission. 22 * 23 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 24 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 25 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 26 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 27 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 28 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 29 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 30 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 31 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 32 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 33 * SUCH DAMAGE. 34 * 35 * @(#)dma.c 36 */ 37 38 #include <sys/param.h> 39 #include <sys/systm.h> 40 #include <sys/kernel.h> 41 #include <sys/device.h> 42 #include <scsi/scsi_all.h> 43 #include <scsi/scsiconf.h> 44 #include <vm/vm.h> 45 #include <vm/vm_kern.h> 46 #include <vm/vm_page.h> 47 #include <machine/pmap.h> 48 #include <amiga/amiga/custom.h> 49 #include <amiga/amiga/cc.h> 50 #include <amiga/amiga/device.h> 51 #include <amiga/amiga/isr.h> 52 #include <amiga/dev/sfasreg.h> 53 #include <amiga/dev/sfasvar.h> 54 #include <amiga/dev/zbusvar.h> 55 #include <amiga/dev/flscreg.h> 56 #include <amiga/dev/flscvar.h> 57 58 int flscprint __P((void *auxp, char *)); 59 void flscattach __P((struct device *, struct device *, void *)); 60 int flscmatch __P((struct device *, void *, void *)); 61 62 struct scsi_adapter flsc_scsiswitch = { 63 sfas_scsicmd, 64 sfas_minphys, 65 0, /* no lun support */ 66 0, /* no lun support */ 67 }; 68 69 struct scsi_device flsc_scsidev = { 70 NULL, /* use default error handler */ 71 NULL, /* do not have a start functio */ 72 NULL, /* have no async handler */ 73 NULL, /* Use default done routine */ 74 }; 75 76 struct cfattach flsc_ca = { 77 sizeof(struct flsc_softc), flscmatch, flscattach 78 }; 79 80 struct cfdriver flsc_cd = { 81 NULL, "flsc", DV_DULL, NULL, 0 82 }; 83 84 int flsc_intr __P((struct sfas_softc *dev)); 85 int flsc_setup_dma __P((struct sfas_softc *sc, void *ptr, int len, 86 int mode)); 87 int flsc_build_dma_chain __P((struct sfas_softc *sc, 88 struct sfas_dma_chain *chain, void *p, int l)); 89 int flsc_need_bump __P((struct sfas_softc *sc, void *ptr, int len)); 90 void flsc_led __P((struct sfas_softc *sc, int mode)); 91 92 /* 93 * if we are an Advanced Systems & Software FastlaneZ3 94 */ 95 int 96 flscmatch(pdp, match, auxp) 97 struct device *pdp; 98 void *match, *auxp; 99 { 100 struct zbus_args *zap; 101 102 if (!is_a4000() && !is_a3000()) 103 return(0); 104 105 zap = auxp; 106 if (zap->manid == 0x2140 && zap->prodid == 11) 107 return(1); 108 109 return(0); 110 } 111 112 void 113 flscattach(pdp, dp, auxp) 114 struct device *pdp; 115 struct device *dp; 116 void *auxp; 117 { 118 struct flsc_softc *sc; 119 struct zbus_args *zap; 120 flsc_regmap_p rp; 121 vu_char *fas; 122 123 zap = auxp; 124 fas = &((vu_char *)zap->va)[0x1000001]; 125 126 sc = (struct flsc_softc *)dp; 127 rp = &sc->sc_regmap; 128 129 rp->FAS216.sfas_tc_low = &fas[0x00]; 130 rp->FAS216.sfas_tc_mid = &fas[0x04]; 131 rp->FAS216.sfas_fifo = &fas[0x08]; 132 rp->FAS216.sfas_command = &fas[0x0C]; 133 rp->FAS216.sfas_dest_id = &fas[0x10]; 134 rp->FAS216.sfas_timeout = &fas[0x14]; 135 rp->FAS216.sfas_syncper = &fas[0x18]; 136 rp->FAS216.sfas_syncoff = &fas[0x1C]; 137 rp->FAS216.sfas_config1 = &fas[0x20]; 138 rp->FAS216.sfas_clkconv = &fas[0x24]; 139 rp->FAS216.sfas_test = &fas[0x28]; 140 rp->FAS216.sfas_config2 = &fas[0x2C]; 141 rp->FAS216.sfas_config3 = &fas[0x30]; 142 rp->FAS216.sfas_tc_high = &fas[0x38]; 143 rp->FAS216.sfas_fifo_bot = &fas[0x3C]; 144 rp->hardbits = &fas[0x40]; 145 rp->clear = &fas[0x80]; 146 rp->dmabase = zap->va; 147 148 sc->sc_softc.sc_fas = (sfas_regmap_p)rp; 149 sc->sc_softc.sc_spec = &sc->sc_specific; 150 151 sc->sc_softc.sc_led = flsc_led; 152 153 sc->sc_softc.sc_setup_dma = flsc_setup_dma; 154 sc->sc_softc.sc_build_dma_chain = flsc_build_dma_chain; 155 sc->sc_softc.sc_need_bump = flsc_need_bump; 156 157 sc->sc_softc.sc_clock_freq = 40; /* FastlaneZ3 runs at 40MHz */ 158 sc->sc_softc.sc_timeout = 250; /* Set default timeout to 250ms */ 159 sc->sc_softc.sc_config_flags = 0; /* No config flags yet */ 160 sc->sc_softc.sc_host_id = 7; /* Should check the jumpers */ 161 162 sc->sc_specific.portbits = 0xA0 | FLSC_PB_EDI | FLSC_PB_ESI; 163 sc->sc_specific.hardbits = *rp->hardbits; 164 165 sc->sc_softc.sc_bump_sz = NBPG; 166 sc->sc_softc.sc_bump_pa = 0x0; 167 168 sfasinitialize((struct sfas_softc *)sc); 169 170 sc->sc_softc.sc_link.adapter_softc = sc; 171 sc->sc_softc.sc_link.adapter_target = sc->sc_softc.sc_host_id; 172 sc->sc_softc.sc_link.adapter = &flsc_scsiswitch; 173 sc->sc_softc.sc_link.device = &flsc_scsidev; 174 sc->sc_softc.sc_link.openings = 1; 175 176 sc->sc_softc.sc_isr.isr_intr = flsc_intr; 177 sc->sc_softc.sc_isr.isr_arg = &sc->sc_softc; 178 sc->sc_softc.sc_isr.isr_ipl = 2; 179 add_isr(&sc->sc_softc.sc_isr); 180 181 /* We don't want interrupt until we're initialized! */ 182 *rp->hardbits = sc->sc_specific.portbits; 183 184 printf("\n"); 185 186 /* attach all scsi units on us */ 187 config_found(dp, &sc->sc_softc.sc_link, flscprint); 188 } 189 190 /* print diag if pnp is NULL else just extra */ 191 int 192 flscprint(auxp, pnp) 193 void *auxp; 194 char *pnp; 195 { 196 if (pnp == NULL) 197 return(UNCONF); 198 199 return(QUIET); 200 } 201 202 int 203 flsc_intr(dev) 204 struct sfas_softc *dev; 205 { 206 flsc_regmap_p rp; 207 struct flsc_specific *flspec; 208 int quickints; 209 u_char hb; 210 211 flspec = dev->sc_spec; 212 rp = (flsc_regmap_p)dev->sc_fas; 213 hb = *rp->hardbits; 214 215 if (hb & FLSC_HB_IACT) 216 return(0); 217 218 flspec->hardbits = hb; 219 if ((hb & FLSC_HB_CREQ) && 220 !(hb & FLSC_HB_MINT) && 221 (*rp->FAS216.sfas_status & SFAS_STAT_INTERRUPT_PENDING)) { 222 quickints = 16; 223 do { 224 dev->sc_status = *rp->FAS216.sfas_status; 225 dev->sc_interrupt = *rp->FAS216.sfas_interrupt; 226 227 if (dev->sc_interrupt & SFAS_INT_RESELECTED) { 228 dev->sc_resel[0] = *rp->FAS216.sfas_fifo; 229 dev->sc_resel[1] = *rp->FAS216.sfas_fifo; 230 } 231 sfasintr(dev); 232 233 } while((*rp->FAS216.sfas_status & SFAS_STAT_INTERRUPT_PENDING) 234 && --quickints); 235 } 236 237 /* Reset fastlane interrupt bits */ 238 *rp->hardbits = flspec->portbits & ~FLSC_PB_INT_BITS; 239 *rp->hardbits = flspec->portbits; 240 241 return(1); 242 } 243 244 /* Load transfer adress into dma register */ 245 void 246 flsc_set_dma_adr(sc, ptr) 247 struct sfas_softc *sc; 248 void *ptr; 249 { 250 flsc_regmap_p rp; 251 unsigned int *p; 252 unsigned int d; 253 254 rp = (flsc_regmap_p)sc->sc_fas; 255 256 d = (unsigned int)ptr; 257 p = (unsigned int *)((d & 0xFFFFFF) + (int)rp->dmabase); 258 259 *rp->clear=0; 260 *p = d; 261 } 262 263 /* Set DMA transfer counter */ 264 void 265 flsc_set_dma_tc(sc, len) 266 struct sfas_softc *sc; 267 unsigned int len; 268 { 269 *sc->sc_fas->sfas_tc_low = len; len >>= 8; 270 *sc->sc_fas->sfas_tc_mid = len; len >>= 8; 271 *sc->sc_fas->sfas_tc_high = len; 272 } 273 274 /* Set DMA mode */ 275 void 276 flsc_set_dma_mode(sc, mode) 277 struct sfas_softc *sc; 278 int mode; 279 { 280 struct flsc_specific *spec; 281 282 spec = sc->sc_spec; 283 284 spec->portbits = (spec->portbits & ~FLSC_PB_DMA_BITS) | mode; 285 *((flsc_regmap_p)sc->sc_fas)->hardbits = spec->portbits; 286 } 287 288 /* Initialize DMA for transfer */ 289 int 290 flsc_setup_dma(sc, ptr, len, mode) 291 struct sfas_softc *sc; 292 void *ptr; 293 int len; 294 int mode; 295 { 296 int retval; 297 298 retval = 0; 299 300 switch(mode) { 301 case SFAS_DMA_READ: 302 case SFAS_DMA_WRITE: 303 flsc_set_dma_adr(sc, ptr); 304 if (mode == SFAS_DMA_READ) 305 flsc_set_dma_mode(sc,FLSC_PB_ENABLE_DMA | FLSC_PB_DMA_READ); 306 else 307 flsc_set_dma_mode(sc,FLSC_PB_ENABLE_DMA | FLSC_PB_DMA_WRITE); 308 309 flsc_set_dma_tc(sc, len); 310 break; 311 312 case SFAS_DMA_CLEAR: 313 default: 314 flsc_set_dma_mode(sc, FLSC_PB_DISABLE_DMA); 315 flsc_set_dma_adr(sc, 0); 316 317 retval = (*sc->sc_fas->sfas_tc_high << 16) | 318 (*sc->sc_fas->sfas_tc_mid << 8) | 319 *sc->sc_fas->sfas_tc_low; 320 321 flsc_set_dma_tc(sc, 0); 322 break; 323 } 324 325 return(retval); 326 } 327 328 /* Check if address and len is ok for DMA transfer */ 329 int 330 flsc_need_bump(sc, ptr, len) 331 struct sfas_softc *sc; 332 void *ptr; 333 int len; 334 { 335 int p; 336 337 p = (int)ptr & 0x03; 338 339 if (p) { 340 p = 4-p; 341 342 if (len < 256) 343 p = len; 344 } 345 346 return(p); 347 } 348 349 /* Interrupt driven routines */ 350 int 351 flsc_build_dma_chain(sc, chain, p, l) 352 struct sfas_softc *sc; 353 struct sfas_dma_chain *chain; 354 void *p; 355 int l; 356 { 357 vm_offset_t pa, lastpa; 358 char *ptr; 359 int len, prelen, postlen, max_t, n; 360 361 if (l == 0) 362 return(0); 363 364 #define set_link(n, p, l, f)\ 365 do { chain[n].ptr = (p); chain[n].len = (l); chain[n++].flg = (f); } while(0) 366 367 n = 0; 368 369 if (l < 512) 370 set_link(n, (vm_offset_t)p, l, SFAS_CHAIN_BUMP); 371 else if ((p >= (void *)0xFF000000) 372 #if M68040 373 && ((mmutype == MMU_68040) && (p >= (void *)0xFFFC0000)) 374 #endif 375 ) { 376 while(l != 0) { 377 len = ((l > sc->sc_bump_sz) ? sc->sc_bump_sz : l); 378 379 set_link(n, (vm_offset_t)p, len, SFAS_CHAIN_BUMP); 380 381 p += len; 382 l -= len; 383 } 384 } else { 385 ptr = p; 386 len = l; 387 388 pa = kvtop(ptr); 389 prelen = ((int)ptr & 0x03); 390 391 if (prelen) { 392 prelen = 4-prelen; 393 set_link(n, (vm_offset_t)ptr, prelen, SFAS_CHAIN_BUMP); 394 ptr += prelen; 395 len -= prelen; 396 } 397 398 lastpa = 0; 399 while(len > 3) { 400 pa = kvtop(ptr); 401 max_t = NBPG - (pa & PGOFSET); 402 if (max_t > len) 403 max_t = len; 404 405 max_t &= ~3; 406 407 if (lastpa == pa) 408 sc->sc_chain[n-1].len += max_t; 409 else 410 set_link(n, pa, max_t, SFAS_CHAIN_DMA); 411 412 lastpa = pa+max_t; 413 414 ptr += max_t; 415 len -= max_t; 416 } 417 418 if (len) 419 set_link(n, (vm_offset_t)ptr, len, SFAS_CHAIN_BUMP); 420 } 421 422 return(n); 423 } 424 425 /* Turn on/off led */ 426 void 427 flsc_led(sc, mode) 428 struct sfas_softc *sc; 429 int mode; 430 { 431 struct flsc_specific *spec; 432 flsc_regmap_p rp; 433 434 spec = sc->sc_spec; 435 rp = (flsc_regmap_p)sc->sc_fas; 436 437 if (mode) { 438 sc->sc_led_status++; 439 440 spec->portbits |= FLSC_PB_LED; 441 *rp->hardbits = spec->portbits; 442 } else { 443 if (sc->sc_led_status) 444 sc->sc_led_status--; 445 446 if (!sc->sc_led_status) { 447 spec->portbits &= ~FLSC_PB_LED; 448 *rp->hardbits = spec->portbits; 449 } 450 } 451 } 452
Indexes created Thu Oct 02 14:10:14 GMT 2025