flsc.c revision 1.42.2.2
1 /* $NetBSD: flsc.c,v 1.42.2.2 2010/10/22 07:20:59 uebayasi Exp $ */ 2 3 /* 4 * Copyright (c) 1997 Michael L. Hitch 5 * Copyright (c) 1995 Daniel Widenfalk 6 * Copyright (c) 1994 Christian E. Hopps 7 * Copyright (c) 1982, 1990 The Regents of the University of California. 8 * All rights reserved. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 3. All advertising materials mentioning features or use of this software 19 * must display the following acknowledgement: 20 * This product includes software developed by Daniel Widenfalk 21 * and Michael L. Hitch. 22 * 4. Neither the name of the University nor the names of its contributors 23 * may be used to endorse or promote products derived from this software 24 * without specific prior written permission. 25 * 26 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 27 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 28 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 29 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 30 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 31 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 32 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 33 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 34 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 35 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 36 * SUCH DAMAGE. 37 */ 38 39 /* 40 * Initial amiga Fastlane driver by Daniel Widenfalk. Conversion to 41 * 53c9x MI driver by Michael L. Hitch (mhitch (at) montana.edu). 42 */ 43 44 #include "opt_ddb.h" 45 #ifdef __m68k__ 46 #include "opt_m68k_arch.h" 47 #endif 48 49 #include <sys/cdefs.h> 50 __KERNEL_RCSID(0, "$NetBSD: flsc.c,v 1.42.2.2 2010/10/22 07:20:59 uebayasi Exp $"); 51 52 #include <sys/types.h> 53 #include <sys/param.h> 54 #include <sys/systm.h> 55 #include <sys/kernel.h> 56 #include <sys/errno.h> 57 #include <sys/ioctl.h> 58 #include <sys/device.h> 59 #include <sys/buf.h> 60 #include <sys/proc.h> 61 #include <sys/queue.h> 62 63 #include <uvm/uvm_extern.h> 64 65 #include <dev/scsipi/scsi_all.h> 66 #include <dev/scsipi/scsipi_all.h> 67 #include <dev/scsipi/scsiconf.h> 68 #include <dev/scsipi/scsi_message.h> 69 70 #include <machine/cpu.h> 71 #include <machine/param.h> 72 73 #include <dev/ic/ncr53c9xreg.h> 74 #include <dev/ic/ncr53c9xvar.h> 75 76 #include <amiga/amiga/isr.h> 77 #include <amiga/dev/flscvar.h> 78 #include <amiga/dev/zbusvar.h> 79 80 int flscmatch(device_t, cfdata_t, void *); 81 void flscattach(device_t, device_t, void *); 82 83 /* Linkup to the rest of the kernel */ 84 CFATTACH_DECL_NEW(flsc, sizeof(struct flsc_softc), 85 flscmatch, flscattach, NULL, NULL); 86 87 /* 88 * Functions and the switch for the MI code. 89 */ 90 uint8_t flsc_read_reg(struct ncr53c9x_softc *, int); 91 void flsc_write_reg(struct ncr53c9x_softc *, int, uint8_t); 92 int flsc_dma_isintr(struct ncr53c9x_softc *); 93 void flsc_dma_reset(struct ncr53c9x_softc *); 94 int flsc_dma_intr(struct ncr53c9x_softc *); 95 int flsc_dma_setup(struct ncr53c9x_softc *, uint8_t **, 96 size_t *, int, size_t *); 97 void flsc_dma_go(struct ncr53c9x_softc *); 98 void flsc_dma_stop(struct ncr53c9x_softc *); 99 int flsc_dma_isactive(struct ncr53c9x_softc *); 100 void flsc_clear_latched_intr(struct ncr53c9x_softc *); 101 102 struct ncr53c9x_glue flsc_glue = { 103 flsc_read_reg, 104 flsc_write_reg, 105 flsc_dma_isintr, 106 flsc_dma_reset, 107 flsc_dma_intr, 108 flsc_dma_setup, 109 flsc_dma_go, 110 flsc_dma_stop, 111 flsc_dma_isactive, 112 flsc_clear_latched_intr, 113 }; 114 115 /* Maximum DMA transfer length to reduce impact on high-speed serial input */ 116 u_long flsc_max_dma = 1024; 117 extern int ser_open_speed; 118 119 extern int ncr53c9x_debug; 120 extern u_long scsi_nosync; 121 extern int shift_nosync; 122 123 /* 124 * if we are an Advanced Systems & Software FastlaneZ3 125 */ 126 int 127 flscmatch(device_t parent, cfdata_t cf, void *aux) 128 { 129 struct zbus_args *zap; 130 131 if (!is_a4000() && !is_a3000()) 132 return 0; 133 134 zap = aux; 135 if (zap->manid == 0x2140 && zap->prodid == 11 136 && iszthreepa(zap->pa)) 137 return 1; 138 139 return 0; 140 } 141 142 /* 143 * Attach this instance, and then all the sub-devices 144 */ 145 void 146 flscattach(device_t parent, device_t self, void *aux) 147 { 148 struct flsc_softc *fsc = device_private(self); 149 struct ncr53c9x_softc *sc = &fsc->sc_ncr53c9x; 150 struct zbus_args *zap; 151 152 /* 153 * Set up the glue for MI code early; we use some of it here. 154 */ 155 sc->sc_dev = self; 156 sc->sc_glue = &flsc_glue; 157 158 /* 159 * Save the regs 160 */ 161 zap = aux; 162 fsc->sc_dmabase = (volatile uint8_t *)zap->va; 163 fsc->sc_reg = &((volatile uint8_t *)zap->va)[0x1000001]; 164 165 sc->sc_freq = 40; /* Clocked at 40 MHz */ 166 167 aprint_normal(": address %p", fsc->sc_reg); 168 169 sc->sc_id = 7; 170 171 /* 172 * It is necessary to try to load the 2nd config register here, 173 * to find out what rev the flsc chip is, else the flsc_reset 174 * will not set up the defaults correctly. 175 */ 176 sc->sc_cfg1 = sc->sc_id | NCRCFG1_PARENB; 177 sc->sc_cfg2 = NCRCFG2_SCSI2 | NCRCFG2_FE; 178 sc->sc_cfg3 = 0x08 /*FCLK*/ | NCRESPCFG3_FSCSI | NCRESPCFG3_CDB; 179 sc->sc_rev = NCR_VARIANT_FAS216; 180 181 /* 182 * This is the value used to start sync negotiations 183 * Note that the NCR register "SYNCTP" is programmed 184 * in "clocks per byte", and has a minimum value of 4. 185 * The SCSI period used in negotiation is one-fourth 186 * of the time (in nanoseconds) needed to transfer one byte. 187 * Since the chip's clock is given in MHz, we have the following 188 * formula: 4 * period = (1000 / freq) * 4 189 */ 190 sc->sc_minsync = 1000 / sc->sc_freq; 191 192 if (((scsi_nosync >> shift_nosync) & 0xff00) == 0xff00) 193 sc->sc_minsync = 0; 194 195 /* Really no limit, but since we want to fit into the TCR... */ 196 sc->sc_maxxfer = 64 * 1024; 197 198 fsc->sc_portbits = 0xa0 | FLSC_PB_EDI | FLSC_PB_ESI; 199 fsc->sc_hardbits = fsc->sc_reg[0x40]; 200 201 fsc->sc_alignbuf = (uint8_t *)((u_long)fsc->sc_unalignbuf & -4); 202 203 device_cfdata(self)->cf_flags |= 204 (scsi_nosync >> shift_nosync) & 0xffff; 205 shift_nosync += 16; 206 ncr53c9x_debug |= (scsi_nosync >> shift_nosync) & 0xffff; 207 shift_nosync += 16; 208 209 /* 210 * Configure interrupts. 211 */ 212 fsc->sc_isr.isr_intr = ncr53c9x_intr; 213 fsc->sc_isr.isr_arg = sc; 214 fsc->sc_isr.isr_ipl = 2; 215 add_isr(&fsc->sc_isr); 216 217 fsc->sc_reg[0x40] = fsc->sc_portbits; 218 219 /* 220 * Now try to attach all the sub-devices 221 */ 222 sc->sc_adapter.adapt_request = ncr53c9x_scsipi_request; 223 sc->sc_adapter.adapt_minphys = minphys; 224 ncr53c9x_attach(sc); 225 } 226 227 /* 228 * Glue functions. 229 */ 230 231 uint8_t 232 flsc_read_reg(struct ncr53c9x_softc *sc, int reg) 233 { 234 struct flsc_softc *fsc = (struct flsc_softc *)sc; 235 236 return fsc->sc_reg[reg * 4]; 237 } 238 239 void 240 flsc_write_reg(struct ncr53c9x_softc *sc, int reg, uint8_t val) 241 { 242 struct flsc_softc *fsc = (struct flsc_softc *)sc; 243 struct ncr53c9x_tinfo *ti; 244 uint8_t v = val; 245 246 if (fsc->sc_piomode && reg == NCR_CMD && 247 v == (NCRCMD_TRANS | NCRCMD_DMA)) { 248 v = NCRCMD_TRANS; 249 } 250 /* 251 * Can't do synchronous transfers in XS_CTL_POLL mode: 252 * If starting XS_CTL_POLL command, clear defer sync negotiation 253 * by clearing the T_NEGOTIATE flag. If starting XS_CTL_POLL and 254 * the device is currently running synchronous, force another 255 * T_NEGOTIATE with 0 offset. 256 */ 257 if (reg == NCR_SELID) { 258 ti = &sc->sc_tinfo[ 259 sc->sc_nexus->xs->xs_periph->periph_target]; 260 if (sc->sc_nexus->xs->xs_control & XS_CTL_POLL) { 261 if (ti->flags & T_SYNCMODE) { 262 ti->flags ^= T_SYNCMODE | T_NEGOTIATE; 263 } else if (ti->flags & T_NEGOTIATE) { 264 ti->flags ^= T_NEGOTIATE | T_SYNCHOFF; 265 /* save T_NEGOTIATE in private flags? */ 266 } 267 } else { 268 /* 269 * If we haven't attempted sync negotiation yet, 270 * do it now. 271 */ 272 if ((ti->flags & (T_SYNCMODE | T_SYNCHOFF)) == 273 T_SYNCHOFF && 274 sc->sc_minsync != 0) /* XXX */ 275 ti->flags ^= T_NEGOTIATE | T_SYNCHOFF; 276 } 277 } 278 if (reg == NCR_CMD && v == NCRCMD_SETATN && 279 sc->sc_flags & NCR_SYNCHNEGO && 280 sc->sc_nexus->xs->xs_control & XS_CTL_POLL) { 281 ti = &sc->sc_tinfo[ 282 sc->sc_nexus->xs->xs_periph->periph_target]; 283 ti->offset = 0; 284 } 285 fsc->sc_reg[reg * 4] = v; 286 } 287 288 int 289 flsc_dma_isintr(struct ncr53c9x_softc *sc) 290 { 291 struct flsc_softc *fsc = (struct flsc_softc *)sc; 292 unsigned int hardbits; 293 294 hardbits = fsc->sc_reg[0x40]; 295 if ((hardbits & FLSC_HB_IACT) != 0) 296 return (fsc->sc_csr = 0); 297 298 if (sc->sc_state == NCR_CONNECTED || sc->sc_state == NCR_SELECTING) 299 fsc->sc_portbits |= FLSC_PB_LED; 300 else 301 fsc->sc_portbits &= ~FLSC_PB_LED; 302 303 if ((hardbits & FLSC_HB_CREQ) != 0 && (hardbits & FLSC_HB_MINT) == 0 && 304 (fsc->sc_reg[NCR_STAT * 4] & NCRSTAT_INT) != 0) { 305 return 1; 306 } 307 /* Do I still need this? */ 308 if (fsc->sc_piomode && (fsc->sc_reg[NCR_STAT * 4] & NCRSTAT_INT) != 0 && 309 (hardbits & FLSC_HB_MINT) == 0) 310 return 1; 311 312 fsc->sc_reg[0x40] = fsc->sc_portbits & ~FLSC_PB_INT_BITS; 313 fsc->sc_reg[0x40] = fsc->sc_portbits; 314 return 0; 315 } 316 317 void 318 flsc_clear_latched_intr(struct ncr53c9x_softc *sc) 319 { 320 struct flsc_softc *fsc = (struct flsc_softc *)sc; 321 322 fsc->sc_reg[0x40] = fsc->sc_portbits & ~FLSC_PB_INT_BITS; 323 fsc->sc_reg[0x40] = fsc->sc_portbits; 324 } 325 326 void 327 flsc_dma_reset(struct ncr53c9x_softc *sc) 328 { 329 struct flsc_softc *fsc = (struct flsc_softc *)sc; 330 struct ncr53c9x_tinfo *ti; 331 332 if (sc->sc_nexus) 333 ti = &sc->sc_tinfo[sc->sc_nexus->xs->xs_periph->periph_target]; 334 else 335 ti = &sc->sc_tinfo[1]; /* XXX */ 336 if (fsc->sc_active) { 337 printf("dmaaddr %p dmasize %d stat %x flags %x off %d ", 338 *fsc->sc_dmaaddr, fsc->sc_dmasize, 339 fsc->sc_reg[NCR_STAT * 4], ti->flags, ti->offset); 340 printf("per %d ff %x intr %x\n", 341 ti->period, fsc->sc_reg[NCR_FFLAG * 4], 342 fsc->sc_reg[NCR_INTR * 4]); 343 #ifdef DDB 344 Debugger(); 345 #endif 346 } 347 fsc->sc_portbits &= ~FLSC_PB_DMA_BITS; 348 fsc->sc_reg[0x40] = fsc->sc_portbits; 349 fsc->sc_reg[0x80] = 0; 350 *((volatile uint32_t *)fsc->sc_dmabase) = 0; 351 fsc->sc_active = 0; 352 fsc->sc_piomode = 0; 353 } 354 355 int 356 flsc_dma_intr(struct ncr53c9x_softc *sc) 357 { 358 register struct flsc_softc *fsc = (struct flsc_softc *)sc; 359 uint8_t *p; 360 volatile uint8_t *cmdreg, *intrreg, *statreg, *fiforeg; 361 u_int flscphase, flscstat, flscintr; 362 int cnt; 363 364 NCR_DMA(("flsc_dma_intr: pio %d cnt %d int %x stat %x fifo %d ", 365 fsc->sc_piomode, fsc->sc_dmasize, sc->sc_espintr, sc->sc_espstat, 366 fsc->sc_reg[NCR_FFLAG * 4] & NCRFIFO_FF)); 367 if ((fsc->sc_reg[0x40] & FLSC_HB_CREQ) == 0) 368 printf("flsc_dma_intr: csr %x stat %x intr %x\n", fsc->sc_csr, 369 sc->sc_espstat, sc->sc_espintr); 370 if (fsc->sc_active == 0) { 371 printf("flsc_intr--inactive DMA\n"); 372 return -1; 373 } 374 375 /* if DMA transfer, update sc_dmaaddr and sc_pdmalen, else PIO xfer */ 376 if (fsc->sc_piomode == 0) { 377 fsc->sc_portbits &= ~FLSC_PB_DMA_BITS; 378 fsc->sc_reg[0x40] = fsc->sc_portbits; 379 fsc->sc_reg[0x80] = 0; 380 *((volatile uint32_t *)fsc->sc_dmabase) = 0; 381 cnt = fsc->sc_reg[NCR_TCL * 4]; 382 cnt += fsc->sc_reg[NCR_TCM * 4] << 8; 383 cnt += fsc->sc_reg[NCR_TCH * 4] << 16; 384 if (!fsc->sc_datain) { 385 cnt += fsc->sc_reg[NCR_FFLAG * 4] & NCRFIFO_FF; 386 fsc->sc_reg[NCR_CMD * 4] = NCRCMD_FLUSH; 387 } 388 cnt = fsc->sc_dmasize - cnt; /* number of bytes transferred */ 389 NCR_DMA(("DMA xferred %d\n", cnt)); 390 if (fsc->sc_xfr_align) { 391 int i; 392 for (i = 0; i < cnt; ++i) 393 (*fsc->sc_dmaaddr)[i] = fsc->sc_alignbuf[i]; 394 fsc->sc_xfr_align = 0; 395 } 396 *fsc->sc_dmaaddr += cnt; 397 *fsc->sc_pdmalen -= cnt; 398 fsc->sc_active = 0; 399 return 0; 400 } 401 402 if ((sc->sc_espintr & NCRINTR_BS) == 0) { 403 fsc->sc_active = 0; 404 fsc->sc_piomode = 0; 405 NCR_DMA(("no NCRINTR_BS\n")); 406 return 0; 407 } 408 409 cnt = fsc->sc_dmasize; 410 #if 0 411 if (cnt == 0) { 412 printf("data interrupt, but no count left."); 413 } 414 #endif 415 416 p = *fsc->sc_dmaaddr; 417 flscphase = sc->sc_phase; 418 flscstat = (u_int)sc->sc_espstat; 419 flscintr = (u_int)sc->sc_espintr; 420 cmdreg = fsc->sc_reg + NCR_CMD * 4; 421 fiforeg = fsc->sc_reg + NCR_FIFO * 4; 422 statreg = fsc->sc_reg + NCR_STAT * 4; 423 intrreg = fsc->sc_reg + NCR_INTR * 4; 424 NCR_DMA(("PIO %d datain %d phase %d stat %x intr %x\n", 425 cnt, fsc->sc_datain, flscphase, flscstat, flscintr)); 426 do { 427 if (fsc->sc_datain) { 428 *p++ = *fiforeg; 429 cnt--; 430 if (flscphase == DATA_IN_PHASE) { 431 *cmdreg = NCRCMD_TRANS; 432 } else { 433 fsc->sc_active = 0; 434 } 435 } else { 436 NCR_DMA(("flsc_dma_intr: PIO out- phase %d cnt %d active %d\n", flscphase, cnt, 437 fsc->sc_active)); 438 if ( (flscphase == DATA_OUT_PHASE) 439 || (flscphase == MESSAGE_OUT_PHASE)) { 440 int n; 441 n = 16 - (fsc->sc_reg[NCR_FFLAG * 4] & NCRFIFO_FF); 442 if (n > cnt) 443 n = cnt; 444 cnt -= n; 445 while (n-- > 0) 446 *fiforeg = *p++; 447 *cmdreg = NCRCMD_TRANS; 448 } else { 449 fsc->sc_active = 0; 450 } 451 } 452 453 if (fsc->sc_active && cnt) { 454 while ((*statreg & 0x80) == 0) 455 ; 456 flscstat = *statreg; 457 flscintr = *intrreg; 458 flscphase = (flscintr & NCRINTR_DIS) 459 ? /* Disconnected */ BUSFREE_PHASE 460 : flscstat & PHASE_MASK; 461 } 462 } while (cnt && fsc->sc_active && (flscintr & NCRINTR_BS) != 0); 463 #if 1 464 if (fsc->sc_dmasize < 8 && cnt) 465 printf("flsc_dma_intr: short transfer: dmasize %d cnt %d\n", 466 fsc->sc_dmasize, cnt); 467 #endif 468 NCR_DMA(("flsc_dma_intr: PIO transfer [%d], %d->%d phase %d stat %x intr %x\n", 469 *fsc->sc_pdmalen, fsc->sc_dmasize, cnt, flscphase, flscstat, flscintr)); 470 sc->sc_phase = flscphase; 471 sc->sc_espstat = (uint8_t)flscstat; 472 sc->sc_espintr = (uint8_t)flscintr; 473 *fsc->sc_dmaaddr = p; 474 *fsc->sc_pdmalen -= fsc->sc_dmasize - cnt; 475 fsc->sc_dmasize = cnt; 476 477 if (*fsc->sc_pdmalen == 0) { 478 sc->sc_espstat |= NCRSTAT_TC; 479 fsc->sc_piomode = 0; 480 } 481 return 0; 482 } 483 484 int 485 flsc_dma_setup(struct ncr53c9x_softc *sc, uint8_t **addr, size_t *len, 486 int datain, size_t *dmasize) 487 { 488 struct flsc_softc *fsc = (struct flsc_softc *)sc; 489 paddr_t pa; 490 uint8_t *ptr; 491 size_t xfer; 492 493 fsc->sc_dmaaddr = addr; 494 fsc->sc_pdmalen = len; 495 fsc->sc_datain = datain; 496 fsc->sc_dmasize = *dmasize; 497 if (sc->sc_nexus->xs->xs_control & XS_CTL_POLL) { 498 /* polling mode, use PIO */ 499 *dmasize = fsc->sc_dmasize; 500 NCR_DMA(("pfsc_dma_setup: PIO %p/%d [%d]\n", *addr, 501 fsc->sc_dmasize, *len)); 502 fsc->sc_piomode = 1; 503 if (datain == 0) { 504 int n; 505 n = fsc->sc_dmasize; 506 if (n > 16) 507 n = 16; 508 while (n-- > 0) { 509 fsc->sc_reg[NCR_FIFO * 4] = **fsc->sc_dmaaddr; 510 (*fsc->sc_pdmalen)--; 511 (*fsc->sc_dmaaddr)++; 512 --fsc->sc_dmasize; 513 } 514 } 515 return 0; 516 } 517 /* 518 * DMA can be nasty for high-speed serial input, so limit the 519 * size of this DMA operation if the serial port is running at 520 * a high speed (higher than 19200 for now - should be adjusted 521 * based on CPU type and speed?). 522 * XXX - add serial speed check XXX 523 */ 524 if (ser_open_speed > 19200 && flsc_max_dma != 0 && 525 fsc->sc_dmasize > flsc_max_dma) 526 fsc->sc_dmasize = flsc_max_dma; 527 ptr = *addr; /* Kernel virtual address */ 528 pa = kvtop(ptr); /* Physical address of DMA */ 529 xfer = min(fsc->sc_dmasize, PAGE_SIZE - (pa & (PAGE_SIZE - 1))); 530 fsc->sc_xfr_align = 0; 531 fsc->sc_piomode = 0; 532 fsc->sc_portbits &= ~FLSC_PB_DMA_BITS; 533 fsc->sc_reg[0x40] = fsc->sc_portbits; 534 fsc->sc_reg[0x80] = 0; 535 *((volatile uint32_t *)fsc->sc_dmabase) = 0; 536 537 /* 538 * If output and length < 16, copy to fifo 539 */ 540 if (datain == 0 && fsc->sc_dmasize < 16) { 541 int n; 542 for (n = 0; n < fsc->sc_dmasize; ++n) 543 fsc->sc_reg[NCR_FIFO * 4] = *ptr++; 544 NCR_DMA(("flsc_dma_setup: %d bytes written to fifo\n", n)); 545 fsc->sc_piomode = 1; 546 fsc->sc_active = 1; 547 *fsc->sc_pdmalen -= fsc->sc_dmasize; 548 *fsc->sc_dmaaddr += fsc->sc_dmasize; 549 *dmasize = fsc->sc_dmasize; 550 fsc->sc_dmasize = 0; 551 return 0; /* All done */ 552 } 553 /* 554 * If output and unaligned, copy unaligned data to fifo 555 */ 556 else if (datain == 0 && (int)ptr & 3) { 557 int n = 4 - ((int)ptr & 3); 558 NCR_DMA(("flsc_dma_setup: align %d bytes written to fifo\n", n)); 559 pa += n; 560 xfer -= n; 561 while (n--) 562 fsc->sc_reg[NCR_FIFO * 4] = *ptr++; 563 } 564 /* 565 * If unaligned address, read unaligned bytes into alignment buffer 566 */ 567 else if ((int)ptr & 3 || xfer & 3) { 568 pa = kvtop((void *)fsc->sc_alignbuf); 569 xfer = fsc->sc_dmasize = min(xfer, sizeof(fsc->sc_unalignbuf)); 570 NCR_DMA(("flsc_dma_setup: align read by %d bytes\n", xfer)); 571 fsc->sc_xfr_align = 1; 572 } 573 /* 574 * If length smaller than longword, read into alignment buffer 575 * XXX doesn't work for 1 or 2 bytes !!!! 576 */ 577 else if (fsc->sc_dmasize < 4) { 578 NCR_DMA(("flsc_dma_setup: read remaining %d bytes\n", 579 fsc->sc_dmasize)); 580 pa = kvtop((void *)fsc->sc_alignbuf); 581 fsc->sc_xfr_align = 1; 582 } 583 /* 584 * Finally, limit transfer length to multiple of 4 bytes. 585 */ 586 else { 587 fsc->sc_dmasize &= -4; 588 xfer &= -4; 589 } 590 591 while (xfer < fsc->sc_dmasize) { 592 if ((pa + xfer) != kvtop(*addr + xfer)) 593 break; 594 if ((fsc->sc_dmasize - xfer) < PAGE_SIZE) 595 xfer = fsc->sc_dmasize; 596 else 597 xfer += PAGE_SIZE; 598 } 599 600 fsc->sc_dmasize = xfer; 601 *dmasize = fsc->sc_dmasize; 602 fsc->sc_pa = pa; 603 #if defined(M68040) || defined(M68060) 604 if (mmutype == MMU_68040) { 605 if (fsc->sc_xfr_align) { 606 int n; 607 for (n = 0; n < sizeof(fsc->sc_unalignbuf); ++n) 608 fsc->sc_alignbuf[n] = n | 0x80; 609 dma_cachectl(fsc->sc_alignbuf, 610 sizeof(fsc->sc_unalignbuf)); 611 } 612 else 613 dma_cachectl(*fsc->sc_dmaaddr, fsc->sc_dmasize); 614 } 615 #endif 616 fsc->sc_reg[0x80] = 0; 617 *((volatile uint32_t *)(fsc->sc_dmabase + (pa & 0x00fffffc))) = pa; 618 fsc->sc_portbits &= ~FLSC_PB_DMA_BITS; 619 fsc->sc_portbits |= FLSC_PB_ENABLE_DMA | 620 (fsc->sc_datain ? FLSC_PB_DMA_READ : FLSC_PB_DMA_WRITE); 621 fsc->sc_reg[0x40] = fsc->sc_portbits; 622 NCR_DMA(("flsc_dma_setup: DMA %p->%lx/%d [%d]\n", 623 ptr, pa, fsc->sc_dmasize, *len)); 624 fsc->sc_active = 1; 625 return 0; 626 } 627 628 void 629 flsc_dma_go(struct ncr53c9x_softc *sc) 630 { 631 struct flsc_softc *fsc = (struct flsc_softc *)sc; 632 633 NCR_DMA(("flsc_dma_go: datain %d size %d\n", fsc->sc_datain, 634 fsc->sc_dmasize)); 635 if (sc->sc_nexus->xs->xs_control & XS_CTL_POLL) { 636 fsc->sc_active = 1; 637 return; 638 } else if (fsc->sc_piomode == 0) { 639 fsc->sc_portbits &= ~FLSC_PB_DMA_BITS; 640 fsc->sc_portbits |= FLSC_PB_ENABLE_DMA | 641 (fsc->sc_datain ? FLSC_PB_DMA_READ : FLSC_PB_DMA_WRITE); 642 fsc->sc_reg[0x40] = fsc->sc_portbits; 643 } 644 } 645 646 void 647 flsc_dma_stop(struct ncr53c9x_softc *sc) 648 { 649 struct flsc_softc *fsc = (struct flsc_softc *)sc; 650 651 fsc->sc_portbits &= ~FLSC_PB_DMA_BITS; 652 fsc->sc_reg[0x40] = fsc->sc_portbits; 653 654 fsc->sc_reg[0x80] = 0; 655 *((volatile uint32_t *)fsc->sc_dmabase) = 0; 656 fsc->sc_piomode = 0; 657 } 658 659 int 660 flsc_dma_isactive(struct ncr53c9x_softc *sc) 661 { 662 struct flsc_softc *fsc = (struct flsc_softc *)sc; 663 664 return fsc->sc_active; 665 } 666
Indexes created Thu Oct 02 14:10:14 GMT 2025