flsc.c revision 1.5
1 /* $NetBSD: flsc.c,v 1.5 1996/04/21 21:11:03 veego Exp $ */ 2 3 /* 4 * Copyright (c) 1995 Daniel Widenfalk 5 * Copyright (c) 1994 Christian E. Hopps 6 * Copyright (c) 1982, 1990 The Regents of the University of California. 7 * All rights reserved. 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions 11 * are met: 12 * 1. Redistributions of source code must retain the above copyright 13 * notice, this list of conditions and the following disclaimer. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 3. All advertising materials mentioning features or use of this software 18 * must display the following acknowledgement: 19 * This product includes software developed by the University of 20 * California, Berkeley and its contributors. 21 * 4. Neither the name of the University nor the names of its contributors 22 * may be used to endorse or promote products derived from this software 23 * without specific prior written permission. 24 * 25 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 26 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 27 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 28 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 29 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 30 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 31 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 32 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 33 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 34 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 35 * SUCH DAMAGE. 36 * 37 * @(#)dma.c 38 */ 39 40 #include <sys/param.h> 41 #include <sys/systm.h> 42 #include <sys/kernel.h> 43 #include <sys/device.h> 44 #include <scsi/scsi_all.h> 45 #include <scsi/scsiconf.h> 46 #include <vm/vm.h> 47 #include <vm/vm_kern.h> 48 #include <vm/vm_page.h> 49 #include <machine/pmap.h> 50 #include <amiga/amiga/custom.h> 51 #include <amiga/amiga/cc.h> 52 #include <amiga/amiga/device.h> 53 #include <amiga/amiga/isr.h> 54 #include <amiga/dev/sfasreg.h> 55 #include <amiga/dev/sfasvar.h> 56 #include <amiga/dev/zbusvar.h> 57 #include <amiga/dev/flscreg.h> 58 #include <amiga/dev/flscvar.h> 59 60 int flscprint __P((void *auxp, char *)); 61 void flscattach __P((struct device *, struct device *, void *)); 62 int flscmatch __P((struct device *, void *, void *)); 63 64 struct scsi_adapter flsc_scsiswitch = { 65 sfas_scsicmd, 66 sfas_minphys, 67 0, /* no lun support */ 68 0, /* no lun support */ 69 }; 70 71 struct scsi_device flsc_scsidev = { 72 NULL, /* use default error handler */ 73 NULL, /* do not have a start functio */ 74 NULL, /* have no async handler */ 75 NULL, /* Use default done routine */ 76 }; 77 78 struct cfattach flsc_ca = { 79 sizeof(struct flsc_softc), flscmatch, flscattach 80 }; 81 82 struct cfdriver flsc_cd = { 83 NULL, "flsc", DV_DULL, NULL, 0 84 }; 85 86 int flsc_intr __P((void *)); 87 void flsc_set_dma_adr __P((struct sfas_softc *sc, vm_offset_t ptr)); 88 void flsc_set_dma_tc __P((struct sfas_softc *sc, unsigned int len)); 89 void flsc_set_dma_mode __P((struct sfas_softc *sc, int mode)); 90 int flsc_setup_dma __P((struct sfas_softc *sc, vm_offset_t ptr, int len, 91 int mode)); 92 int flsc_build_dma_chain __P((struct sfas_softc *sc, 93 struct sfas_dma_chain *chain, void *p, int l)); 94 int flsc_need_bump __P((struct sfas_softc *sc, vm_offset_t ptr, int len)); 95 void flsc_led __P((struct sfas_softc *sc, int mode)); 96 97 /* 98 * if we are an Advanced Systems & Software FastlaneZ3 99 */ 100 int 101 flscmatch(pdp, match, auxp) 102 struct device *pdp; 103 void *match, *auxp; 104 { 105 struct zbus_args *zap; 106 107 if (!is_a4000() && !is_a3000()) 108 return(0); 109 110 zap = auxp; 111 if (zap->manid == 0x2140 && zap->prodid == 11) 112 return(1); 113 114 return(0); 115 } 116 117 void 118 flscattach(pdp, dp, auxp) 119 struct device *pdp; 120 struct device *dp; 121 void *auxp; 122 { 123 struct flsc_softc *sc; 124 struct zbus_args *zap; 125 flsc_regmap_p rp; 126 vu_char *fas; 127 128 zap = auxp; 129 fas = &((vu_char *)zap->va)[0x1000001]; 130 131 sc = (struct flsc_softc *)dp; 132 rp = &sc->sc_regmap; 133 134 rp->FAS216.sfas_tc_low = &fas[0x00]; 135 rp->FAS216.sfas_tc_mid = &fas[0x04]; 136 rp->FAS216.sfas_fifo = &fas[0x08]; 137 rp->FAS216.sfas_command = &fas[0x0C]; 138 rp->FAS216.sfas_dest_id = &fas[0x10]; 139 rp->FAS216.sfas_timeout = &fas[0x14]; 140 rp->FAS216.sfas_syncper = &fas[0x18]; 141 rp->FAS216.sfas_syncoff = &fas[0x1C]; 142 rp->FAS216.sfas_config1 = &fas[0x20]; 143 rp->FAS216.sfas_clkconv = &fas[0x24]; 144 rp->FAS216.sfas_test = &fas[0x28]; 145 rp->FAS216.sfas_config2 = &fas[0x2C]; 146 rp->FAS216.sfas_config3 = &fas[0x30]; 147 rp->FAS216.sfas_tc_high = &fas[0x38]; 148 rp->FAS216.sfas_fifo_bot = &fas[0x3C]; 149 rp->hardbits = &fas[0x40]; 150 rp->clear = &fas[0x80]; 151 rp->dmabase = zap->va; 152 153 sc->sc_softc.sc_fas = (sfas_regmap_p)rp; 154 sc->sc_softc.sc_spec = &sc->sc_specific; 155 156 sc->sc_softc.sc_led = flsc_led; 157 158 sc->sc_softc.sc_setup_dma = flsc_setup_dma; 159 sc->sc_softc.sc_build_dma_chain = flsc_build_dma_chain; 160 sc->sc_softc.sc_need_bump = flsc_need_bump; 161 162 sc->sc_softc.sc_clock_freq = 40; /* FastlaneZ3 runs at 40MHz */ 163 sc->sc_softc.sc_timeout = 250; /* Set default timeout to 250ms */ 164 sc->sc_softc.sc_config_flags = 0; /* No config flags yet */ 165 sc->sc_softc.sc_host_id = 7; /* Should check the jumpers */ 166 167 sc->sc_specific.portbits = 0xA0 | FLSC_PB_EDI | FLSC_PB_ESI; 168 sc->sc_specific.hardbits = *rp->hardbits; 169 170 sc->sc_softc.sc_bump_sz = NBPG; 171 sc->sc_softc.sc_bump_pa = 0x0; 172 173 sfasinitialize((struct sfas_softc *)sc); 174 175 sc->sc_softc.sc_link.adapter_softc = sc; 176 sc->sc_softc.sc_link.adapter_target = sc->sc_softc.sc_host_id; 177 sc->sc_softc.sc_link.adapter = &flsc_scsiswitch; 178 sc->sc_softc.sc_link.device = &flsc_scsidev; 179 sc->sc_softc.sc_link.openings = 1; 180 181 sc->sc_softc.sc_isr.isr_intr = flsc_intr; 182 sc->sc_softc.sc_isr.isr_arg = &sc->sc_softc; 183 sc->sc_softc.sc_isr.isr_ipl = 2; 184 add_isr(&sc->sc_softc.sc_isr); 185 186 /* We don't want interrupt until we're initialized! */ 187 *rp->hardbits = sc->sc_specific.portbits; 188 189 printf("\n"); 190 191 /* attach all scsi units on us */ 192 config_found(dp, &sc->sc_softc.sc_link, flscprint); 193 } 194 195 /* print diag if pnp is NULL else just extra */ 196 int 197 flscprint(auxp, pnp) 198 void *auxp; 199 char *pnp; 200 { 201 if (pnp == NULL) 202 return(UNCONF); 203 204 return(QUIET); 205 } 206 207 int 208 flsc_intr(arg) 209 void *arg; 210 { 211 struct sfas_softc *dev = arg; 212 flsc_regmap_p rp; 213 struct flsc_specific *flspec; 214 int quickints; 215 u_char hb; 216 217 flspec = dev->sc_spec; 218 rp = (flsc_regmap_p)dev->sc_fas; 219 hb = *rp->hardbits; 220 221 if (hb & FLSC_HB_IACT) 222 return(0); 223 224 flspec->hardbits = hb; 225 if ((hb & FLSC_HB_CREQ) && 226 !(hb & FLSC_HB_MINT) && 227 (*rp->FAS216.sfas_status & SFAS_STAT_INTERRUPT_PENDING)) { 228 quickints = 16; 229 do { 230 dev->sc_status = *rp->FAS216.sfas_status; 231 dev->sc_interrupt = *rp->FAS216.sfas_interrupt; 232 233 if (dev->sc_interrupt & SFAS_INT_RESELECTED) { 234 dev->sc_resel[0] = *rp->FAS216.sfas_fifo; 235 dev->sc_resel[1] = *rp->FAS216.sfas_fifo; 236 } 237 sfasintr(dev); 238 239 } while((*rp->FAS216.sfas_status & SFAS_STAT_INTERRUPT_PENDING) 240 && --quickints); 241 } 242 243 /* Reset fastlane interrupt bits */ 244 *rp->hardbits = flspec->portbits & ~FLSC_PB_INT_BITS; 245 *rp->hardbits = flspec->portbits; 246 247 return(1); 248 } 249 250 /* Load transfer adress into dma register */ 251 void 252 flsc_set_dma_adr(sc, ptr) 253 struct sfas_softc *sc; 254 vm_offset_t ptr; 255 { 256 flsc_regmap_p rp; 257 unsigned int *p; 258 unsigned int d; 259 260 rp = (flsc_regmap_p)sc->sc_fas; 261 262 d = (unsigned int)ptr; 263 p = (unsigned int *)((d & 0xFFFFFF) + (int)rp->dmabase); 264 265 *rp->clear=0; 266 *p = d; 267 } 268 269 /* Set DMA transfer counter */ 270 void 271 flsc_set_dma_tc(sc, len) 272 struct sfas_softc *sc; 273 unsigned int len; 274 { 275 *sc->sc_fas->sfas_tc_low = len; len >>= 8; 276 *sc->sc_fas->sfas_tc_mid = len; len >>= 8; 277 *sc->sc_fas->sfas_tc_high = len; 278 } 279 280 /* Set DMA mode */ 281 void 282 flsc_set_dma_mode(sc, mode) 283 struct sfas_softc *sc; 284 int mode; 285 { 286 struct flsc_specific *spec; 287 288 spec = sc->sc_spec; 289 290 spec->portbits = (spec->portbits & ~FLSC_PB_DMA_BITS) | mode; 291 *((flsc_regmap_p)sc->sc_fas)->hardbits = spec->portbits; 292 } 293 294 /* Initialize DMA for transfer */ 295 int 296 flsc_setup_dma(sc, ptr, len, mode) 297 struct sfas_softc *sc; 298 vm_offset_t ptr; 299 int len; 300 int mode; 301 { 302 int retval; 303 304 retval = 0; 305 306 switch(mode) { 307 case SFAS_DMA_READ: 308 case SFAS_DMA_WRITE: 309 flsc_set_dma_adr(sc, ptr); 310 if (mode == SFAS_DMA_READ) 311 flsc_set_dma_mode(sc,FLSC_PB_ENABLE_DMA | FLSC_PB_DMA_READ); 312 else 313 flsc_set_dma_mode(sc,FLSC_PB_ENABLE_DMA | FLSC_PB_DMA_WRITE); 314 315 flsc_set_dma_tc(sc, len); 316 break; 317 318 case SFAS_DMA_CLEAR: 319 default: 320 flsc_set_dma_mode(sc, FLSC_PB_DISABLE_DMA); 321 flsc_set_dma_adr(sc, 0); 322 323 retval = (*sc->sc_fas->sfas_tc_high << 16) | 324 (*sc->sc_fas->sfas_tc_mid << 8) | 325 *sc->sc_fas->sfas_tc_low; 326 327 flsc_set_dma_tc(sc, 0); 328 break; 329 } 330 331 return(retval); 332 } 333 334 /* Check if address and len is ok for DMA transfer */ 335 int 336 flsc_need_bump(sc, ptr, len) 337 struct sfas_softc *sc; 338 vm_offset_t ptr; 339 int len; 340 { 341 int p; 342 343 p = (int)ptr & 0x03; 344 345 if (p) { 346 p = 4-p; 347 348 if (len < 256) 349 p = len; 350 } 351 352 return(p); 353 } 354 355 /* Interrupt driven routines */ 356 int 357 flsc_build_dma_chain(sc, chain, p, l) 358 struct sfas_softc *sc; 359 struct sfas_dma_chain *chain; 360 void *p; 361 int l; 362 { 363 vm_offset_t pa, lastpa; 364 char *ptr; 365 int len, prelen, max_t, n; 366 367 if (l == 0) 368 return(0); 369 370 #define set_link(n, p, l, f)\ 371 do { chain[n].ptr = (p); chain[n].len = (l); chain[n++].flg = (f); } while(0) 372 373 n = 0; 374 375 if (l < 512) 376 set_link(n, (vm_offset_t)p, l, SFAS_CHAIN_BUMP); 377 else if ((p >= (void *)0xFF000000) 378 #if M68040 379 && ((mmutype == MMU_68040) && (p >= (void *)0xFFFC0000)) 380 #endif 381 ) { 382 while(l != 0) { 383 len = ((l > sc->sc_bump_sz) ? sc->sc_bump_sz : l); 384 385 set_link(n, (vm_offset_t)p, len, SFAS_CHAIN_BUMP); 386 387 p += len; 388 l -= len; 389 } 390 } else { 391 ptr = p; 392 len = l; 393 394 pa = kvtop(ptr); 395 prelen = ((int)ptr & 0x03); 396 397 if (prelen) { 398 prelen = 4-prelen; 399 set_link(n, (vm_offset_t)ptr, prelen, SFAS_CHAIN_BUMP); 400 ptr += prelen; 401 len -= prelen; 402 } 403 404 lastpa = 0; 405 while(len > 3) { 406 pa = kvtop(ptr); 407 max_t = NBPG - (pa & PGOFSET); 408 if (max_t > len) 409 max_t = len; 410 411 max_t &= ~3; 412 413 if (lastpa == pa) 414 sc->sc_chain[n-1].len += max_t; 415 else 416 set_link(n, pa, max_t, SFAS_CHAIN_DMA); 417 418 lastpa = pa+max_t; 419 420 ptr += max_t; 421 len -= max_t; 422 } 423 424 if (len) 425 set_link(n, (vm_offset_t)ptr, len, SFAS_CHAIN_BUMP); 426 } 427 428 return(n); 429 } 430 431 /* Turn on/off led */ 432 void 433 flsc_led(sc, mode) 434 struct sfas_softc *sc; 435 int mode; 436 { 437 struct flsc_specific *spec; 438 flsc_regmap_p rp; 439 440 spec = sc->sc_spec; 441 rp = (flsc_regmap_p)sc->sc_fas; 442 443 if (mode) { 444 sc->sc_led_status++; 445 446 spec->portbits |= FLSC_PB_LED; 447 *rp->hardbits = spec->portbits; 448 } else { 449 if (sc->sc_led_status) 450 sc->sc_led_status--; 451 452 if (!sc->sc_led_status) { 453 spec->portbits &= ~FLSC_PB_LED; 454 *rp->hardbits = spec->portbits; 455 } 456 } 457 } 458
Indexes created Thu Oct 02 14:10:14 GMT 2025