flsc.c revision 1.6
1 /* $NetBSD: flsc.c,v 1.6 1996/06/03 17:07:20 is Exp $ */ 2 3 /* 4 * Copyright (c) 1995 Daniel Widenfalk 5 * Copyright (c) 1994 Christian E. Hopps 6 * Copyright (c) 1982, 1990 The Regents of the University of California. 7 * All rights reserved. 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions 11 * are met: 12 * 1. Redistributions of source code must retain the above copyright 13 * notice, this list of conditions and the following disclaimer. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 3. All advertising materials mentioning features or use of this software 18 * must display the following acknowledgement: 19 * This product includes software developed by the University of 20 * California, Berkeley and its contributors. 21 * 4. Neither the name of the University nor the names of its contributors 22 * may be used to endorse or promote products derived from this software 23 * without specific prior written permission. 24 * 25 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 26 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 27 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 28 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 29 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 30 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 31 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 32 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 33 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 34 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 35 * SUCH DAMAGE. 36 * 37 * @(#)dma.c 38 */ 39 40 #include <sys/param.h> 41 #include <sys/systm.h> 42 #include <sys/kernel.h> 43 #include <sys/device.h> 44 #include <scsi/scsi_all.h> 45 #include <scsi/scsiconf.h> 46 #include <vm/vm.h> 47 #include <vm/vm_kern.h> 48 #include <vm/vm_page.h> 49 #include <machine/pmap.h> 50 #include <amiga/amiga/custom.h> 51 #include <amiga/amiga/cc.h> 52 #include <amiga/amiga/device.h> 53 #include <amiga/amiga/isr.h> 54 #include <amiga/dev/sfasreg.h> 55 #include <amiga/dev/sfasvar.h> 56 #include <amiga/dev/zbusvar.h> 57 #include <amiga/dev/flscreg.h> 58 #include <amiga/dev/flscvar.h> 59 60 int flscprint __P((void *auxp, char *)); 61 void flscattach __P((struct device *, struct device *, void *)); 62 int flscmatch __P((struct device *, void *, void *)); 63 64 struct scsi_adapter flsc_scsiswitch = { 65 sfas_scsicmd, 66 sfas_minphys, 67 0, /* no lun support */ 68 0, /* no lun support */ 69 }; 70 71 struct scsi_device flsc_scsidev = { 72 NULL, /* use default error handler */ 73 NULL, /* do not have a start functio */ 74 NULL, /* have no async handler */ 75 NULL, /* Use default done routine */ 76 }; 77 78 struct cfattach flsc_ca = { 79 sizeof(struct flsc_softc), flscmatch, flscattach 80 }; 81 82 struct cfdriver flsc_cd = { 83 NULL, "flsc", DV_DULL, NULL, 0 84 }; 85 86 int flsc_intr __P((void *)); 87 void flsc_set_dma_adr __P((struct sfas_softc *sc, vm_offset_t ptr)); 88 void flsc_set_dma_tc __P((struct sfas_softc *sc, unsigned int len)); 89 void flsc_set_dma_mode __P((struct sfas_softc *sc, int mode)); 90 int flsc_setup_dma __P((struct sfas_softc *sc, vm_offset_t ptr, int len, 91 int mode)); 92 int flsc_build_dma_chain __P((struct sfas_softc *sc, 93 struct sfas_dma_chain *chain, void *p, int l)); 94 int flsc_need_bump __P((struct sfas_softc *sc, vm_offset_t ptr, int len)); 95 void flsc_led __P((struct sfas_softc *sc, int mode)); 96 97 /* 98 * if we are an Advanced Systems & Software FastlaneZ3 99 */ 100 int 101 flscmatch(pdp, match, auxp) 102 struct device *pdp; 103 void *match, *auxp; 104 { 105 struct zbus_args *zap; 106 107 if (!is_a4000() && !is_a3000()) 108 return(0); 109 110 zap = auxp; 111 if (zap->manid == 0x2140 && zap->prodid == 11 112 && iszthreepa(zap->pa)) 113 return(1); 114 115 return(0); 116 } 117 118 void 119 flscattach(pdp, dp, auxp) 120 struct device *pdp; 121 struct device *dp; 122 void *auxp; 123 { 124 struct flsc_softc *sc; 125 struct zbus_args *zap; 126 flsc_regmap_p rp; 127 vu_char *fas; 128 129 zap = auxp; 130 fas = &((vu_char *)zap->va)[0x1000001]; 131 132 sc = (struct flsc_softc *)dp; 133 rp = &sc->sc_regmap; 134 135 rp->FAS216.sfas_tc_low = &fas[0x00]; 136 rp->FAS216.sfas_tc_mid = &fas[0x04]; 137 rp->FAS216.sfas_fifo = &fas[0x08]; 138 rp->FAS216.sfas_command = &fas[0x0C]; 139 rp->FAS216.sfas_dest_id = &fas[0x10]; 140 rp->FAS216.sfas_timeout = &fas[0x14]; 141 rp->FAS216.sfas_syncper = &fas[0x18]; 142 rp->FAS216.sfas_syncoff = &fas[0x1C]; 143 rp->FAS216.sfas_config1 = &fas[0x20]; 144 rp->FAS216.sfas_clkconv = &fas[0x24]; 145 rp->FAS216.sfas_test = &fas[0x28]; 146 rp->FAS216.sfas_config2 = &fas[0x2C]; 147 rp->FAS216.sfas_config3 = &fas[0x30]; 148 rp->FAS216.sfas_tc_high = &fas[0x38]; 149 rp->FAS216.sfas_fifo_bot = &fas[0x3C]; 150 rp->hardbits = &fas[0x40]; 151 rp->clear = &fas[0x80]; 152 rp->dmabase = zap->va; 153 154 sc->sc_softc.sc_fas = (sfas_regmap_p)rp; 155 sc->sc_softc.sc_spec = &sc->sc_specific; 156 157 sc->sc_softc.sc_led = flsc_led; 158 159 sc->sc_softc.sc_setup_dma = flsc_setup_dma; 160 sc->sc_softc.sc_build_dma_chain = flsc_build_dma_chain; 161 sc->sc_softc.sc_need_bump = flsc_need_bump; 162 163 sc->sc_softc.sc_clock_freq = 40; /* FastlaneZ3 runs at 40MHz */ 164 sc->sc_softc.sc_timeout = 250; /* Set default timeout to 250ms */ 165 sc->sc_softc.sc_config_flags = 0; /* No config flags yet */ 166 sc->sc_softc.sc_host_id = 7; /* Should check the jumpers */ 167 168 sc->sc_specific.portbits = 0xA0 | FLSC_PB_EDI | FLSC_PB_ESI; 169 sc->sc_specific.hardbits = *rp->hardbits; 170 171 sc->sc_softc.sc_bump_sz = NBPG; 172 sc->sc_softc.sc_bump_pa = 0x0; 173 174 sfasinitialize((struct sfas_softc *)sc); 175 176 sc->sc_softc.sc_link.adapter_softc = sc; 177 sc->sc_softc.sc_link.adapter_target = sc->sc_softc.sc_host_id; 178 sc->sc_softc.sc_link.adapter = &flsc_scsiswitch; 179 sc->sc_softc.sc_link.device = &flsc_scsidev; 180 sc->sc_softc.sc_link.openings = 1; 181 182 sc->sc_softc.sc_isr.isr_intr = flsc_intr; 183 sc->sc_softc.sc_isr.isr_arg = &sc->sc_softc; 184 sc->sc_softc.sc_isr.isr_ipl = 2; 185 add_isr(&sc->sc_softc.sc_isr); 186 187 /* We don't want interrupt until we're initialized! */ 188 *rp->hardbits = sc->sc_specific.portbits; 189 190 printf("\n"); 191 192 /* attach all scsi units on us */ 193 config_found(dp, &sc->sc_softc.sc_link, flscprint); 194 } 195 196 /* print diag if pnp is NULL else just extra */ 197 int 198 flscprint(auxp, pnp) 199 void *auxp; 200 char *pnp; 201 { 202 if (pnp == NULL) 203 return(UNCONF); 204 205 return(QUIET); 206 } 207 208 int 209 flsc_intr(arg) 210 void *arg; 211 { 212 struct sfas_softc *dev = arg; 213 flsc_regmap_p rp; 214 struct flsc_specific *flspec; 215 int quickints; 216 u_char hb; 217 218 flspec = dev->sc_spec; 219 rp = (flsc_regmap_p)dev->sc_fas; 220 hb = *rp->hardbits; 221 222 if (hb & FLSC_HB_IACT) 223 return(0); 224 225 flspec->hardbits = hb; 226 if ((hb & FLSC_HB_CREQ) && 227 !(hb & FLSC_HB_MINT) && 228 (*rp->FAS216.sfas_status & SFAS_STAT_INTERRUPT_PENDING)) { 229 quickints = 16; 230 do { 231 dev->sc_status = *rp->FAS216.sfas_status; 232 dev->sc_interrupt = *rp->FAS216.sfas_interrupt; 233 234 if (dev->sc_interrupt & SFAS_INT_RESELECTED) { 235 dev->sc_resel[0] = *rp->FAS216.sfas_fifo; 236 dev->sc_resel[1] = *rp->FAS216.sfas_fifo; 237 } 238 sfasintr(dev); 239 240 } while((*rp->FAS216.sfas_status & SFAS_STAT_INTERRUPT_PENDING) 241 && --quickints); 242 } 243 244 /* Reset fastlane interrupt bits */ 245 *rp->hardbits = flspec->portbits & ~FLSC_PB_INT_BITS; 246 *rp->hardbits = flspec->portbits; 247 248 return(1); 249 } 250 251 /* Load transfer adress into dma register */ 252 void 253 flsc_set_dma_adr(sc, ptr) 254 struct sfas_softc *sc; 255 vm_offset_t ptr; 256 { 257 flsc_regmap_p rp; 258 unsigned int *p; 259 unsigned int d; 260 261 rp = (flsc_regmap_p)sc->sc_fas; 262 263 d = (unsigned int)ptr; 264 p = (unsigned int *)((d & 0xFFFFFF) + (int)rp->dmabase); 265 266 *rp->clear=0; 267 *p = d; 268 } 269 270 /* Set DMA transfer counter */ 271 void 272 flsc_set_dma_tc(sc, len) 273 struct sfas_softc *sc; 274 unsigned int len; 275 { 276 *sc->sc_fas->sfas_tc_low = len; len >>= 8; 277 *sc->sc_fas->sfas_tc_mid = len; len >>= 8; 278 *sc->sc_fas->sfas_tc_high = len; 279 } 280 281 /* Set DMA mode */ 282 void 283 flsc_set_dma_mode(sc, mode) 284 struct sfas_softc *sc; 285 int mode; 286 { 287 struct flsc_specific *spec; 288 289 spec = sc->sc_spec; 290 291 spec->portbits = (spec->portbits & ~FLSC_PB_DMA_BITS) | mode; 292 *((flsc_regmap_p)sc->sc_fas)->hardbits = spec->portbits; 293 } 294 295 /* Initialize DMA for transfer */ 296 int 297 flsc_setup_dma(sc, ptr, len, mode) 298 struct sfas_softc *sc; 299 vm_offset_t ptr; 300 int len; 301 int mode; 302 { 303 int retval; 304 305 retval = 0; 306 307 switch(mode) { 308 case SFAS_DMA_READ: 309 case SFAS_DMA_WRITE: 310 flsc_set_dma_adr(sc, ptr); 311 if (mode == SFAS_DMA_READ) 312 flsc_set_dma_mode(sc,FLSC_PB_ENABLE_DMA | FLSC_PB_DMA_READ); 313 else 314 flsc_set_dma_mode(sc,FLSC_PB_ENABLE_DMA | FLSC_PB_DMA_WRITE); 315 316 flsc_set_dma_tc(sc, len); 317 break; 318 319 case SFAS_DMA_CLEAR: 320 default: 321 flsc_set_dma_mode(sc, FLSC_PB_DISABLE_DMA); 322 flsc_set_dma_adr(sc, 0); 323 324 retval = (*sc->sc_fas->sfas_tc_high << 16) | 325 (*sc->sc_fas->sfas_tc_mid << 8) | 326 *sc->sc_fas->sfas_tc_low; 327 328 flsc_set_dma_tc(sc, 0); 329 break; 330 } 331 332 return(retval); 333 } 334 335 /* Check if address and len is ok for DMA transfer */ 336 int 337 flsc_need_bump(sc, ptr, len) 338 struct sfas_softc *sc; 339 vm_offset_t ptr; 340 int len; 341 { 342 int p; 343 344 p = (int)ptr & 0x03; 345 346 if (p) { 347 p = 4-p; 348 349 if (len < 256) 350 p = len; 351 } 352 353 return(p); 354 } 355 356 /* Interrupt driven routines */ 357 int 358 flsc_build_dma_chain(sc, chain, p, l) 359 struct sfas_softc *sc; 360 struct sfas_dma_chain *chain; 361 void *p; 362 int l; 363 { 364 vm_offset_t pa, lastpa; 365 char *ptr; 366 int len, prelen, max_t, n; 367 368 if (l == 0) 369 return(0); 370 371 #define set_link(n, p, l, f)\ 372 do { chain[n].ptr = (p); chain[n].len = (l); chain[n++].flg = (f); } while(0) 373 374 n = 0; 375 376 if (l < 512) 377 set_link(n, (vm_offset_t)p, l, SFAS_CHAIN_BUMP); 378 else if ((p >= (void *)0xFF000000) 379 #if M68040 380 && ((mmutype == MMU_68040) && (p >= (void *)0xFFFC0000)) 381 #endif 382 ) { 383 while(l != 0) { 384 len = ((l > sc->sc_bump_sz) ? sc->sc_bump_sz : l); 385 386 set_link(n, (vm_offset_t)p, len, SFAS_CHAIN_BUMP); 387 388 p += len; 389 l -= len; 390 } 391 } else { 392 ptr = p; 393 len = l; 394 395 pa = kvtop(ptr); 396 prelen = ((int)ptr & 0x03); 397 398 if (prelen) { 399 prelen = 4-prelen; 400 set_link(n, (vm_offset_t)ptr, prelen, SFAS_CHAIN_BUMP); 401 ptr += prelen; 402 len -= prelen; 403 } 404 405 lastpa = 0; 406 while(len > 3) { 407 pa = kvtop(ptr); 408 max_t = NBPG - (pa & PGOFSET); 409 if (max_t > len) 410 max_t = len; 411 412 max_t &= ~3; 413 414 if (lastpa == pa) 415 sc->sc_chain[n-1].len += max_t; 416 else 417 set_link(n, pa, max_t, SFAS_CHAIN_DMA); 418 419 lastpa = pa+max_t; 420 421 ptr += max_t; 422 len -= max_t; 423 } 424 425 if (len) 426 set_link(n, (vm_offset_t)ptr, len, SFAS_CHAIN_BUMP); 427 } 428 429 return(n); 430 } 431 432 /* Turn on/off led */ 433 void 434 flsc_led(sc, mode) 435 struct sfas_softc *sc; 436 int mode; 437 { 438 struct flsc_specific *spec; 439 flsc_regmap_p rp; 440 441 spec = sc->sc_spec; 442 rp = (flsc_regmap_p)sc->sc_fas; 443 444 if (mode) { 445 sc->sc_led_status++; 446 447 spec->portbits |= FLSC_PB_LED; 448 *rp->hardbits = spec->portbits; 449 } else { 450 if (sc->sc_led_status) 451 sc->sc_led_status--; 452 453 if (!sc->sc_led_status) { 454 spec->portbits &= ~FLSC_PB_LED; 455 *rp->hardbits = spec->portbits; 456 } 457 } 458 } 459
Indexes created Thu Oct 02 14:10:14 GMT 2025