grf_cv3dreg.h revision 1.1
1 /* $NetBSD: grf_cv3dreg.h,v 1.1 1997/10/19 18:55:23 veego Exp $ */ 2 3 /* 4 * Copyright (c) 1995 Michael Teske 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 3. All advertising materials mentioning features or use of this software 16 * must display the following acknowledgement: 17 * This product includes software developed by Ezra Story and by Kari 18 * Mettinen. 19 * 4. The name of the author may not be used to endorse or promote products 20 * derived from this software without specific prior written permission 21 * 22 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 23 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 24 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 25 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 26 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 27 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 28 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 29 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 30 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 31 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 32 */ 33 34 #ifndef _GRF_CV3DREG_H 35 #define _GRF_CV3DREG_H 36 37 /* 38 * This is derived from ciruss driver source 39 */ 40 41 /* Extension to grfvideo_mode to support text modes. 42 * This can be passed to both text & gfx functions 43 * without worry. If gv.depth == 4, then the extended 44 * fields for a text mode are present. 45 */ 46 47 struct grfcv3dtext_mode { 48 struct grfvideo_mode gv; 49 unsigned short fx; /* font x dimension */ 50 unsigned short fy; /* font y dimension */ 51 unsigned short cols; /* screen dimensions */ 52 unsigned short rows; 53 void *fdata; /* font data */ 54 unsigned short fdstart; 55 unsigned short fdend; 56 }; 57 58 /* maximum console size */ 59 #define MAXROWS 200 60 #define MAXCOLS 200 61 62 /* read VGA register */ 63 #define vgar(ba, reg) (*((volatile caddr_t)(((caddr_t)ba)+(reg ^ 3)))) 64 65 /* write VGA register */ 66 #define vgaw(ba, reg, val) \ 67 *((volatile caddr_t)(((caddr_t)ba)+(reg ^ 3))) = ((val) & 0xff) 68 69 /* MMIO access */ 70 #define BYTEACCIO(x) ( ((x) & 0x3ffc) | (((x) & 3)^3) | (((x) & 3) <<14) ) 71 72 #define vgario(ba, reg) \ 73 (*((volatile caddr_t)(((caddr_t)ba) + ( BYTEACCIO(reg) )))) 74 75 #define vgawio(ba, reg, val) \ 76 do { \ 77 if (cv3d_zorroIII != 1) { \ 78 *((volatile caddr_t)(((caddr_t)cv3d_vcode_switch_base) + \ 79 0x04)) = (0x01 & 0xffff); \ 80 asm volatile ("nop"); \ 81 } \ 82 *((volatile caddr_t)(((caddr_t)cv3d_special_register_base) + \ 83 ( BYTEACCIO(reg) & 0xffff ))) = ((val) & 0xff); \ 84 if (cv3d_zorroIII != 1) { \ 85 *((volatile caddr_t)(((caddr_t)cv3d_vcode_switch_base) + \ 86 0x04)) = (0x02 & 0xffff); \ 87 asm volatile ("nop"); \ 88 } \ 89 } while (0) 90 91 /* read 32 Bit VGA register */ 92 #define vgar32(ba, reg) ( *((unsigned long *) (((volatile caddr_t)ba)+reg)) ) 93 94 /* write 32 Bit VGA register */ 95 #define vgaw32(ba, reg, val) \ 96 *((unsigned long *) (((volatile caddr_t)ba)+reg)) = val 97 98 /* read 16 Bit VGA register */ 99 #define vgar16(ba, reg) ( *((unsigned short *) (((volatile caddr_t)ba)+reg)) ) 100 101 /* write 16 Bit VGA register */ 102 #define vgaw16(ba, reg, val) \ 103 *((unsigned short *) (((volatile caddr_t)ba)+reg)) = val 104 105 int grfcv3d_cnprobe __P((void)); 106 void grfcv3d_iteinit __P((struct grf_softc *)); 107 static __inline void GfxBusyWait __P((volatile caddr_t)); 108 static __inline void GfxFifoWait __P((volatile caddr_t)); 109 static __inline unsigned char RAttr __P((volatile caddr_t, short)); 110 static __inline unsigned char RSeq __P((volatile caddr_t, short)); 111 static __inline unsigned char RCrt __P((volatile caddr_t, short)); 112 static __inline unsigned char RGfx __P((volatile caddr_t, short)); 113 114 115 /* 116 * defines for the used register addresses (mw) 117 * 118 * NOTE: there are some registers that have different addresses when 119 * in mono or color mode. We only support color mode, and thus 120 * some addresses won't work in mono-mode! 121 * 122 * General and VGA-registers taken from retina driver. Fixed a few 123 * bugs in it. (SR and GR read address is Port + 1, NOT Port) 124 * 125 */ 126 127 /* General Registers: */ 128 #define GREG_MISC_OUTPUT_R 0x03CC 129 #define GREG_MISC_OUTPUT_W 0x03C2 130 #define GREG_FEATURE_CONTROL_R 0x03CA 131 #define GREG_FEATURE_CONTROL_W 0x03DA 132 #define GREG_INPUT_STATUS0_R 0x03C2 133 #define GREG_INPUT_STATUS1_R 0x03DA 134 135 /* Setup Registers: */ 136 #define SREG_OPTION_SELECT 0x0102 137 #define SREG_VIDEO_SUBS_ENABLE 0x03C3 /* Trio64: 0x46E8 */ 138 139 /* Attribute Controller: */ 140 #define ACT_ADDRESS 0x03C0 141 #define ACT_ADDRESS_R 0x03C1 142 #define ACT_ADDRESS_W 0x03C0 143 #define ACT_ADDRESS_RESET 0x03DA 144 #define ACT_ID_PALETTE0 0x00 145 #define ACT_ID_PALETTE1 0x01 146 #define ACT_ID_PALETTE2 0x02 147 #define ACT_ID_PALETTE3 0x03 148 #define ACT_ID_PALETTE4 0x04 149 #define ACT_ID_PALETTE5 0x05 150 #define ACT_ID_PALETTE6 0x06 151 #define ACT_ID_PALETTE7 0x07 152 #define ACT_ID_PALETTE8 0x08 153 #define ACT_ID_PALETTE9 0x09 154 #define ACT_ID_PALETTE10 0x0A 155 #define ACT_ID_PALETTE11 0x0B 156 #define ACT_ID_PALETTE12 0x0C 157 #define ACT_ID_PALETTE13 0x0D 158 #define ACT_ID_PALETTE14 0x0E 159 #define ACT_ID_PALETTE15 0x0F 160 #define ACT_ID_ATTR_MODE_CNTL 0x10 161 #define ACT_ID_OVERSCAN_COLOR 0x11 162 #define ACT_ID_COLOR_PLANE_ENA 0x12 163 #define ACT_ID_HOR_PEL_PANNING 0x13 164 #define ACT_ID_COLOR_SELECT 0x14 165 166 /* Graphics Controller: */ 167 #define GCT_ADDRESS 0x03CE 168 #define GCT_ADDRESS_R 0x03CF 169 #define GCT_ADDRESS_W 0x03CF 170 #define GCT_ID_SET_RESET 0x00 171 #define GCT_ID_ENABLE_SET_RESET 0x01 172 #define GCT_ID_COLOR_COMPARE 0x02 173 #define GCT_ID_DATA_ROTATE 0x03 174 #define GCT_ID_READ_MAP_SELECT 0x04 175 #define GCT_ID_GRAPHICS_MODE 0x05 176 #define GCT_ID_MISC 0x06 177 #define GCT_ID_COLOR_XCARE 0x07 178 #define GCT_ID_BITMASK 0x08 179 180 /* Sequencer: */ 181 #define SEQ_ADDRESS 0x03C4 182 #define SEQ_ADDRESS_R 0x03C5 183 #define SEQ_ADDRESS_W 0x03C5 184 #define SEQ_ID_RESET 0x00 185 #define SEQ_ID_CLOCKING_MODE 0x01 186 #define SEQ_ID_MAP_MASK 0x02 187 #define SEQ_ID_CHAR_MAP_SELECT 0x03 188 #define SEQ_ID_MEMORY_MODE 0x04 189 #define SEQ_ID_UNKNOWN1 0x05 190 #define SEQ_ID_UNKNOWN2 0x06 191 #define SEQ_ID_UNKNOWN3 0x07 192 /* S3 extensions */ 193 #define SEQ_ID_UNLOCK_EXT 0x08 194 #define SEQ_ID_MMIO_SELECT 0x09 /* Trio64: SEQ_ID_EXT_SEQ_REG9 */ 195 #define SEQ_ID_BUS_REQ_CNTL 0x0A 196 #define SEQ_ID_EXT_MISC_SEQ 0x0B 197 #define SEQ_ID_UNKNOWN4 0x0C 198 #define SEQ_ID_EXT_SEQ 0x0D 199 #define SEQ_ID_UNKNOWN5 0x0E 200 #define SEQ_ID_UNKNOWN6 0x0F 201 #define SEQ_ID_MCLK_LO 0x10 202 #define SEQ_ID_MCLK_HI 0x11 203 #define SEQ_ID_DCLK_LO 0x12 204 #define SEQ_ID_DCLK_HI 0x13 205 #define SEQ_ID_CLKSYN_CNTL_1 0x14 206 #define SEQ_ID_CLKSYN_CNTL_2 0x15 207 #define SEQ_ID_CLKSYN_TEST_HI 0x16 /* reserved for S3 testing of the */ 208 #define SEQ_ID_CLKSYN_TEST_LO 0x17 /* internal clock synthesizer */ 209 #define SEQ_ID_RAMDAC_CNTL 0x18 210 #define SEQ_ID_MORE_MAGIC 0x1A /* not available on the Virge */ 211 #define SEQ_ID_SIGNAL_SELECT 0x1C 212 213 /* CRT Controller: */ 214 #define CRT_ADDRESS 0x03D4 215 #define CRT_ADDRESS_R 0x03D5 216 #define CRT_ADDRESS_W 0x03D5 217 #define CRT_ID_HOR_TOTAL 0x00 218 #define CRT_ID_HOR_DISP_ENA_END 0x01 219 #define CRT_ID_START_HOR_BLANK 0x02 220 #define CRT_ID_END_HOR_BLANK 0x03 221 #define CRT_ID_START_HOR_RETR 0x04 222 #define CRT_ID_END_HOR_RETR 0x05 223 #define CRT_ID_VER_TOTAL 0x06 224 #define CRT_ID_OVERFLOW 0x07 225 #define CRT_ID_PRESET_ROW_SCAN 0x08 226 #define CRT_ID_MAX_SCAN_LINE 0x09 227 #define CRT_ID_CURSOR_START 0x0A 228 #define CRT_ID_CURSOR_END 0x0B 229 #define CRT_ID_START_ADDR_HIGH 0x0C 230 #define CRT_ID_START_ADDR_LOW 0x0D 231 #define CRT_ID_CURSOR_LOC_HIGH 0x0E 232 #define CRT_ID_CURSOR_LOC_LOW 0x0F 233 #define CRT_ID_START_VER_RETR 0x10 234 #define CRT_ID_END_VER_RETR 0x11 235 #define CRT_ID_VER_DISP_ENA_END 0x12 236 #define CRT_ID_SCREEN_OFFSET 0x13 237 #define CRT_ID_UNDERLINE_LOC 0x14 238 #define CRT_ID_START_VER_BLANK 0x15 239 #define CRT_ID_END_VER_BLANK 0x16 240 #define CRT_ID_MODE_CONTROL 0x17 241 #define CRT_ID_LINE_COMPARE 0x18 242 #define CRT_ID_GD_LATCH_RBACK 0x22 243 #define CRT_ID_ACT_TOGGLE_RBACK 0x24 244 #define CRT_ID_ACT_INDEX_RBACK 0x26 245 /* S3 extensions: S3 VGA Registers */ 246 #define CRT_ID_DEVICE_HIGH 0x2D 247 #define CRT_ID_DEVICE_LOW 0x2E 248 #define CRT_ID_REVISION 0x2F 249 #define CRT_ID_CHIP_ID_REV 0x30 250 #define CRT_ID_MEMORY_CONF 0x31 251 #define CRT_ID_BACKWAD_COMP_1 0x32 252 #define CRT_ID_BACKWAD_COMP_2 0x33 253 #define CRT_ID_BACKWAD_COMP_3 0x34 254 #define CRT_ID_REGISTER_LOCK 0x35 255 #define CRT_ID_CONFIG_1 0x36 256 #define CRT_ID_CONFIG_2 0x37 257 #define CRT_ID_REGISTER_LOCK_1 0x38 258 #define CRT_ID_REGISTER_LOCK_2 0x39 259 #define CRT_ID_MISC_1 0x3A 260 #define CRT_ID_DISPLAY_FIFO 0x3B 261 #define CRT_ID_LACE_RETR_START 0x3C 262 /* S3 extensions: System Control Registers */ 263 #define CRT_ID_SYSTEM_CONFIG 0x40 264 #define CRT_ID_BIOS_FLAG 0x41 265 #define CRT_ID_LACE_CONTROL 0x42 266 #define CRT_ID_EXT_MODE 0x43 267 #define CRT_ID_HWGC_MODE 0x45 /* HWGC = Hardware Graphics Cursor */ 268 #define CRT_ID_HWGC_ORIGIN_X_HI 0x46 269 #define CRT_ID_HWGC_ORIGIN_X_LO 0x47 270 #define CRT_ID_HWGC_ORIGIN_Y_HI 0x48 271 #define CRT_ID_HWGC_ORIGIN_Y_LO 0x49 272 #define CRT_ID_HWGC_FG_STACK 0x4A 273 #define CRT_ID_HWGC_BG_STACK 0x4B 274 #define CRT_ID_HWGC_START_AD_HI 0x4C 275 #define CRT_ID_HWGC_START_AD_LO 0x4D 276 #define CRT_ID_HWGC_DSTART_X 0x4E 277 #define CRT_ID_HWGC_DSTART_Y 0x4F 278 /* S3 extensions: System Extension Registers */ 279 #define CRT_ID_EXT_SYS_CNTL_1 0x50 280 #define CRT_ID_EXT_SYS_CNTL_2 0x51 281 #define CRT_ID_EXT_BIOS_FLAG_1 0x52 282 #define CRT_ID_EXT_MEM_CNTL_1 0x53 283 #define CRT_ID_EXT_MEM_CNTL_2 0x54 284 #define CRT_ID_EXT_DAC_CNTL 0x55 285 #define CRT_ID_EX_SYNC_1 0x56 286 #define CRT_ID_EX_SYNC_2 0x57 287 #define CRT_ID_LAW_CNTL 0x58 /* LAW = Linear Address Window */ 288 #define CRT_ID_LAW_POS_HI 0x59 289 #define CRT_ID_LAW_POS_LO 0x5A 290 #define CRT_ID_GOUT_PORT 0x5C 291 #define CRT_ID_EXT_HOR_OVF 0x5D 292 #define CRT_ID_EXT_VER_OVF 0x5E 293 #define CRT_ID_EXT_MEM_CNTL_3 0x60 294 #define CRT_ID_EXT_MEM_CNTL_4 0x61 /* only available on the Virge */ 295 #define CRT_ID_EX_SYNC_3 0x63 /* not available on the Virge */ 296 #define CRT_ID_EXT_MISC_CNTL 0x65 297 #define CRT_ID_EXT_MISC_CNTL_1 0x66 298 #define CRT_ID_EXT_MISC_CNTL_2 0x67 299 #define CRT_ID_CONFIG_3 0x68 300 #define CRT_ID_EXT_SYS_CNTL_3 0x69 301 #define CRT_ID_EXT_SYS_CNTL_4 0x6A 302 #define CRT_ID_EXT_BIOS_FLAG_3 0x6B 303 #define CRT_ID_EXT_BIOS_FLAG_4 0x6C 304 #define CRT_ID_EXT_BIOS_FLAG_5 0x6D /* only available on the Virge */ 305 #define CRT_ID_RAMDAC_SIG_TEST 0x6E /* only available on the Virge */ 306 #define CRT_ID_CONFIG_4 0x6F /* only available on the Virge */ 307 308 /* Streams Processor */ 309 #define SP_PRIMARY_CONTROL 0x8180 310 #define SP_COLOR_CHROMA_KEY_CONTROL 0x8184 311 #define SP_SECONDARY_CONTROL 0x8190 312 #define SP_CHROMA_KEY_UPPER_BOUND 0x8194 313 #define SP_SECONDARY_CONSTANTS 0x8198 314 #define SP_BLEND_CONTROL 0x81A0 315 #define SP_PRIMARY_ADDRESS_0 0x81C0 316 #define SP_PRIMARY_ADDRESS_1 0x81C4 317 #define SP_PRIMARY_STRIDE 0x81C8 318 #define SP_DOUBLE_BUFFER_LPB_SUPPORT 0x81CC 319 #define SP_SECONDARY_ADDRESS_0 0x81D0 320 #define SP_SECONDARY_ADDRESS_1 0x81D4 321 #define SP_SECONDARY_STRIDE 0x81D8 322 #define SP_OPAQUE_OVERLAY_CONTROL 0x81DC 323 #define SP_K1_VERTICAL_SCALE_FACTOR 0x81E0 324 #define SP_K2_VERTICAL_SCALE_FACTOR 0x81E4 325 #define SP_DDA_VERTICAL_ACCUMULATOR 0x81E8 326 #define SP_FIFO_CONTROL 0x81EC 327 #define SP_PRIMARY_WINDOW_TOP_LEFT 0x81F0 328 #define SP_PRIMARY_WINDOW_SIZE 0x81F4 329 #define SP_SECONDARY_WINDOW_TOP_LEFT 0x81F8 330 #define SP_SECONDARY_WINDOW_SIZE 0x81FC 331 332 /* Memory Port Controller */ 333 #define MPC_FIFO_CONTROL 0x8200 334 #define MPC_MIU_CONTROL 0x8204 335 #define MPC_STREAMS_TIMEOUT 0x8208 336 #define MPC_MISC_TIMEOUT 0x820C 337 #define MPC_DMA_READ_BASE_ADDRESS 0x8220 338 #define MPC_DMA_READ_STRIDE_WIDTH 0x8224 339 340 /* Miscellaneous Registers */ 341 #define MR_SUBSYSTEM_STATUS_CNTL 0x8504 342 #define MR_ADVANCED_FUNCTION_CONTROL 0x850C 343 344 /* S3d Engine */ 345 #define S3D_BIT_BLT_RECT_FILL 0xA400 346 #define S3D_LINE_2D 0xA800 347 #define S3D_POLYGON_2D 0xAC00 348 #define S3D_LINE_3D 0xB000 349 #define S3D_TRIANGLE_3D 0xB400 350 351 #define BLT_ADDRESS 0xA4D4 352 #define BLT_SOURCE_ADDRESS 0xA4D4 353 #define BLT_DEST_ADDRESS 0xA4D8 354 #define BLT_CLIP_LEFT_RIGHT 0xA4DC 355 #define BLT_CLIP_LEFT BLT_CLIP_LEFT_RIGHT 356 #define BLT_CLIP_RIGHT 0xA4DE 357 #define BLT_CLIP_TOP_BOTTOM 0xA4E0 358 #define BLT_CLIP_BOTTOM BLT_CLIP_TOP_BOTTOM 359 #define BLT_CLIP_TOP 0xA4E2 360 #define BLT_DEST_SOURCE_PITCH 0xA4E4 361 #define BLT_SOURCE_PITCH BLT_DEST_SOURCE_PITCH 362 #define BLT_DEST_PITCH 0xA4E6 363 #define BLT_MONO_PATTERN 0xA4E8 364 #define BLT_MONO_PATTERN_0 BLT_MONO_PATTERN 365 #define BLT_MONO_PATTERN_1 0xA4EC 366 #define BLT_PATTERN_BG_COLOR 0xA4F0 367 #define BLT_PATTERN_BG_COLOR_TRUE_COLOR BLT_PATTERN_BG_COLOR 368 #define BLT_PATTERN_BG_COLOR_ALPHA BLT_PATTERN_BG_COLOR 369 #define BLT_PATTERN_BG_COLOR_RED 0xA4F1 370 #define BLT_PATTERN_BG_COLOR_HI_COLOR 0xA4F2 371 #define BLT_PATTERN_BG_COLOR_GREEN BLT_PATTERN_BG_COLOR_HI_COLOR 372 #define BLT_PATTERN_BG_COLOR_INDEX 0xA4F3 373 #define BLT_PATTERN_BG_COLOR_BLUE BLT_PATTERN_BG_COLOR_INDEX 374 #define BLT_PATTERN_FG_COLOR 0xA4F4 375 #define BLT_PATTERN_FG_COLOR_TRUE_COLOR BLT_PATTERN_FG_COLOR 376 #define BLT_PATTERN_FG_COLOR_ALPHA BLT_PATTERN_FG_COLOR 377 #define BLT_PATTERN_FG_COLOR_RED 0xA4F5 378 #define BLT_PATTERN_FG_COLOR_HI_COLOR 0xA4F6 379 #define BLT_PATTERN_FG_COLOR_GREEN BLT_PATTERN_FG_COLOR_HI_COLOR 380 #define BLT_PATTERN_FG_COLOR_INDEX 0xA4F7 381 #define BLT_PATTERN_FG_COLOR_BLUE BLT_PATTERN_FG_COLOR_INDEX 382 #define BLT_SOURCE_BG_COLOR 0xA4F8 383 #define BLT_SOURCE_BG_COLOR_TRUE_COLOR BLT_SOURCE_BG_COLOR 384 #define BLT_SOURCE_BG_COLOR_ALPHA BLT_SOURCE_BG_COLOR 385 #define BLT_SOURCE_BG_COLOR_RED 0xA4F9 386 #define BLT_SOURCE_BG_COLOR_HI_COLOR 0xA4FA 387 #define BLT_SOURCE_BG_COLOR_GREEN BLT_SOURCE_BG_COLOR_HI_COLOR 388 #define BLT_SOURCE_BG_COLOR_INDEX 0xA4FB 389 #define BLT_SOURCE_BG_COLOR_BLUE BLT_SOURCE_BG_COLOR_INDEX 390 #define BLT_SOURCE_FG_COLOR 0xA4FC 391 #define BLT_SOURCE_FG_COLOR_TRUE_COLOR BLT_SOURCE_FG_COLOR 392 #define BLT_SOURCE_FG_COLOR_ALPHA BLT_SOURCE_FG_COLOR 393 #define BLT_SOURCE_FG_COLOR_RED 0xA4FD 394 #define BLT_SOURCE_FG_COLOR_HI_COLOR 0xA4FE 395 #define BLT_SOURCE_FG_COLOR_GREEN BLT_SOURCE_FG_COLOR_HI_COLOR 396 #define BLT_SOURCE_FG_COLOR_INDEX 0xA4FF 397 #define BLT_SOURCE_FG_COLOR_BLUE BLT_SOURCE_FG_COLOR_INDEX 398 #define BLT_COMMAND_SET 0xA500 399 #define BLT_WIDTH_HEIGHT 0xA504 400 #define BLT_HEIGHT BLT_WIDTH_HEIGHT 401 #define BLT_WIDTH 0xA506 402 #define BLT_SOURCE_XY 0xA508 403 #define BLT_SOURCE_Y BLT_SOURCE_XY 404 #define BLT_SOURCE_X 0xA50A 405 #define BLT_DESTINATION_XY 0xA50C 406 #define BLT_DESTINATION_Y BLT_DESTINATION_XY 407 #define BLT_DESTINATION_X 0xA50E 408 409 #define L2D_ADDRESS 0xA8D4 410 #define L2D_SOURCE_ADDRESS 0xA8D4 411 #define L2D_DEST_ADDRESS 0xA8D8 412 #define L2D_CLIP_LEFT_RIGHT 0xA8DC 413 #define L2D_CLIP_LEFT L2D_CLIP_LEFT_RIGHT 414 #define L2D_CLIP_RIGHT 0xA8DE 415 #define L2D_CLIP_TOP_BOTTOM 0xA8E0 416 #define L2D_CLIP_BOTTOM L2D_CLIP_TOP_BOTTOM 417 #define L2D_CLIP_TOP 0xA8E2 418 #define L2D_DEST_SOURCE_PITCH 0xA8E4 419 #define L2D_SOURCE_PITCH L2D_DEST_SOURCE_PITCH 420 #define L2D_DEST_PITCH 0xA8E6 421 #define L2D_PAD_0 0xA8E8 422 #define L2D_PATTERN_FG_COLOR_TRUE_COLOR 0xA8F4 423 #define L2D_PATTERN_FG_COLOR_ALPHA L2D_PATTERN_FG_COLOR_TRUECOLOR 424 #define L2D_PATTERN_FG_COLOR_RED 0xA8F5 425 #define L2D_PATTERN_FG_COLOR_HI_COLOR 0xA8F6 426 #define L2D_PATTERN_FG_COLOR_GREEN L2D_PATTERN_FG_COLOR_HICOLOR 427 #define L2D_PATTERN_FG_COLOR_INDEX 0xA8F7 428 #define L2D_PATTERN_FG_COLOR_BLUE L2D_PATTERN_FG_COLOR_INDEX 429 #define L2D_PAD_1 0xA8F8 430 #define L2D_COMMAND_SET 0xA900 431 #define L2D_PAD_2 0xA904 432 #define L2D_END_0_END_1 0xA96C 433 #define L2D_END_1 L2D_END_0_END_1 434 #define L2D_END_0 0xA96E 435 #define L2D_DX 0xA970 436 #define L2D_X_START 0xA974 437 #define L2D_Y_START 0xA978 438 #define L2D_Y_COUNT 0xA97C 439 440 #define P2D_ADDRESS 0xACD4 441 #define P2D_SOURCE_ADDRESS 0xACD4 442 #define P2D_DEST_ADDRESS 0xACD8 443 #define P2D_CLIP_LEFT_RIGHT 0xACDC 444 #define P2D_CLIP_LEFT P2D_CLIP_LEFT_RIGHT 445 #define P2D_CLIP_RIGHT 0xACDE 446 #define P2D_CLIP_TOP_BOTTOM 0xACE0 447 #define P2D_CLIP_BOTTOM P2D_CLIP_TOP_BOTTOM 448 #define P2D_CLIP_TOP 0xACE2 449 #define P2D_DEST_SOURCE_PITCH 0xACE4 450 #define P2D_SOURCE_PITCH P2D_DEST_SOURCE_PITCH 451 #define P2D_DEST_PITCH 0xACE6 452 #define P2D_MONO_PATTERN 0xACE8 453 #define P2D_PATTERN_BG_COLOR_TRUE_COLOR 0xACF0 454 #define P2D_PATTERN_BG_COLOR_ALPHA P2D_PATTERN_BG_COLOR_TRUE_COLOR 455 #define P2D_PATTERN_BG_COLOR_RED 0xACF1 456 #define P2D_PATTERN_BG_COLOR_HI_COLOR 0xACF2 457 #define P2D_PATTERN_BG_COLOR_GREEN P2D_PATTERN_BG_COLOR_HI_COLOR 458 #define P2D_PATTERN_BG_COLOR_INDEX 0xACF3 459 #define P2D_PATTERN_BG_COLOR_BLUE P2D_PATTERN_BG_COLOR_INDEX 460 #define P2D_PATTERN_FG_COLOR_TRUE_COLOR 0xACF4 461 #define P2D_PATTERN_FG_COLOR_ALPHA P2D_PATTERN_FG_COLOR_TRUE_COLOR 462 #define P2D_PATTERN_FG_COLOR_RED 0xACF5 463 #define P2D_PATTERN_FG_COLOR_HI_COLOR 0xACF6 464 #define P2D_PATTERN_FG_COLOR_GREEN P2D_PATTERN_FG_COLOR_HI_COLOR 465 #define P2D_PATTERN_FG_COLOR_INDEX 0xACF7 466 #define P2D_PATTERN_FG_COLOR_BLUE P2D_PATTERN_FG_COLOR_INDEX 467 #define P2D_PAD_1 0xACF8 468 #define P2D_COMMAND_SET 0xAD00 469 #define P2D_PAD_2 0xAD04 470 #define P2D_RIGHT_DX 0xAD68 471 #define P2D_RIGHT_X_START 0xAD6C 472 #define P2D_LEFT_DX 0xAD70 473 #define P2D_LEFT_X_START 0xAD74 474 #define P2D_Y_START 0xAD78 475 #define P2D_Y_COUNT 0xAD7C 476 477 #define CMD_NOP (7 << 27) /* %1111 << 27 */ 478 #define CMD_LINE (3 << 27) /* %0011 << 27 */ 479 #define CMD_RECT (4 << 27) /* %0010 << 27 */ 480 #define CMD_POLYGON (5 << 27) /* %0101 << 27 */ 481 #define CMD_BITBLT (0 << 27) /* %0000 << 27 */ 482 483 #define CMD_SKIP_TRANSFER_BYTES_1 (1 << 12) /* %01 << 12 */ 484 #define CMD_SKIP_TRANSFER_BYTES_2 (2 << 12) /* %10 << 12 */ 485 #define CMD_SKIP_TRANSFER_BYTES_3 (3 << 12) /* %11 << 12 */ 486 487 #define CMD_TRANSFER_ALIGNMENT_BYTE (0 << 10) /* %00 << 10 */ 488 #define CMD_TRANSFER_ALIGNMENT_WORD (1 << 10) /* %01 << 10 */ 489 #define CMD_TRANSFER_ALIGNMENT_DOUBLEWORD (2 << 10) /* %10 << 10 */ 490 491 #define CMD_CHUNKY (0 << 2) /* %00 << 2 */ 492 #define CMD_HI_COLOR (1 << 2) /* %01 << 2 */ 493 #define CMD_TRUE_COLOR (2 << 2) /* %10 << 2 */ 494 495 #define ROP_FALSE 0x00 496 #define ROP_NOR 0x10 497 #define ROP_ONLYDST 0x20 498 #define ROP_NOTSRC 0x30 499 #define ROP_ONLYSRC 0x40 500 #define ROP_NOTDST 0x50 501 #define ROP_EOR 0x60 502 #define ROP_NAND 0x70 503 #define ROP_AND 0x80 504 #define ROP_NEOR 0x90 505 #define ROP_DST 0xA0 506 #define ROP_NOTONLYSRC 0xB0 507 #define ROP_SRC 0xC0 508 #define ROP_NOTONLYDST 0xD0 509 #define ROP_OR 0xE0 510 #define ROP_TRUE 0xF0 511 512 /* Pass-through */ 513 #if 0 /* XXX */ 514 #define PASS_ADDRESS 0x 515 #define PASS_ADDRESS_W 0x 516 #endif 517 518 /* Video DAC */ 519 #define VDAC_ADDRESS 0x03C8 520 #define VDAC_ADDRESS_W 0x03C8 521 #define VDAC_ADDRESS_R 0x03C7 522 #define VDAC_STATE 0x03C7 523 #define VDAC_DATA 0x03C9 524 #define VDAC_MASK 0x03C6 525 526 527 #define WGfx(ba, idx, val) \ 528 do { vgaw(ba, GCT_ADDRESS, idx); vgaw(ba, GCT_ADDRESS_W , val); } while (0) 529 530 #define WSeq(ba, idx, val) \ 531 do { vgaw(ba, SEQ_ADDRESS, idx); vgaw(ba, SEQ_ADDRESS_W , val); } while (0) 532 533 #define WCrt(ba, idx, val) \ 534 do { vgaw(ba, CRT_ADDRESS, idx); vgaw(ba, CRT_ADDRESS_W , val); } while (0) 535 536 #define WAttr(ba, idx, val) \ 537 do { \ 538 unsigned char tmp;\ 539 tmp = vgar(ba, ACT_ADDRESS_RESET);\ 540 vgaw(ba, ACT_ADDRESS_W, idx);\ 541 vgaw(ba, ACT_ADDRESS_W, val);\ 542 } while (0) 543 544 545 #define SetTextPlane(ba, m) \ 546 do { \ 547 WGfx(ba, GCT_ID_READ_MAP_SELECT, m & 3 );\ 548 WSeq(ba, SEQ_ID_MAP_MASK, (1 << (m & 3)));\ 549 } while (0) 550 551 552 /* Gfx engine busy wait */ 553 554 static __inline void 555 GfxBusyWait (ba) 556 volatile caddr_t ba; 557 { 558 int test; 559 560 do { 561 test = vgar32(ba, MR_SUBSYSTEM_STATUS_CNTL); 562 asm volatile ("nop"); 563 } while (!(test & (1 << 13))); 564 } 565 566 567 static __inline void 568 GfxFifoWait(ba) 569 volatile caddr_t ba; 570 { 571 #if 0 /* XXX */ 572 int test; 573 574 do { 575 test = vgar32(ba, MR_SUBSYSTEM_STATUS_CNTL); 576 } while (test & 0x0f); 577 #endif 578 } 579 580 581 /* Special wakeup/passthrough registers on graphics boards 582 * 583 * The methods have diverged a bit for each board, so 584 * WPass(P) has been converted into a set of specific 585 * __inline functions. 586 */ 587 588 static __inline unsigned char 589 RAttr(ba, idx) 590 volatile caddr_t ba; 591 short idx; 592 { 593 594 vgaw(ba, ACT_ADDRESS_W, idx); 595 delay(0); 596 return vgar(ba, ACT_ADDRESS_R); 597 } 598 599 static __inline unsigned char 600 RSeq(ba, idx) 601 volatile caddr_t ba; 602 short idx; 603 { 604 vgaw(ba, SEQ_ADDRESS, idx); 605 return vgar(ba, SEQ_ADDRESS_R); 606 } 607 608 static __inline unsigned char 609 RCrt(ba, idx) 610 volatile caddr_t ba; 611 short idx; 612 { 613 vgaw(ba, CRT_ADDRESS, idx); 614 return vgar(ba, CRT_ADDRESS_R); 615 } 616 617 static __inline unsigned char 618 RGfx(ba, idx) 619 volatile caddr_t ba; 620 short idx; 621 { 622 vgaw(ba, GCT_ADDRESS, idx); 623 return vgar(ba, GCT_ADDRESS_R); 624 } 625 626 #endif /* _GRF_CV3DREG_H */ 627 628
Indexes created Tue Oct 07 21:09:53 GMT 2025