grf_cv3dreg.h revision 1.9
1 /* $NetBSD: grf_cv3dreg.h,v 1.9 2007/03/05 19:48:19 he Exp $ */ 2 3 /* 4 * Copyright (c) 1995 Michael Teske 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 3. All advertising materials mentioning features or use of this software 16 * must display the following acknowledgement: 17 * This product includes software developed by Ezra Story and by Kari 18 * Mettinen. 19 * 4. The name of the author may not be used to endorse or promote products 20 * derived from this software without specific prior written permission 21 * 22 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 23 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 24 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 25 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 26 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 27 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 28 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 29 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 30 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 31 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 32 */ 33 34 #ifndef _GRF_CV3DREG_H 35 #define _GRF_CV3DREG_H 36 37 /* 38 * This is derived from ciruss driver source 39 */ 40 41 /* Extension to grfvideo_mode to support text modes. 42 * This can be passed to both text & gfx functions 43 * without worry. If gv.depth == 4, then the extended 44 * fields for a text mode are present. 45 */ 46 47 struct grfcv3dtext_mode { 48 struct grfvideo_mode gv; 49 unsigned short fx; /* font x dimension */ 50 unsigned short fy; /* font y dimension */ 51 unsigned short cols; /* screen dimensions */ 52 unsigned short rows; 53 void *fdata; /* font data */ 54 unsigned short fdstart; 55 unsigned short fdend; 56 }; 57 58 /* maximum console size */ 59 #define MAXROWS 200 60 #define MAXCOLS 200 61 62 /* read VGA register */ 63 #define vgar(ba, reg) \ 64 *(((volatile char *)ba)+(reg ^ 3)) 65 66 /* write VGA register */ 67 #define vgaw(ba, reg, val) \ 68 *(((volatile char *)ba)+(reg ^ 3)) = ((val) & 0xff) 69 70 /* MMIO access */ 71 #define ByteAccessIO(x) ( ((x) & 0x3ffc) | (((x) & 3)^3) | (((x) & 3) <<14) ) 72 73 #define vgario(ba, reg) \ 74 *(((volatile char *)ba) + ( ByteAccessIO(reg) )) 75 76 #define vgawio(ba, reg, val) \ 77 do { \ 78 if (!cv3d_zorroIII) { \ 79 *(((volatile char *)cv3d_vcode_switch_base) + \ 80 0x04) = (0x01 & 0xffff); \ 81 __asm volatile ("nop"); \ 82 } \ 83 *(((volatile char *)cv3d_special_register_base) + \ 84 ( ByteAccessIO(reg) & 0xffff )) = ((val) & 0xff); \ 85 if (!cv3d_zorroIII) { \ 86 *(((volatile char *)cv3d_vcode_switch_base) + \ 87 0x04) = (0x02 & 0xffff); \ 88 __asm volatile ("nop"); \ 89 } \ 90 } while (0) 91 92 /* read 32 Bit VGA register */ 93 #define vgar32(ba, reg) \ 94 *((volatile unsigned long *) (((volatile char *)ba)+reg)) 95 96 /* write 32 Bit VGA register */ 97 #define vgaw32(ba, reg, val) \ 98 *((volatile unsigned long *) (((volatile char *)ba)+reg)) = val 99 100 /* read 16 Bit VGA register */ 101 #define vgar16(ba, reg) \ 102 *((volatile unsigned short *) (((volatile char *)ba)+reg)) 103 104 /* write 16 Bit VGA register */ 105 #define vgaw16(ba, reg, val) \ 106 *((volatile unsigned short *) (((volatile char *)ba)+reg)) = val 107 108 /* XXX This is totaly untested */ 109 #define Select_Zorro2_FrameBuffer(flag) \ 110 do { \ 111 *(((volatile char *)cv3d_vcode_switch_base) + \ 112 0x08) = ((flag * 0x40) & 0xffff); \ 113 __asm volatile ("nop"); \ 114 } while (0) 115 116 int grfcv3d_cnprobe(void); 117 void grfcv3d_iteinit(struct grf_softc *); 118 static inline void GfxBusyWait(volatile void *); 119 static inline void GfxFifoWait(volatile void *); 120 static inline unsigned char RAttr(volatile void *, short); 121 static inline unsigned char RSeq(volatile void *, short); 122 static inline unsigned char RCrt(volatile void *, short); 123 static inline unsigned char RGfx(volatile void *, short); 124 125 126 /* 127 * defines for the used register addresses (mw) 128 * 129 * NOTE: there are some registers that have different addresses when 130 * in mono or color mode. We only support color mode, and thus 131 * some addresses won't work in mono-mode! 132 * 133 * General and VGA-registers taken from retina driver. Fixed a few 134 * bugs in it. (SR and GR read address is Port + 1, NOT Port) 135 * 136 */ 137 138 /* General Registers: */ 139 #define GREG_MISC_OUTPUT_R 0x03CC 140 #define GREG_MISC_OUTPUT_W 0x03C2 141 #define GREG_FEATURE_CONTROL_R 0x03CA 142 #define GREG_FEATURE_CONTROL_W 0x03DA 143 #define GREG_INPUT_STATUS0_R 0x03C2 144 #define GREG_INPUT_STATUS1_R 0x03DA 145 146 /* Setup Registers: */ 147 #define SREG_OPTION_SELECT 0x0102 148 #define SREG_VIDEO_SUBS_ENABLE 0x03C3 /* Trio64: 0x46E8 */ 149 150 /* Attribute Controller: */ 151 #define ACT_ADDRESS 0x03C0 152 #define ACT_ADDRESS_R 0x03C1 153 #define ACT_ADDRESS_W 0x03C0 154 #define ACT_ADDRESS_RESET 0x03DA 155 #define ACT_ID_PALETTE0 0x00 156 #define ACT_ID_PALETTE1 0x01 157 #define ACT_ID_PALETTE2 0x02 158 #define ACT_ID_PALETTE3 0x03 159 #define ACT_ID_PALETTE4 0x04 160 #define ACT_ID_PALETTE5 0x05 161 #define ACT_ID_PALETTE6 0x06 162 #define ACT_ID_PALETTE7 0x07 163 #define ACT_ID_PALETTE8 0x08 164 #define ACT_ID_PALETTE9 0x09 165 #define ACT_ID_PALETTE10 0x0A 166 #define ACT_ID_PALETTE11 0x0B 167 #define ACT_ID_PALETTE12 0x0C 168 #define ACT_ID_PALETTE13 0x0D 169 #define ACT_ID_PALETTE14 0x0E 170 #define ACT_ID_PALETTE15 0x0F 171 #define ACT_ID_ATTR_MODE_CNTL 0x10 172 #define ACT_ID_OVERSCAN_COLOR 0x11 173 #define ACT_ID_COLOR_PLANE_ENA 0x12 174 #define ACT_ID_HOR_PEL_PANNING 0x13 175 #define ACT_ID_COLOR_SELECT 0x14 /* ACT_ID_PIXEL_PADDING */ 176 177 /* Graphics Controller: */ 178 #define GCT_ADDRESS 0x03CE 179 #define GCT_ADDRESS_R 0x03CF 180 #define GCT_ADDRESS_W 0x03CF 181 #define GCT_ID_SET_RESET 0x00 182 #define GCT_ID_ENABLE_SET_RESET 0x01 183 #define GCT_ID_COLOR_COMPARE 0x02 184 #define GCT_ID_DATA_ROTATE 0x03 185 #define GCT_ID_READ_MAP_SELECT 0x04 186 #define GCT_ID_GRAPHICS_MODE 0x05 187 #define GCT_ID_MISC 0x06 188 #define GCT_ID_COLOR_XCARE 0x07 189 #define GCT_ID_BITMASK 0x08 190 191 /* Sequencer: */ 192 #define SEQ_ADDRESS 0x03C4 193 #define SEQ_ADDRESS_R 0x03C5 194 #define SEQ_ADDRESS_W 0x03C5 195 #define SEQ_ID_RESET 0x00 196 #define SEQ_ID_CLOCKING_MODE 0x01 197 #define SEQ_ID_MAP_MASK 0x02 198 #define SEQ_ID_CHAR_MAP_SELECT 0x03 199 #define SEQ_ID_MEMORY_MODE 0x04 200 #define SEQ_ID_UNKNOWN1 0x05 201 #define SEQ_ID_UNKNOWN2 0x06 202 #define SEQ_ID_UNKNOWN3 0x07 203 /* S3 extensions */ 204 #define SEQ_ID_UNLOCK_EXT 0x08 205 #define SEQ_ID_MMIO_SELECT 0x09 /* Trio64: SEQ_ID_EXT_SEQ_REG9 */ 206 #define SEQ_ID_BUS_REQ_CNTL 0x0A 207 #define SEQ_ID_EXT_MISC_SEQ 0x0B 208 #define SEQ_ID_UNKNOWN4 0x0C 209 #define SEQ_ID_EXT_SEQ 0x0D 210 #define SEQ_ID_UNKNOWN5 0x0E 211 #define SEQ_ID_UNKNOWN6 0x0F 212 #define SEQ_ID_MCLK_LO 0x10 213 #define SEQ_ID_MCLK_HI 0x11 214 #define SEQ_ID_DCLK_LO 0x12 215 #define SEQ_ID_DCLK_HI 0x13 216 #define SEQ_ID_CLKSYN_CNTL_1 0x14 217 #define SEQ_ID_CLKSYN_CNTL_2 0x15 218 #define SEQ_ID_CLKSYN_TEST_HI 0x16 /* reserved for S3 testing of the */ 219 #define SEQ_ID_CLKSYN_TEST_LO 0x17 /* internal clock synthesizer */ 220 #define SEQ_ID_RAMDAC_CNTL 0x18 221 #define SEQ_ID_MORE_MAGIC 0x1A /* not available on the Virge */ 222 #define SEQ_ID_SIGNAL_SELECT 0x1C 223 224 /* CRT Controller: */ 225 #define CRT_ADDRESS 0x03D4 226 #define CRT_ADDRESS_R 0x03D5 227 #define CRT_ADDRESS_W 0x03D5 228 #define CRT_ID_HOR_TOTAL 0x00 229 #define CRT_ID_HOR_DISP_ENA_END 0x01 230 #define CRT_ID_START_HOR_BLANK 0x02 231 #define CRT_ID_END_HOR_BLANK 0x03 232 #define CRT_ID_START_HOR_RETR 0x04 233 #define CRT_ID_END_HOR_RETR 0x05 234 #define CRT_ID_VER_TOTAL 0x06 235 #define CRT_ID_OVERFLOW 0x07 236 #define CRT_ID_PRESET_ROW_SCAN 0x08 237 #define CRT_ID_MAX_SCAN_LINE 0x09 238 #define CRT_ID_CURSOR_START 0x0A 239 #define CRT_ID_CURSOR_END 0x0B 240 #define CRT_ID_START_ADDR_HIGH 0x0C 241 #define CRT_ID_START_ADDR_LOW 0x0D 242 #define CRT_ID_CURSOR_LOC_HIGH 0x0E 243 #define CRT_ID_CURSOR_LOC_LOW 0x0F 244 #define CRT_ID_START_VER_RETR 0x10 245 #define CRT_ID_END_VER_RETR 0x11 246 #define CRT_ID_VER_DISP_ENA_END 0x12 247 #define CRT_ID_SCREEN_OFFSET 0x13 248 #define CRT_ID_UNDERLINE_LOC 0x14 249 #define CRT_ID_START_VER_BLANK 0x15 250 #define CRT_ID_END_VER_BLANK 0x16 251 #define CRT_ID_MODE_CONTROL 0x17 252 #define CRT_ID_LINE_COMPARE 0x18 253 #define CRT_ID_GD_LATCH_RBACK 0x22 254 #define CRT_ID_ACT_TOGGLE_RBACK 0x24 255 #define CRT_ID_ACT_INDEX_RBACK 0x26 256 /* S3 extensions: S3 VGA Registers */ 257 #define CRT_ID_DEVICE_HIGH 0x2D 258 #define CRT_ID_DEVICE_LOW 0x2E 259 #define CRT_ID_REVISION 0x2F 260 #define CRT_ID_CHIP_ID_REV 0x30 261 #define CRT_ID_MEMORY_CONF 0x31 262 #define CRT_ID_BACKWAD_COMP_1 0x32 263 #define CRT_ID_BACKWAD_COMP_2 0x33 264 #define CRT_ID_BACKWAD_COMP_3 0x34 265 #define CRT_ID_REGISTER_LOCK 0x35 266 #define CRT_ID_CONFIG_1 0x36 267 #define CRT_ID_CONFIG_2 0x37 268 #define CRT_ID_REGISTER_LOCK_1 0x38 269 #define CRT_ID_REGISTER_LOCK_2 0x39 270 #define CRT_ID_MISC_1 0x3A 271 #define CRT_ID_DISPLAY_FIFO 0x3B 272 #define CRT_ID_LACE_RETR_START 0x3C 273 /* S3 extensions: System Control Registers */ 274 #define CRT_ID_SYSTEM_CONFIG 0x40 275 #define CRT_ID_BIOS_FLAG 0x41 276 #define CRT_ID_LACE_CONTROL 0x42 277 #define CRT_ID_EXT_MODE 0x43 278 #define CRT_ID_HWGC_MODE 0x45 /* HWGC = Hardware Graphics Cursor */ 279 #define CRT_ID_HWGC_ORIGIN_X_HI 0x46 280 #define CRT_ID_HWGC_ORIGIN_X_LO 0x47 281 #define CRT_ID_HWGC_ORIGIN_Y_HI 0x48 282 #define CRT_ID_HWGC_ORIGIN_Y_LO 0x49 283 #define CRT_ID_HWGC_FG_STACK 0x4A 284 #define CRT_ID_HWGC_BG_STACK 0x4B 285 #define CRT_ID_HWGC_START_AD_HI 0x4C 286 #define CRT_ID_HWGC_START_AD_LO 0x4D 287 #define CRT_ID_HWGC_DSTART_X 0x4E 288 #define CRT_ID_HWGC_DSTART_Y 0x4F 289 /* S3 extensions: System Extension Registers */ 290 #define CRT_ID_EXT_SYS_CNTL_1 0x50 291 #define CRT_ID_EXT_SYS_CNTL_2 0x51 292 #define CRT_ID_EXT_BIOS_FLAG_1 0x52 293 #define CRT_ID_EXT_MEM_CNTL_1 0x53 294 #define CRT_ID_EXT_MEM_CNTL_2 0x54 295 #define CRT_ID_EXT_DAC_CNTL 0x55 296 #define CRT_ID_EX_SYNC_1 0x56 297 #define CRT_ID_EX_SYNC_2 0x57 298 #define CRT_ID_LAW_CNTL 0x58 /* LAW = Linear Address Window */ 299 #define CRT_ID_LAW_POS_HI 0x59 300 #define CRT_ID_LAW_POS_LO 0x5A 301 #define CRT_ID_GOUT_PORT 0x5C 302 #define CRT_ID_EXT_HOR_OVF 0x5D 303 #define CRT_ID_EXT_VER_OVF 0x5E 304 #define CRT_ID_EXT_MEM_CNTL_3 0x60 305 #define CRT_ID_EXT_MEM_CNTL_4 0x61 /* only available on the Virge */ 306 #define CRT_ID_EX_SYNC_3 0x63 /* not available on the Virge */ 307 #define CRT_ID_EXT_MISC_CNTL 0x65 308 #define CRT_ID_EXT_MISC_CNTL_1 0x66 309 #define CRT_ID_EXT_MISC_CNTL_2 0x67 310 #define CRT_ID_CONFIG_3 0x68 311 #define CRT_ID_EXT_SYS_CNTL_3 0x69 312 #define CRT_ID_EXT_SYS_CNTL_4 0x6A 313 #define CRT_ID_EXT_BIOS_FLAG_3 0x6B 314 #define CRT_ID_EXT_BIOS_FLAG_4 0x6C 315 #define CRT_ID_EXT_BIOS_FLAG_5 0x6D /* only available on the Virge */ 316 #define CRT_ID_RAMDAC_SIG_TEST 0x6E /* only available on the Virge */ 317 #define CRT_ID_CONFIG_4 0x6F /* only available on the Virge */ 318 319 /* Streams Processor */ 320 #define SP_PRIMARY_CONTROL 0x8180 321 #define SP_COLOR_CHROMA_KEY_CONTROL 0x8184 322 #define SP_SECONDARY_CONTROL 0x8190 323 #define SP_CHROMA_KEY_UPPER_BOUND 0x8194 324 #define SP_SECONDARY_CONSTANTS 0x8198 325 #define SP_BLEND_CONTROL 0x81A0 326 #define SP_PRIMARY_ADDRESS_0 0x81C0 327 #define SP_PRIMARY_ADDRESS_1 0x81C4 328 #define SP_PRIMARY_STRIDE 0x81C8 329 #define SP_DOUBLE_BUFFER_LPB_SUPPORT 0x81CC 330 #define SP_SECONDARY_ADDRESS_0 0x81D0 331 #define SP_SECONDARY_ADDRESS_1 0x81D4 332 #define SP_SECONDARY_STRIDE 0x81D8 333 #define SP_OPAQUE_OVERLAY_CONTROL 0x81DC 334 #define SP_K1_VERTICAL_SCALE_FACTOR 0x81E0 335 #define SP_K2_VERTICAL_SCALE_FACTOR 0x81E4 336 #define SP_DDA_VERTICAL_ACCUMULATOR 0x81E8 337 #define SP_FIFO_CONTROL 0x81EC 338 #define SP_PRIMARY_WINDOW_TOP_LEFT 0x81F0 339 #define SP_PRIMARY_WINDOW_SIZE 0x81F4 340 #define SP_SECONDARY_WINDOW_TOP_LEFT 0x81F8 341 #define SP_SECONDARY_WINDOW_SIZE 0x81FC 342 343 /* Memory Port Controller */ 344 #define MPC_FIFO_CONTROL 0x8200 345 #define MPC_MIU_CONTROL 0x8204 346 #define MPC_STREAMS_TIMEOUT 0x8208 347 #define MPC_MISC_TIMEOUT 0x820C 348 #define MPC_DMA_READ_BASE_ADDRESS 0x8220 349 #define MPC_DMA_READ_STRIDE_WIDTH 0x8224 350 351 /* Miscellaneous Registers */ 352 #define MR_SUBSYSTEM_STATUS_CNTL 0x8504 353 #define MR_ADVANCED_FUNCTION_CONTROL 0x850C 354 355 /* S3d Engine */ 356 #define S3D_BIT_BLT_RECT_FILL 0xA400 357 #define S3D_LINE_2D 0xA800 358 #define S3D_POLYGON_2D 0xAC00 359 #define S3D_LINE_3D 0xB000 360 #define S3D_TRIANGLE_3D 0xB400 361 362 #define BLT_ADDRESS 0xA4D4 363 #define BLT_SOURCE_ADDRESS 0xA4D4 364 #define BLT_DEST_ADDRESS 0xA4D8 365 #define BLT_CLIP_LEFT_RIGHT 0xA4DC 366 #define BLT_CLIP_LEFT BLT_CLIP_LEFT_RIGHT 367 #define BLT_CLIP_RIGHT 0xA4DE 368 #define BLT_CLIP_TOP_BOTTOM 0xA4E0 369 #define BLT_CLIP_BOTTOM BLT_CLIP_TOP_BOTTOM 370 #define BLT_CLIP_TOP 0xA4E2 371 #define BLT_DEST_SOURCE_PITCH 0xA4E4 372 #define BLT_SOURCE_PITCH BLT_DEST_SOURCE_PITCH 373 #define BLT_DEST_PITCH 0xA4E6 374 #define BLT_MONO_PATTERN 0xA4E8 375 #define BLT_MONO_PATTERN_0 BLT_MONO_PATTERN 376 #define BLT_MONO_PATTERN_1 0xA4EC 377 #define BLT_PATTERN_BG_COLOR 0xA4F0 378 #define BLT_PATTERN_BG_COLOR_TRUE_COLOR BLT_PATTERN_BG_COLOR 379 #define BLT_PATTERN_BG_COLOR_ALPHA BLT_PATTERN_BG_COLOR 380 #define BLT_PATTERN_BG_COLOR_RED 0xA4F1 381 #define BLT_PATTERN_BG_COLOR_HI_COLOR 0xA4F2 382 #define BLT_PATTERN_BG_COLOR_GREEN BLT_PATTERN_BG_COLOR_HI_COLOR 383 #define BLT_PATTERN_BG_COLOR_INDEX 0xA4F3 384 #define BLT_PATTERN_BG_COLOR_BLUE BLT_PATTERN_BG_COLOR_INDEX 385 #define BLT_PATTERN_FG_COLOR 0xA4F4 386 #define BLT_PATTERN_FG_COLOR_TRUE_COLOR BLT_PATTERN_FG_COLOR 387 #define BLT_PATTERN_FG_COLOR_ALPHA BLT_PATTERN_FG_COLOR 388 #define BLT_PATTERN_FG_COLOR_RED 0xA4F5 389 #define BLT_PATTERN_FG_COLOR_HI_COLOR 0xA4F6 390 #define BLT_PATTERN_FG_COLOR_GREEN BLT_PATTERN_FG_COLOR_HI_COLOR 391 #define BLT_PATTERN_FG_COLOR_INDEX 0xA4F7 392 #define BLT_PATTERN_FG_COLOR_BLUE BLT_PATTERN_FG_COLOR_INDEX 393 #define BLT_SOURCE_BG_COLOR 0xA4F8 394 #define BLT_SOURCE_BG_COLOR_TRUE_COLOR BLT_SOURCE_BG_COLOR 395 #define BLT_SOURCE_BG_COLOR_ALPHA BLT_SOURCE_BG_COLOR 396 #define BLT_SOURCE_BG_COLOR_RED 0xA4F9 397 #define BLT_SOURCE_BG_COLOR_HI_COLOR 0xA4FA 398 #define BLT_SOURCE_BG_COLOR_GREEN BLT_SOURCE_BG_COLOR_HI_COLOR 399 #define BLT_SOURCE_BG_COLOR_INDEX 0xA4FB 400 #define BLT_SOURCE_BG_COLOR_BLUE BLT_SOURCE_BG_COLOR_INDEX 401 #define BLT_SOURCE_FG_COLOR 0xA4FC 402 #define BLT_SOURCE_FG_COLOR_TRUE_COLOR BLT_SOURCE_FG_COLOR 403 #define BLT_SOURCE_FG_COLOR_ALPHA BLT_SOURCE_FG_COLOR 404 #define BLT_SOURCE_FG_COLOR_RED 0xA4FD 405 #define BLT_SOURCE_FG_COLOR_HI_COLOR 0xA4FE 406 #define BLT_SOURCE_FG_COLOR_GREEN BLT_SOURCE_FG_COLOR_HI_COLOR 407 #define BLT_SOURCE_FG_COLOR_INDEX 0xA4FF 408 #define BLT_SOURCE_FG_COLOR_BLUE BLT_SOURCE_FG_COLOR_INDEX 409 #define BLT_COMMAND_SET 0xA500 410 #define BLT_WIDTH_HEIGHT 0xA504 411 #define BLT_HEIGHT BLT_WIDTH_HEIGHT 412 #define BLT_WIDTH 0xA506 413 #define BLT_SOURCE_XY 0xA508 414 #define BLT_SOURCE_Y BLT_SOURCE_XY 415 #define BLT_SOURCE_X 0xA50A 416 #define BLT_DESTINATION_XY 0xA50C 417 #define BLT_DESTINATION_Y BLT_DESTINATION_XY 418 #define BLT_DESTINATION_X 0xA50E 419 420 #define L2D_ADDRESS 0xA8D4 421 #define L2D_SOURCE_ADDRESS 0xA8D4 422 #define L2D_DEST_ADDRESS 0xA8D8 423 #define L2D_CLIP_LEFT_RIGHT 0xA8DC 424 #define L2D_CLIP_LEFT L2D_CLIP_LEFT_RIGHT 425 #define L2D_CLIP_RIGHT 0xA8DE 426 #define L2D_CLIP_TOP_BOTTOM 0xA8E0 427 #define L2D_CLIP_BOTTOM L2D_CLIP_TOP_BOTTOM 428 #define L2D_CLIP_TOP 0xA8E2 429 #define L2D_DEST_SOURCE_PITCH 0xA8E4 430 #define L2D_SOURCE_PITCH L2D_DEST_SOURCE_PITCH 431 #define L2D_DEST_PITCH 0xA8E6 432 #define L2D_PAD_0 0xA8E8 433 #define L2D_PATTERN_FG_COLOR_TRUE_COLOR 0xA8F4 434 #define L2D_PATTERN_FG_COLOR_ALPHA L2D_PATTERN_FG_COLOR_TRUECOLOR 435 #define L2D_PATTERN_FG_COLOR_RED 0xA8F5 436 #define L2D_PATTERN_FG_COLOR_HI_COLOR 0xA8F6 437 #define L2D_PATTERN_FG_COLOR_GREEN L2D_PATTERN_FG_COLOR_HICOLOR 438 #define L2D_PATTERN_FG_COLOR_INDEX 0xA8F7 439 #define L2D_PATTERN_FG_COLOR_BLUE L2D_PATTERN_FG_COLOR_INDEX 440 #define L2D_PAD_1 0xA8F8 441 #define L2D_COMMAND_SET 0xA900 442 #define L2D_PAD_2 0xA904 443 #define L2D_END_0_END_1 0xA96C 444 #define L2D_END_1 L2D_END_0_END_1 445 #define L2D_END_0 0xA96E 446 #define L2D_DX 0xA970 447 #define L2D_X_START 0xA974 448 #define L2D_Y_START 0xA978 449 #define L2D_Y_COUNT 0xA97C 450 451 #define P2D_ADDRESS 0xACD4 452 #define P2D_SOURCE_ADDRESS 0xACD4 453 #define P2D_DEST_ADDRESS 0xACD8 454 #define P2D_CLIP_LEFT_RIGHT 0xACDC 455 #define P2D_CLIP_LEFT P2D_CLIP_LEFT_RIGHT 456 #define P2D_CLIP_RIGHT 0xACDE 457 #define P2D_CLIP_TOP_BOTTOM 0xACE0 458 #define P2D_CLIP_BOTTOM P2D_CLIP_TOP_BOTTOM 459 #define P2D_CLIP_TOP 0xACE2 460 #define P2D_DEST_SOURCE_PITCH 0xACE4 461 #define P2D_SOURCE_PITCH P2D_DEST_SOURCE_PITCH 462 #define P2D_DEST_PITCH 0xACE6 463 #define P2D_MONO_PATTERN 0xACE8 464 #define P2D_PATTERN_BG_COLOR_TRUE_COLOR 0xACF0 465 #define P2D_PATTERN_BG_COLOR_ALPHA P2D_PATTERN_BG_COLOR_TRUE_COLOR 466 #define P2D_PATTERN_BG_COLOR_RED 0xACF1 467 #define P2D_PATTERN_BG_COLOR_HI_COLOR 0xACF2 468 #define P2D_PATTERN_BG_COLOR_GREEN P2D_PATTERN_BG_COLOR_HI_COLOR 469 #define P2D_PATTERN_BG_COLOR_INDEX 0xACF3 470 #define P2D_PATTERN_BG_COLOR_BLUE P2D_PATTERN_BG_COLOR_INDEX 471 #define P2D_PATTERN_FG_COLOR_TRUE_COLOR 0xACF4 472 #define P2D_PATTERN_FG_COLOR_ALPHA P2D_PATTERN_FG_COLOR_TRUE_COLOR 473 #define P2D_PATTERN_FG_COLOR_RED 0xACF5 474 #define P2D_PATTERN_FG_COLOR_HI_COLOR 0xACF6 475 #define P2D_PATTERN_FG_COLOR_GREEN P2D_PATTERN_FG_COLOR_HI_COLOR 476 #define P2D_PATTERN_FG_COLOR_INDEX 0xACF7 477 #define P2D_PATTERN_FG_COLOR_BLUE P2D_PATTERN_FG_COLOR_INDEX 478 #define P2D_PAD_1 0xACF8 479 #define P2D_COMMAND_SET 0xAD00 480 #define P2D_PAD_2 0xAD04 481 #define P2D_RIGHT_DX 0xAD68 482 #define P2D_RIGHT_X_START 0xAD6C 483 #define P2D_LEFT_DX 0xAD70 484 #define P2D_LEFT_X_START 0xAD74 485 #define P2D_Y_START 0xAD78 486 #define P2D_Y_COUNT 0xAD7C 487 488 #define CMD_NOP (7 << 27) /* %1111 << 27 */ 489 #define CMD_LINE (3 << 27) /* %0011 << 27 */ 490 #define CMD_RECT (4 << 27) /* %0010 << 27 */ 491 #define CMD_POLYGON (5 << 27) /* %0101 << 27 */ 492 #define CMD_BITBLT (0 << 27) /* %0000 << 27 */ 493 494 #define CMD_SKIP_TRANSFER_BYTES_1 (1 << 12) /* %01 << 12 */ 495 #define CMD_SKIP_TRANSFER_BYTES_2 (2 << 12) /* %10 << 12 */ 496 #define CMD_SKIP_TRANSFER_BYTES_3 (3 << 12) /* %11 << 12 */ 497 498 #define CMD_TRANSFER_ALIGNMENT_BYTE (0 << 10) /* %00 << 10 */ 499 #define CMD_TRANSFER_ALIGNMENT_WORD (1 << 10) /* %01 << 10 */ 500 #define CMD_TRANSFER_ALIGNMENT_DOUBLEWORD (2 << 10) /* %10 << 10 */ 501 502 #define CMD_CHUNKY (0 << 2) /* %00 << 2 */ 503 #define CMD_HI_COLOR (1 << 2) /* %01 << 2 */ 504 #define CMD_TRUE_COLOR (2 << 2) /* %10 << 2 */ 505 506 #define ROP_FALSE 0x00 507 #define ROP_NOR 0x10 508 #define ROP_ONLYDST 0x20 509 #define ROP_NOTSRC 0x30 510 #define ROP_ONLYSRC 0x40 511 #define ROP_NOTDST 0x50 512 #define ROP_EOR 0x60 513 #define ROP_NAND 0x70 514 #define ROP_AND 0x80 515 #define ROP_NEOR 0x90 516 #define ROP_DST 0xA0 517 #define ROP_NOTONLYSRC 0xB0 518 #define ROP_SRC 0xC0 519 #define ROP_NOTONLYDST 0xD0 520 #define ROP_OR 0xE0 521 #define ROP_TRUE 0xF0 522 523 /* Pass-through */ 524 #if 0 /* XXX */ 525 #define PASS_ADDRESS 0x 526 #define PASS_ADDRESS_W 0x 527 #endif 528 529 /* Video DAC */ 530 #define VDAC_ADDRESS 0x03C8 531 #define VDAC_ADDRESS_W 0x03C8 532 #define VDAC_ADDRESS_R 0x03C7 533 #define VDAC_STATE 0x03C7 534 #define VDAC_DATA 0x03C9 535 #define VDAC_MASK 0x03C6 536 537 538 #define WGfx(ba, idx, val) \ 539 do { vgaw(ba, GCT_ADDRESS, idx); vgaw(ba, GCT_ADDRESS_W , val); } while (0) 540 541 #define WSeq(ba, idx, val) \ 542 do { vgaw(ba, SEQ_ADDRESS, idx); vgaw(ba, SEQ_ADDRESS_W , val); } while (0) 543 544 #define WCrt(ba, idx, val) \ 545 do { vgaw(ba, CRT_ADDRESS, idx); vgaw(ba, CRT_ADDRESS_W , val); } while (0) 546 547 #define WAttr(ba, idx, val) \ 548 do { \ 549 unsigned char tmp;\ 550 tmp = vgar(ba, ACT_ADDRESS_RESET);\ 551 vgaw(ba, ACT_ADDRESS_W, idx);\ 552 vgaw(ba, ACT_ADDRESS_W, val);\ 553 } while (0) 554 555 556 #define SetTextPlane(ba, m) \ 557 do { \ 558 WGfx(ba, GCT_ID_READ_MAP_SELECT, m & 3 );\ 559 WSeq(ba, SEQ_ID_MAP_MASK, (1 << (m & 3)));\ 560 } while (0) 561 562 563 /* Gfx engine busy wait */ 564 565 static inline void 566 GfxBusyWait (ba) 567 volatile void *ba; 568 { 569 int test; 570 571 do { 572 test = vgar32(ba, MR_SUBSYSTEM_STATUS_CNTL); 573 __asm volatile ("nop"); 574 } while (!(test & (1 << 13))); 575 } 576 577 578 static inline void 579 GfxFifoWait(ba) 580 volatile void *ba; 581 { 582 #if 0 /* XXX */ 583 int test; 584 585 do { 586 test = vgar32(ba, MR_SUBSYSTEM_STATUS_CNTL); 587 } while (test & 0x0f); 588 #endif 589 } 590 591 592 /* Special wakeup/passthrough registers on graphics boards 593 * 594 * The methods have diverged a bit for each board, so 595 * WPass(P) has been converted into a set of specific 596 * inline functions. 597 */ 598 599 static inline unsigned char 600 RAttr(ba, idx) 601 volatile void *ba; 602 short idx; 603 { 604 605 vgaw(ba, ACT_ADDRESS_W, idx); 606 delay(0); 607 return vgar(ba, ACT_ADDRESS_R); 608 } 609 610 static inline unsigned char 611 RSeq(ba, idx) 612 volatile void *ba; 613 short idx; 614 { 615 vgaw(ba, SEQ_ADDRESS, idx); 616 return vgar(ba, SEQ_ADDRESS_R); 617 } 618 619 static inline unsigned char 620 RCrt(ba, idx) 621 volatile void *ba; 622 short idx; 623 { 624 vgaw(ba, CRT_ADDRESS, idx); 625 return vgar(ba, CRT_ADDRESS_R); 626 } 627 628 static inline unsigned char 629 RGfx(ba, idx) 630 volatile void *ba; 631 short idx; 632 { 633 vgaw(ba, GCT_ADDRESS, idx); 634 return vgar(ba, GCT_ADDRESS_R); 635 } 636 637 #endif /* _GRF_CV3DREG_H */ 638
Indexes created Tue Oct 07 21:09:53 GMT 2025