grf_cv3dreg.h revision 1.9.78.1
1 /* $NetBSD: grf_cv3dreg.h,v 1.9.78.1 2012/04/17 00:06:01 yamt Exp $ */ 2 3 /* 4 * Copyright (c) 1995 Michael Teske 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 3. All advertising materials mentioning features or use of this software 16 * must display the following acknowledgement: 17 * This product includes software developed by Ezra Story and by Kari 18 * Mettinen. 19 * 4. The name of the author may not be used to endorse or promote products 20 * derived from this software without specific prior written permission 21 * 22 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 23 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 24 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 25 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 26 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 27 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 28 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 29 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 30 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 31 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 32 */ 33 34 #ifndef _GRF_CV3DREG_H 35 #define _GRF_CV3DREG_H 36 37 /* 38 * This is derived from Cirrus driver source. 39 */ 40 41 /* Extension to grfvideo_mode to support text modes. 42 * This can be passed to both text & gfx functions 43 * without worry. If gv.depth == 4, then the extended 44 * fields for a text mode are present. 45 */ 46 47 struct grfcv3dtext_mode { 48 struct grfvideo_mode gv; 49 unsigned short fx; /* font x dimension */ 50 unsigned short fy; /* font y dimension */ 51 unsigned short cols; /* screen dimensions */ 52 unsigned short rows; 53 void *fdata; /* font data */ 54 unsigned short fdstart; 55 unsigned short fdend; 56 }; 57 58 /* read VGA register */ 59 #define vgar(ba, reg) \ 60 *(((volatile char *)ba)+(reg ^ 3)) 61 62 /* write VGA register */ 63 #define vgaw(ba, reg, val) \ 64 *(((volatile char *)ba)+(reg ^ 3)) = ((val) & 0xff) 65 66 /* MMIO access */ 67 #define ByteAccessIO(x) ( ((x) & 0x3ffc) | (((x) & 3)^3) | (((x) & 3) <<14) ) 68 69 #define vgario(ba, reg) \ 70 *(((volatile char *)ba) + ( ByteAccessIO(reg) )) 71 72 #define vgawio(ba, reg, val) \ 73 do { \ 74 if (!cv3d_zorroIII) { \ 75 *(((volatile char *)cv3d_vcode_switch_base) + \ 76 0x04) = (0x01 & 0xffff); \ 77 __asm volatile ("nop"); \ 78 } \ 79 *(((volatile char *)cv3d_special_register_base) + \ 80 ( ByteAccessIO(reg) & 0xffff )) = ((val) & 0xff); \ 81 if (!cv3d_zorroIII) { \ 82 *(((volatile char *)cv3d_vcode_switch_base) + \ 83 0x04) = (0x02 & 0xffff); \ 84 __asm volatile ("nop"); \ 85 } \ 86 } while (0) 87 88 /* read 32 Bit VGA register */ 89 #define vgar32(ba, reg) \ 90 *((volatile unsigned long *) (((volatile char *)ba)+reg)) 91 92 /* write 32 Bit VGA register */ 93 #define vgaw32(ba, reg, val) \ 94 *((volatile unsigned long *) (((volatile char *)ba)+reg)) = val 95 96 /* read 16 Bit VGA register */ 97 #define vgar16(ba, reg) \ 98 *((volatile unsigned short *) (((volatile char *)ba)+reg)) 99 100 /* write 16 Bit VGA register */ 101 #define vgaw16(ba, reg, val) \ 102 *((volatile unsigned short *) (((volatile char *)ba)+reg)) = val 103 104 /* XXX This is totaly untested */ 105 #define Select_Zorro2_FrameBuffer(flag) \ 106 do { \ 107 *(((volatile char *)cv3d_vcode_switch_base) + \ 108 0x08) = ((flag * 0x40) & 0xffff); \ 109 __asm volatile ("nop"); \ 110 } while (0) 111 112 int grfcv3d_cnprobe(void); 113 void grfcv3d_iteinit(struct grf_softc *); 114 static inline void GfxBusyWait(volatile void *); 115 static inline void GfxFifoWait(volatile void *); 116 static inline unsigned char RAttr(volatile void *, short); 117 static inline unsigned char RSeq(volatile void *, short); 118 static inline unsigned char RCrt(volatile void *, short); 119 static inline unsigned char RGfx(volatile void *, short); 120 121 122 /* 123 * defines for the used register addresses (mw) 124 * 125 * NOTE: there are some registers that have different addresses when 126 * in mono or color mode. We only support color mode, and thus 127 * some addresses won't work in mono-mode! 128 * 129 * General and VGA-registers taken from retina driver. Fixed a few 130 * bugs in it. (SR and GR read address is Port + 1, NOT Port) 131 * 132 */ 133 134 /* General Registers: */ 135 #define GREG_MISC_OUTPUT_R 0x03CC 136 #define GREG_MISC_OUTPUT_W 0x03C2 137 #define GREG_FEATURE_CONTROL_R 0x03CA 138 #define GREG_FEATURE_CONTROL_W 0x03DA 139 #define GREG_INPUT_STATUS0_R 0x03C2 140 #define GREG_INPUT_STATUS1_R 0x03DA 141 142 /* Setup Registers: */ 143 #define SREG_OPTION_SELECT 0x0102 144 #define SREG_VIDEO_SUBS_ENABLE 0x03C3 /* Trio64: 0x46E8 */ 145 146 /* Attribute Controller: */ 147 #define ACT_ADDRESS 0x03C0 148 #define ACT_ADDRESS_R 0x03C1 149 #define ACT_ADDRESS_W 0x03C0 150 #define ACT_ADDRESS_RESET 0x03DA 151 #define ACT_ID_PALETTE0 0x00 152 #define ACT_ID_PALETTE1 0x01 153 #define ACT_ID_PALETTE2 0x02 154 #define ACT_ID_PALETTE3 0x03 155 #define ACT_ID_PALETTE4 0x04 156 #define ACT_ID_PALETTE5 0x05 157 #define ACT_ID_PALETTE6 0x06 158 #define ACT_ID_PALETTE7 0x07 159 #define ACT_ID_PALETTE8 0x08 160 #define ACT_ID_PALETTE9 0x09 161 #define ACT_ID_PALETTE10 0x0A 162 #define ACT_ID_PALETTE11 0x0B 163 #define ACT_ID_PALETTE12 0x0C 164 #define ACT_ID_PALETTE13 0x0D 165 #define ACT_ID_PALETTE14 0x0E 166 #define ACT_ID_PALETTE15 0x0F 167 #define ACT_ID_ATTR_MODE_CNTL 0x10 168 #define ACT_ID_OVERSCAN_COLOR 0x11 169 #define ACT_ID_COLOR_PLANE_ENA 0x12 170 #define ACT_ID_HOR_PEL_PANNING 0x13 171 #define ACT_ID_COLOR_SELECT 0x14 /* ACT_ID_PIXEL_PADDING */ 172 173 /* Graphics Controller: */ 174 #define GCT_ADDRESS 0x03CE 175 #define GCT_ADDRESS_R 0x03CF 176 #define GCT_ADDRESS_W 0x03CF 177 #define GCT_ID_SET_RESET 0x00 178 #define GCT_ID_ENABLE_SET_RESET 0x01 179 #define GCT_ID_COLOR_COMPARE 0x02 180 #define GCT_ID_DATA_ROTATE 0x03 181 #define GCT_ID_READ_MAP_SELECT 0x04 182 #define GCT_ID_GRAPHICS_MODE 0x05 183 #define GCT_ID_MISC 0x06 184 #define GCT_ID_COLOR_XCARE 0x07 185 #define GCT_ID_BITMASK 0x08 186 187 /* Sequencer: */ 188 #define SEQ_ADDRESS 0x03C4 189 #define SEQ_ADDRESS_R 0x03C5 190 #define SEQ_ADDRESS_W 0x03C5 191 #define SEQ_ID_RESET 0x00 192 #define SEQ_ID_CLOCKING_MODE 0x01 193 #define SEQ_ID_MAP_MASK 0x02 194 #define SEQ_ID_CHAR_MAP_SELECT 0x03 195 #define SEQ_ID_MEMORY_MODE 0x04 196 #define SEQ_ID_UNKNOWN1 0x05 197 #define SEQ_ID_UNKNOWN2 0x06 198 #define SEQ_ID_UNKNOWN3 0x07 199 /* S3 extensions */ 200 #define SEQ_ID_UNLOCK_EXT 0x08 201 #define SEQ_ID_MMIO_SELECT 0x09 /* Trio64: SEQ_ID_EXT_SEQ_REG9 */ 202 #define SEQ_ID_BUS_REQ_CNTL 0x0A 203 #define SEQ_ID_EXT_MISC_SEQ 0x0B 204 #define SEQ_ID_UNKNOWN4 0x0C 205 #define SEQ_ID_EXT_SEQ 0x0D 206 #define SEQ_ID_UNKNOWN5 0x0E 207 #define SEQ_ID_UNKNOWN6 0x0F 208 #define SEQ_ID_MCLK_LO 0x10 209 #define SEQ_ID_MCLK_HI 0x11 210 #define SEQ_ID_DCLK_LO 0x12 211 #define SEQ_ID_DCLK_HI 0x13 212 #define SEQ_ID_CLKSYN_CNTL_1 0x14 213 #define SEQ_ID_CLKSYN_CNTL_2 0x15 214 #define SEQ_ID_CLKSYN_TEST_HI 0x16 /* reserved for S3 testing of the */ 215 #define SEQ_ID_CLKSYN_TEST_LO 0x17 /* internal clock synthesizer */ 216 #define SEQ_ID_RAMDAC_CNTL 0x18 217 #define SEQ_ID_MORE_MAGIC 0x1A /* not available on the Virge */ 218 #define SEQ_ID_SIGNAL_SELECT 0x1C 219 220 /* CRT Controller: */ 221 #define CRT_ADDRESS 0x03D4 222 #define CRT_ADDRESS_R 0x03D5 223 #define CRT_ADDRESS_W 0x03D5 224 #define CRT_ID_HOR_TOTAL 0x00 225 #define CRT_ID_HOR_DISP_ENA_END 0x01 226 #define CRT_ID_START_HOR_BLANK 0x02 227 #define CRT_ID_END_HOR_BLANK 0x03 228 #define CRT_ID_START_HOR_RETR 0x04 229 #define CRT_ID_END_HOR_RETR 0x05 230 #define CRT_ID_VER_TOTAL 0x06 231 #define CRT_ID_OVERFLOW 0x07 232 #define CRT_ID_PRESET_ROW_SCAN 0x08 233 #define CRT_ID_MAX_SCAN_LINE 0x09 234 #define CRT_ID_CURSOR_START 0x0A 235 #define CRT_ID_CURSOR_END 0x0B 236 #define CRT_ID_START_ADDR_HIGH 0x0C 237 #define CRT_ID_START_ADDR_LOW 0x0D 238 #define CRT_ID_CURSOR_LOC_HIGH 0x0E 239 #define CRT_ID_CURSOR_LOC_LOW 0x0F 240 #define CRT_ID_START_VER_RETR 0x10 241 #define CRT_ID_END_VER_RETR 0x11 242 #define CRT_ID_VER_DISP_ENA_END 0x12 243 #define CRT_ID_SCREEN_OFFSET 0x13 244 #define CRT_ID_UNDERLINE_LOC 0x14 245 #define CRT_ID_START_VER_BLANK 0x15 246 #define CRT_ID_END_VER_BLANK 0x16 247 #define CRT_ID_MODE_CONTROL 0x17 248 #define CRT_ID_LINE_COMPARE 0x18 249 #define CRT_ID_GD_LATCH_RBACK 0x22 250 #define CRT_ID_ACT_TOGGLE_RBACK 0x24 251 #define CRT_ID_ACT_INDEX_RBACK 0x26 252 /* S3 extensions: S3 VGA Registers */ 253 #define CRT_ID_DEVICE_HIGH 0x2D 254 #define CRT_ID_DEVICE_LOW 0x2E 255 #define CRT_ID_REVISION 0x2F 256 #define CRT_ID_CHIP_ID_REV 0x30 257 #define CRT_ID_MEMORY_CONF 0x31 258 #define CRT_ID_BACKWAD_COMP_1 0x32 259 #define CRT_ID_BACKWAD_COMP_2 0x33 260 #define CRT_ID_BACKWAD_COMP_3 0x34 261 #define CRT_ID_REGISTER_LOCK 0x35 262 #define CRT_ID_CONFIG_1 0x36 263 #define CRT_ID_CONFIG_2 0x37 264 #define CRT_ID_REGISTER_LOCK_1 0x38 265 #define CRT_ID_REGISTER_LOCK_2 0x39 266 #define CRT_ID_MISC_1 0x3A 267 #define CRT_ID_DISPLAY_FIFO 0x3B 268 #define CRT_ID_LACE_RETR_START 0x3C 269 /* S3 extensions: System Control Registers */ 270 #define CRT_ID_SYSTEM_CONFIG 0x40 271 #define CRT_ID_BIOS_FLAG 0x41 272 #define CRT_ID_LACE_CONTROL 0x42 273 #define CRT_ID_EXT_MODE 0x43 274 #define CRT_ID_HWGC_MODE 0x45 /* HWGC = Hardware Graphics Cursor */ 275 #define CRT_ID_HWGC_ORIGIN_X_HI 0x46 276 #define CRT_ID_HWGC_ORIGIN_X_LO 0x47 277 #define CRT_ID_HWGC_ORIGIN_Y_HI 0x48 278 #define CRT_ID_HWGC_ORIGIN_Y_LO 0x49 279 #define CRT_ID_HWGC_FG_STACK 0x4A 280 #define CRT_ID_HWGC_BG_STACK 0x4B 281 #define CRT_ID_HWGC_START_AD_HI 0x4C 282 #define CRT_ID_HWGC_START_AD_LO 0x4D 283 #define CRT_ID_HWGC_DSTART_X 0x4E 284 #define CRT_ID_HWGC_DSTART_Y 0x4F 285 /* S3 extensions: System Extension Registers */ 286 #define CRT_ID_EXT_SYS_CNTL_1 0x50 287 #define CRT_ID_EXT_SYS_CNTL_2 0x51 288 #define CRT_ID_EXT_BIOS_FLAG_1 0x52 289 #define CRT_ID_EXT_MEM_CNTL_1 0x53 290 #define CRT_ID_EXT_MEM_CNTL_2 0x54 291 #define CRT_ID_EXT_DAC_CNTL 0x55 292 #define CRT_ID_EX_SYNC_1 0x56 293 #define CRT_ID_EX_SYNC_2 0x57 294 #define CRT_ID_LAW_CNTL 0x58 /* LAW = Linear Address Window */ 295 #define CRT_ID_LAW_POS_HI 0x59 296 #define CRT_ID_LAW_POS_LO 0x5A 297 #define CRT_ID_GOUT_PORT 0x5C 298 #define CRT_ID_EXT_HOR_OVF 0x5D 299 #define CRT_ID_EXT_VER_OVF 0x5E 300 #define CRT_ID_EXT_MEM_CNTL_3 0x60 301 #define CRT_ID_EXT_MEM_CNTL_4 0x61 /* only available on the Virge */ 302 #define CRT_ID_EX_SYNC_3 0x63 /* not available on the Virge */ 303 #define CRT_ID_EXT_MISC_CNTL 0x65 304 #define CRT_ID_EXT_MISC_CNTL_1 0x66 305 #define CRT_ID_EXT_MISC_CNTL_2 0x67 306 #define CRT_ID_CONFIG_3 0x68 307 #define CRT_ID_EXT_SYS_CNTL_3 0x69 308 #define CRT_ID_EXT_SYS_CNTL_4 0x6A 309 #define CRT_ID_EXT_BIOS_FLAG_3 0x6B 310 #define CRT_ID_EXT_BIOS_FLAG_4 0x6C 311 #define CRT_ID_EXT_BIOS_FLAG_5 0x6D /* only available on the Virge */ 312 #define CRT_ID_RAMDAC_SIG_TEST 0x6E /* only available on the Virge */ 313 #define CRT_ID_CONFIG_4 0x6F /* only available on the Virge */ 314 315 /* Streams Processor */ 316 #define SP_PRIMARY_CONTROL 0x8180 317 #define SP_COLOR_CHROMA_KEY_CONTROL 0x8184 318 #define SP_SECONDARY_CONTROL 0x8190 319 #define SP_CHROMA_KEY_UPPER_BOUND 0x8194 320 #define SP_SECONDARY_CONSTANTS 0x8198 321 #define SP_BLEND_CONTROL 0x81A0 322 #define SP_PRIMARY_ADDRESS_0 0x81C0 323 #define SP_PRIMARY_ADDRESS_1 0x81C4 324 #define SP_PRIMARY_STRIDE 0x81C8 325 #define SP_DOUBLE_BUFFER_LPB_SUPPORT 0x81CC 326 #define SP_SECONDARY_ADDRESS_0 0x81D0 327 #define SP_SECONDARY_ADDRESS_1 0x81D4 328 #define SP_SECONDARY_STRIDE 0x81D8 329 #define SP_OPAQUE_OVERLAY_CONTROL 0x81DC 330 #define SP_K1_VERTICAL_SCALE_FACTOR 0x81E0 331 #define SP_K2_VERTICAL_SCALE_FACTOR 0x81E4 332 #define SP_DDA_VERTICAL_ACCUMULATOR 0x81E8 333 #define SP_FIFO_CONTROL 0x81EC 334 #define SP_PRIMARY_WINDOW_TOP_LEFT 0x81F0 335 #define SP_PRIMARY_WINDOW_SIZE 0x81F4 336 #define SP_SECONDARY_WINDOW_TOP_LEFT 0x81F8 337 #define SP_SECONDARY_WINDOW_SIZE 0x81FC 338 339 /* Memory Port Controller */ 340 #define MPC_FIFO_CONTROL 0x8200 341 #define MPC_MIU_CONTROL 0x8204 342 #define MPC_STREAMS_TIMEOUT 0x8208 343 #define MPC_MISC_TIMEOUT 0x820C 344 #define MPC_DMA_READ_BASE_ADDRESS 0x8220 345 #define MPC_DMA_READ_STRIDE_WIDTH 0x8224 346 347 /* Miscellaneous Registers */ 348 #define MR_SUBSYSTEM_STATUS_CNTL 0x8504 349 #define MR_ADVANCED_FUNCTION_CONTROL 0x850C 350 351 /* S3d Engine */ 352 #define S3D_BIT_BLT_RECT_FILL 0xA400 353 #define S3D_LINE_2D 0xA800 354 #define S3D_POLYGON_2D 0xAC00 355 #define S3D_LINE_3D 0xB000 356 #define S3D_TRIANGLE_3D 0xB400 357 358 #define BLT_ADDRESS 0xA4D4 359 #define BLT_SOURCE_ADDRESS 0xA4D4 360 #define BLT_DEST_ADDRESS 0xA4D8 361 #define BLT_CLIP_LEFT_RIGHT 0xA4DC 362 #define BLT_CLIP_LEFT BLT_CLIP_LEFT_RIGHT 363 #define BLT_CLIP_RIGHT 0xA4DE 364 #define BLT_CLIP_TOP_BOTTOM 0xA4E0 365 #define BLT_CLIP_BOTTOM BLT_CLIP_TOP_BOTTOM 366 #define BLT_CLIP_TOP 0xA4E2 367 #define BLT_DEST_SOURCE_PITCH 0xA4E4 368 #define BLT_SOURCE_PITCH BLT_DEST_SOURCE_PITCH 369 #define BLT_DEST_PITCH 0xA4E6 370 #define BLT_MONO_PATTERN 0xA4E8 371 #define BLT_MONO_PATTERN_0 BLT_MONO_PATTERN 372 #define BLT_MONO_PATTERN_1 0xA4EC 373 #define BLT_PATTERN_BG_COLOR 0xA4F0 374 #define BLT_PATTERN_BG_COLOR_TRUE_COLOR BLT_PATTERN_BG_COLOR 375 #define BLT_PATTERN_BG_COLOR_ALPHA BLT_PATTERN_BG_COLOR 376 #define BLT_PATTERN_BG_COLOR_RED 0xA4F1 377 #define BLT_PATTERN_BG_COLOR_HI_COLOR 0xA4F2 378 #define BLT_PATTERN_BG_COLOR_GREEN BLT_PATTERN_BG_COLOR_HI_COLOR 379 #define BLT_PATTERN_BG_COLOR_INDEX 0xA4F3 380 #define BLT_PATTERN_BG_COLOR_BLUE BLT_PATTERN_BG_COLOR_INDEX 381 #define BLT_PATTERN_FG_COLOR 0xA4F4 382 #define BLT_PATTERN_FG_COLOR_TRUE_COLOR BLT_PATTERN_FG_COLOR 383 #define BLT_PATTERN_FG_COLOR_ALPHA BLT_PATTERN_FG_COLOR 384 #define BLT_PATTERN_FG_COLOR_RED 0xA4F5 385 #define BLT_PATTERN_FG_COLOR_HI_COLOR 0xA4F6 386 #define BLT_PATTERN_FG_COLOR_GREEN BLT_PATTERN_FG_COLOR_HI_COLOR 387 #define BLT_PATTERN_FG_COLOR_INDEX 0xA4F7 388 #define BLT_PATTERN_FG_COLOR_BLUE BLT_PATTERN_FG_COLOR_INDEX 389 #define BLT_SOURCE_BG_COLOR 0xA4F8 390 #define BLT_SOURCE_BG_COLOR_TRUE_COLOR BLT_SOURCE_BG_COLOR 391 #define BLT_SOURCE_BG_COLOR_ALPHA BLT_SOURCE_BG_COLOR 392 #define BLT_SOURCE_BG_COLOR_RED 0xA4F9 393 #define BLT_SOURCE_BG_COLOR_HI_COLOR 0xA4FA 394 #define BLT_SOURCE_BG_COLOR_GREEN BLT_SOURCE_BG_COLOR_HI_COLOR 395 #define BLT_SOURCE_BG_COLOR_INDEX 0xA4FB 396 #define BLT_SOURCE_BG_COLOR_BLUE BLT_SOURCE_BG_COLOR_INDEX 397 #define BLT_SOURCE_FG_COLOR 0xA4FC 398 #define BLT_SOURCE_FG_COLOR_TRUE_COLOR BLT_SOURCE_FG_COLOR 399 #define BLT_SOURCE_FG_COLOR_ALPHA BLT_SOURCE_FG_COLOR 400 #define BLT_SOURCE_FG_COLOR_RED 0xA4FD 401 #define BLT_SOURCE_FG_COLOR_HI_COLOR 0xA4FE 402 #define BLT_SOURCE_FG_COLOR_GREEN BLT_SOURCE_FG_COLOR_HI_COLOR 403 #define BLT_SOURCE_FG_COLOR_INDEX 0xA4FF 404 #define BLT_SOURCE_FG_COLOR_BLUE BLT_SOURCE_FG_COLOR_INDEX 405 #define BLT_COMMAND_SET 0xA500 406 #define BLT_WIDTH_HEIGHT 0xA504 407 #define BLT_HEIGHT BLT_WIDTH_HEIGHT 408 #define BLT_WIDTH 0xA506 409 #define BLT_SOURCE_XY 0xA508 410 #define BLT_SOURCE_Y BLT_SOURCE_XY 411 #define BLT_SOURCE_X 0xA50A 412 #define BLT_DESTINATION_XY 0xA50C 413 #define BLT_DESTINATION_Y BLT_DESTINATION_XY 414 #define BLT_DESTINATION_X 0xA50E 415 416 #define L2D_ADDRESS 0xA8D4 417 #define L2D_SOURCE_ADDRESS 0xA8D4 418 #define L2D_DEST_ADDRESS 0xA8D8 419 #define L2D_CLIP_LEFT_RIGHT 0xA8DC 420 #define L2D_CLIP_LEFT L2D_CLIP_LEFT_RIGHT 421 #define L2D_CLIP_RIGHT 0xA8DE 422 #define L2D_CLIP_TOP_BOTTOM 0xA8E0 423 #define L2D_CLIP_BOTTOM L2D_CLIP_TOP_BOTTOM 424 #define L2D_CLIP_TOP 0xA8E2 425 #define L2D_DEST_SOURCE_PITCH 0xA8E4 426 #define L2D_SOURCE_PITCH L2D_DEST_SOURCE_PITCH 427 #define L2D_DEST_PITCH 0xA8E6 428 #define L2D_PAD_0 0xA8E8 429 #define L2D_PATTERN_FG_COLOR_TRUE_COLOR 0xA8F4 430 #define L2D_PATTERN_FG_COLOR_ALPHA L2D_PATTERN_FG_COLOR_TRUECOLOR 431 #define L2D_PATTERN_FG_COLOR_RED 0xA8F5 432 #define L2D_PATTERN_FG_COLOR_HI_COLOR 0xA8F6 433 #define L2D_PATTERN_FG_COLOR_GREEN L2D_PATTERN_FG_COLOR_HICOLOR 434 #define L2D_PATTERN_FG_COLOR_INDEX 0xA8F7 435 #define L2D_PATTERN_FG_COLOR_BLUE L2D_PATTERN_FG_COLOR_INDEX 436 #define L2D_PAD_1 0xA8F8 437 #define L2D_COMMAND_SET 0xA900 438 #define L2D_PAD_2 0xA904 439 #define L2D_END_0_END_1 0xA96C 440 #define L2D_END_1 L2D_END_0_END_1 441 #define L2D_END_0 0xA96E 442 #define L2D_DX 0xA970 443 #define L2D_X_START 0xA974 444 #define L2D_Y_START 0xA978 445 #define L2D_Y_COUNT 0xA97C 446 447 #define P2D_ADDRESS 0xACD4 448 #define P2D_SOURCE_ADDRESS 0xACD4 449 #define P2D_DEST_ADDRESS 0xACD8 450 #define P2D_CLIP_LEFT_RIGHT 0xACDC 451 #define P2D_CLIP_LEFT P2D_CLIP_LEFT_RIGHT 452 #define P2D_CLIP_RIGHT 0xACDE 453 #define P2D_CLIP_TOP_BOTTOM 0xACE0 454 #define P2D_CLIP_BOTTOM P2D_CLIP_TOP_BOTTOM 455 #define P2D_CLIP_TOP 0xACE2 456 #define P2D_DEST_SOURCE_PITCH 0xACE4 457 #define P2D_SOURCE_PITCH P2D_DEST_SOURCE_PITCH 458 #define P2D_DEST_PITCH 0xACE6 459 #define P2D_MONO_PATTERN 0xACE8 460 #define P2D_PATTERN_BG_COLOR_TRUE_COLOR 0xACF0 461 #define P2D_PATTERN_BG_COLOR_ALPHA P2D_PATTERN_BG_COLOR_TRUE_COLOR 462 #define P2D_PATTERN_BG_COLOR_RED 0xACF1 463 #define P2D_PATTERN_BG_COLOR_HI_COLOR 0xACF2 464 #define P2D_PATTERN_BG_COLOR_GREEN P2D_PATTERN_BG_COLOR_HI_COLOR 465 #define P2D_PATTERN_BG_COLOR_INDEX 0xACF3 466 #define P2D_PATTERN_BG_COLOR_BLUE P2D_PATTERN_BG_COLOR_INDEX 467 #define P2D_PATTERN_FG_COLOR_TRUE_COLOR 0xACF4 468 #define P2D_PATTERN_FG_COLOR_ALPHA P2D_PATTERN_FG_COLOR_TRUE_COLOR 469 #define P2D_PATTERN_FG_COLOR_RED 0xACF5 470 #define P2D_PATTERN_FG_COLOR_HI_COLOR 0xACF6 471 #define P2D_PATTERN_FG_COLOR_GREEN P2D_PATTERN_FG_COLOR_HI_COLOR 472 #define P2D_PATTERN_FG_COLOR_INDEX 0xACF7 473 #define P2D_PATTERN_FG_COLOR_BLUE P2D_PATTERN_FG_COLOR_INDEX 474 #define P2D_PAD_1 0xACF8 475 #define P2D_COMMAND_SET 0xAD00 476 #define P2D_PAD_2 0xAD04 477 #define P2D_RIGHT_DX 0xAD68 478 #define P2D_RIGHT_X_START 0xAD6C 479 #define P2D_LEFT_DX 0xAD70 480 #define P2D_LEFT_X_START 0xAD74 481 #define P2D_Y_START 0xAD78 482 #define P2D_Y_COUNT 0xAD7C 483 484 #define CMD_NOP (7 << 27) /* %1111 << 27 */ 485 #define CMD_LINE (3 << 27) /* %0011 << 27 */ 486 #define CMD_RECT (4 << 27) /* %0010 << 27 */ 487 #define CMD_POLYGON (5 << 27) /* %0101 << 27 */ 488 #define CMD_BITBLT (0 << 27) /* %0000 << 27 */ 489 490 #define CMD_SKIP_TRANSFER_BYTES_1 (1 << 12) /* %01 << 12 */ 491 #define CMD_SKIP_TRANSFER_BYTES_2 (2 << 12) /* %10 << 12 */ 492 #define CMD_SKIP_TRANSFER_BYTES_3 (3 << 12) /* %11 << 12 */ 493 494 #define CMD_TRANSFER_ALIGNMENT_BYTE (0 << 10) /* %00 << 10 */ 495 #define CMD_TRANSFER_ALIGNMENT_WORD (1 << 10) /* %01 << 10 */ 496 #define CMD_TRANSFER_ALIGNMENT_DOUBLEWORD (2 << 10) /* %10 << 10 */ 497 498 #define CMD_CHUNKY (0 << 2) /* %00 << 2 */ 499 #define CMD_HI_COLOR (1 << 2) /* %01 << 2 */ 500 #define CMD_TRUE_COLOR (2 << 2) /* %10 << 2 */ 501 502 #define ROP_FALSE 0x00 503 #define ROP_NOR 0x10 504 #define ROP_ONLYDST 0x20 505 #define ROP_NOTSRC 0x30 506 #define ROP_ONLYSRC 0x40 507 #define ROP_NOTDST 0x50 508 #define ROP_EOR 0x60 509 #define ROP_NAND 0x70 510 #define ROP_AND 0x80 511 #define ROP_NEOR 0x90 512 #define ROP_DST 0xA0 513 #define ROP_NOTONLYSRC 0xB0 514 #define ROP_SRC 0xC0 515 #define ROP_NOTONLYDST 0xD0 516 #define ROP_OR 0xE0 517 #define ROP_TRUE 0xF0 518 519 /* Pass-through */ 520 #if 0 /* XXX */ 521 #define PASS_ADDRESS 0x 522 #define PASS_ADDRESS_W 0x 523 #endif 524 525 /* Video DAC */ 526 #define VDAC_ADDRESS 0x03C8 527 #define VDAC_ADDRESS_W 0x03C8 528 #define VDAC_ADDRESS_R 0x03C7 529 #define VDAC_STATE 0x03C7 530 #define VDAC_DATA 0x03C9 531 #define VDAC_MASK 0x03C6 532 533 534 #define WGfx(ba, idx, val) \ 535 do { vgaw(ba, GCT_ADDRESS, idx); vgaw(ba, GCT_ADDRESS_W , val); } while (0) 536 537 #define WSeq(ba, idx, val) \ 538 do { vgaw(ba, SEQ_ADDRESS, idx); vgaw(ba, SEQ_ADDRESS_W , val); } while (0) 539 540 #define WCrt(ba, idx, val) \ 541 do { vgaw(ba, CRT_ADDRESS, idx); vgaw(ba, CRT_ADDRESS_W , val); } while (0) 542 543 #define WAttr(ba, idx, val) \ 544 do { \ 545 unsigned char tmp;\ 546 tmp = vgar(ba, ACT_ADDRESS_RESET);\ 547 vgaw(ba, ACT_ADDRESS_W, idx);\ 548 vgaw(ba, ACT_ADDRESS_W, val);\ 549 } while (0) 550 551 552 #define SetTextPlane(ba, m) \ 553 do { \ 554 WGfx(ba, GCT_ID_READ_MAP_SELECT, m & 3 );\ 555 WSeq(ba, SEQ_ID_MAP_MASK, (1 << (m & 3)));\ 556 } while (0) 557 558 559 /* Gfx engine busy wait */ 560 561 static inline void 562 GfxBusyWait (volatile void *ba) 563 { 564 int test; 565 566 do { 567 test = vgar32(ba, MR_SUBSYSTEM_STATUS_CNTL); 568 __asm volatile ("nop"); 569 } while (!(test & (1 << 13))); 570 } 571 572 573 static inline void 574 GfxFifoWait(volatile void *ba) 575 { 576 #if 0 /* XXX */ 577 int test; 578 579 do { 580 test = vgar32(ba, MR_SUBSYSTEM_STATUS_CNTL); 581 } while (test & 0x0f); 582 #endif 583 } 584 585 586 /* Special wakeup/passthrough registers on graphics boards 587 * 588 * The methods have diverged a bit for each board, so 589 * WPass(P) has been converted into a set of specific 590 * inline functions. 591 */ 592 593 static inline unsigned char 594 RAttr(volatile void *ba, short idx) 595 { 596 597 vgaw(ba, ACT_ADDRESS_W, idx); 598 delay(0); 599 return vgar(ba, ACT_ADDRESS_R); 600 } 601 602 static inline unsigned char 603 RSeq(volatile void *ba, short idx) 604 { 605 vgaw(ba, SEQ_ADDRESS, idx); 606 return vgar(ba, SEQ_ADDRESS_R); 607 } 608 609 static inline unsigned char 610 RCrt(volatile void *ba, short idx) 611 { 612 vgaw(ba, CRT_ADDRESS, idx); 613 return vgar(ba, CRT_ADDRESS_R); 614 } 615 616 static inline unsigned char 617 RGfx(volatile void *ba, short idx) 618 { 619 vgaw(ba, GCT_ADDRESS, idx); 620 return vgar(ba, GCT_ADDRESS_R); 621 } 622 623 #endif /* _GRF_CV3DREG_H */ 624
Indexes created Tue Oct 07 21:09:53 GMT 2025