grf_cvreg.h revision 1.1
1 /* 2 * Copyright (c) 1995 Michael Teske 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 3. All advertising materials mentioning features or use of this software 14 * must display the following acknowledgement: 15 * This product includes software developed by Ezra Story, by Kari 16 * Mettinen and by Bernd Ernesti. 17 * 4. The name of the author may not be used to endorse or promote products 18 * derived from this software without specific prior written permission 19 * 20 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 21 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 22 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 23 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 24 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 25 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 26 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 27 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 28 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 29 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 30 */ 31 32 #ifndef _GRF_CVREG_H 33 #define _GRF_CVREG_H 34 35 /* 36 * This is derived from ciruss driver source 37 */ 38 39 /* Extension to grfvideo_mode to support text modes. 40 * This can be passed to both text & gfx functions 41 * without worry. If gv.depth == 4, then the extended 42 * fields for a text mode are present. 43 */ 44 45 struct grfcvtext_mode { 46 struct grfvideo_mode gv; 47 unsigned short fx; /* font x dimension */ 48 unsigned short fy; /* font y dimension */ 49 unsigned short cols; /* screen dimensions */ 50 unsigned short rows; 51 void *fdata; /* font data */ 52 unsigned short fdstart; 53 unsigned short fdend; 54 }; 55 56 57 /* read VGA register */ 58 #define vgar(ba, reg) (*(((volatile unsigned char *)ba)+reg)) 59 60 /* write VGA register */ 61 #define vgaw(ba, reg, val) \ 62 *(((volatile unsigned char *)ba)+reg) = ((val) & 0xff) 63 64 /* 65 * defines for the used register addresses (mw) 66 * 67 * NOTE: there are some registers that have different addresses when 68 * in mono or color mode. We only support color mode, and thus 69 * some addresses won't work in mono-mode! 70 * 71 * General and VGA-registers taken from retina driver. Fixed a few 72 * bugs in it. (SR and GR read address is Port + 1, NOT Port) 73 * 74 */ 75 76 /* General Registers: */ 77 #define GREG_MISC_OUTPUT_R 0x03CC 78 #define GREG_MISC_OUTPUT_W 0x03C2 79 #define GREG_FEATURE_CONTROL_R 0x03CA 80 #define GREG_FEATURE_CONTROL_W 0x03DA 81 #define GREG_INPUT_STATUS0_R 0x03C2 82 #define GREG_INPUT_STATUS1_R 0x03DA 83 84 /* Setup Registers: */ 85 #define SREG_OPTION_SELECT 0x0102 86 #define SREG_VIDEO_SUBS_ENABLE 0x46E8 87 88 /* Attribute Controller: */ 89 #define ACT_ADDRESS 0x03C0 90 #define ACT_ADDRESS_R 0x03C1 91 #define ACT_ADDRESS_W 0x03C0 92 #define ACT_ADDRESS_RESET 0x03DA 93 #define ACT_ID_PALETTE0 0x00 94 #define ACT_ID_PALETTE1 0x01 95 #define ACT_ID_PALETTE2 0x02 96 #define ACT_ID_PALETTE3 0x03 97 #define ACT_ID_PALETTE4 0x04 98 #define ACT_ID_PALETTE5 0x05 99 #define ACT_ID_PALETTE6 0x06 100 #define ACT_ID_PALETTE7 0x07 101 #define ACT_ID_PALETTE8 0x08 102 #define ACT_ID_PALETTE9 0x09 103 #define ACT_ID_PALETTE10 0x0A 104 #define ACT_ID_PALETTE11 0x0B 105 #define ACT_ID_PALETTE12 0x0C 106 #define ACT_ID_PALETTE13 0x0D 107 #define ACT_ID_PALETTE14 0x0E 108 #define ACT_ID_PALETTE15 0x0F 109 #define ACT_ID_ATTR_MODE_CNTL 0x10 110 #define ACT_ID_OVERSCAN_COLOR 0x11 111 #define ACT_ID_COLOR_PLANE_ENA 0x12 112 #define ACT_ID_HOR_PEL_PANNING 0x13 113 #define ACT_ID_COLOR_SELECT 0x14 114 115 /* Graphics Controller: */ 116 #define GCT_ADDRESS 0x03CE 117 #define GCT_ADDRESS_R 0x03CF 118 #define GCT_ADDRESS_W 0x03CF 119 #define GCT_ID_SET_RESET 0x00 120 #define GCT_ID_ENABLE_SET_RESET 0x01 121 #define GCT_ID_COLOR_COMPARE 0x02 122 #define GCT_ID_DATA_ROTATE 0x03 123 #define GCT_ID_READ_MAP_SELECT 0x04 124 #define GCT_ID_GRAPHICS_MODE 0x05 125 #define GCT_ID_MISC 0x06 126 #define GCT_ID_COLOR_XCARE 0x07 127 #define GCT_ID_BITMASK 0x08 128 129 /* Sequencer: */ 130 #define SEQ_ADDRESS 0x03C4 131 #define SEQ_ADDRESS_R 0x03C5 132 #define SEQ_ADDRESS_W 0x03C5 133 #define SEQ_ID_RESET 0x00 134 #define SEQ_ID_CLOCKING_MODE 0x01 135 #define SEQ_ID_MAP_MASK 0x02 136 #define SEQ_ID_CHAR_MAP_SELECT 0x03 137 #define SEQ_ID_MEMORY_MODE 0x04 138 #define SEQ_ID_UNKNOWN1 0x05 139 #define SEQ_ID_UNKNOWN2 0x06 140 #define SEQ_ID_UNKNOWN3 0x07 141 /* S3 extensions */ 142 #define SEQ_ID_UNLOCK_EXT 0x08 143 #define SEQ_ID_EXT_SEQ_REG9 0x09 144 #define SEQ_ID_BUS_REQ_CNTL 0x0A 145 #define SEQ_ID_EXT_MISC_SEQ 0x0B 146 #define SEQ_ID_UNKNOWN4 0x0C 147 #define SEQ_ID_EXT_SEQ 0x0D 148 #define SEQ_ID_UNKNOWN5 0x0E 149 #define SEQ_ID_UNKNOWN6 0x0F 150 #define SEQ_ID_MCLK_LO 0x10 151 #define SEQ_ID_MCLK_HI 0x11 152 #define SEQ_ID_DCLK_LO 0x12 153 #define SEQ_ID_DCLK_HI 0x13 154 #define SEQ_ID_CLKSYN_CNTL_1 0x14 155 #define SEQ_ID_CLKSYN_CNTL_2 0x15 156 #define SEQ_ID_CLKSYN_TEST_HI 0x16 /* reserved for S3 testing of the */ 157 #define SEQ_ID_CLKSYN_TEST_LO 0x17 /* internal clock synthesizer */ 158 #define SEQ_ID_RAMDAC_CNTL 0x18 159 160 /* CRT Controller: */ 161 #define CRT_ADDRESS 0x03D4 162 #define CRT_ADDRESS_R 0x03D5 163 #define CRT_ADDRESS_W 0x03D5 164 #define CRT_ID_HOR_TOTAL 0x00 165 #define CRT_ID_HOR_DISP_ENA_END 0x01 166 #define CRT_ID_START_HOR_BLANK 0x02 167 #define CRT_ID_END_HOR_BLANK 0x03 168 #define CRT_ID_START_HOR_RETR 0x04 169 #define CRT_ID_END_HOR_RETR 0x05 170 #define CRT_ID_VER_TOTAL 0x06 171 #define CRT_ID_OVERFLOW 0x07 172 #define CRT_ID_PRESET_ROW_SCAN 0x08 173 #define CRT_ID_MAX_SCAN_LINE 0x09 174 #define CRT_ID_CURSOR_START 0x0A 175 #define CRT_ID_CURSOR_END 0x0B 176 #define CRT_ID_START_ADDR_HIGH 0x0C 177 #define CRT_ID_START_ADDR_LOW 0x0D 178 #define CRT_ID_CURSOR_LOC_HIGH 0x0E 179 #define CRT_ID_CURSOR_LOC_LOW 0x0F 180 #define CRT_ID_START_VER_RETR 0x10 181 #define CRT_ID_END_VER_RETR 0x11 182 #define CRT_ID_VER_DISP_ENA_END 0x12 183 #define CRT_ID_SCREEN_OFFSET 0x13 184 #define CRT_ID_UNDERLINE_LOC 0x14 185 #define CRT_ID_START_VER_BLANK 0x15 186 #define CRT_ID_END_VER_BLANK 0x16 187 #define CRT_ID_MODE_CONTROL 0x17 188 #define CRT_ID_LINE_COMPARE 0x18 189 #define CRT_ID_GD_LATCH_RBACK 0x22 190 #define CRT_ID_ACT_TOGGLE_RBACK 0x24 191 #define CRT_ID_ACT_INDEX_RBACK 0x26 192 /* S3 extensions: S3 VGA Registers */ 193 #define CRT_ID_DEVICE_HIGH 0x2D 194 #define CRT_ID_DEVICE_LOW 0x2E 195 #define CRT_ID_REVISION 0x2F 196 #define CRT_ID_CHIP_ID_REV 0x30 197 #define CRT_ID_MEMORY_CONF 0x31 198 #define CRT_ID_BACKWAD_COMP_1 0x32 199 #define CRT_ID_BACKWAD_COMP_2 0x33 200 #define CRT_ID_BACKWAD_COMP_3 0x34 201 #define CRT_ID_REGISTER_LOCK 0x35 202 #define CRT_ID_CONFIG_1 0x36 203 #define CRT_ID_CONFIG_2 0x37 204 #define CRT_ID_REGISTER_LOCK_1 0x38 205 #define CRT_ID_REGISTER_LOCK_2 0x39 206 #define CRT_ID_MISC_1 0x3A 207 #define CRT_ID_DISPLAY_FIFO 0x3B 208 #define CRT_ID_LACE_RETR_START 0x3C 209 /* S3 extensions: System Control Registers */ 210 #define CRT_ID_SYSTEM_CONFIG 0x40 211 #define CRT_ID_BIOS_FLAG 0x41 212 #define CRT_ID_LACE_CONTROL 0x42 213 #define CRT_ID_EXT_MODE 0x43 214 #define CRT_ID_HWGC_MODE 0x45 /* HWGC = Hardware Graphics Cursor */ 215 #define CRT_ID_HWGC_ORIGIN_X_HI 0x46 216 #define CRT_ID_HWGC_ORIGIN_X_LO 0x47 217 #define CRT_ID_HWGC_ORIGIN_Y_HI 0x48 218 #define CRT_ID_HWGC_ORIGIN_Y_LO 0x49 219 #define CRT_ID_HWGC_FG_STACK 0x4A 220 #define CRT_ID_HWGC_BG_STACK 0x4B 221 #define CRT_ID_HWGC_START_AD_HI 0x4C 222 #define CRT_ID_HWGC_START_AD_LO 0x4D 223 #define CRT_ID_HWGC_DSTART_X 0x4E 224 #define CRT_ID_HWGC_DSTART_Y 0x4F 225 /* S3 extensions: System Extension Registers */ 226 #define CRT_ID_EXT_SYS_CNTL_1 0x50 227 #define CRT_ID_EXT_SYS_CNTL_2 0x51 228 #define CRT_ID_EXT_BIOS_FLAG_1 0x52 229 #define CRT_ID_EXT_MEM_CNTL_1 0x53 230 #define CRT_ID_EXT_MEM_CNTL_2 0x54 231 #define CRT_ID_EXT_DAC_CNTL 0x55 232 #define CRT_ID_EX_SYNC_1 0x56 233 #define CRT_ID_EX_SYNC_2 0x57 234 #define CRT_ID_LAW_CNTL 0x58 /* LAW = Linear Address Window */ 235 #define CRT_ID_LAW_POS_HI 0x59 236 #define CRT_ID_LAW_POS_LO 0x5A 237 #define CRT_ID_GOUT_PORT 0x5C 238 #define CRT_ID_EXT_HOR_OVF 0x5D 239 #define CRT_ID_EXT_VER_OVF 0x5E 240 #define CRT_ID_EXT_MEM_CNTL_3 0x60 241 #define CRT_ID_EX_SYNC_3 0x63 242 #define CRT_ID_EXT_MISC_CNTL 0x65 243 #define CRT_ID_EXT_MISC_CNTL_1 0x66 244 #define CRT_ID_EXT_MISC_CNTL_2 0x67 245 #define CRT_ID_CONFIG_3 0x68 246 #define CRT_ID_EXT_SYS_CNTL_3 0x69 247 #define CRT_ID_EXT_SYS_CNTL_4 0x6A 248 #define CRT_ID_EXT_BIOS_FLAG_3 0x6B 249 #define CRT_ID_EXT_BIOS_FLAG_4 0x6C 250 251 /* Enhanced Commands Registers: */ 252 #define ECR_SUBSYSTEM_STAT 0x42E8 253 #define ECR_SUBSYSTEM_CNTL 0x42E8 254 #define ECR_ADV_FUNC_CNTL 0x4AE8 255 #define ECR_CURRENT_Y_POS 0x82E8 256 #define ECR_CURRENT_Y_POS2 0x82EA /* Trio64 only */ 257 #define ECR_CURRENT_X_POS 0x86E8 258 #define ECR_CURRENT_X_POS2 0x86EA /* Trio64 only */ 259 #define ECR_DEST_Y__AX_STEP 0x8AE8 260 #define ECR_DEST_Y2__AX_STEP2 0x8AEA /* Trio64 only */ 261 #define ECR_DEST_X__DIA_STEP 0x8EE8 262 #define ECR_DEST_X2__DIA_STEP2 0x8EEA /* Trio64 only */ 263 #define ECR_ERR_TERM 0x92E8 264 #define ECR_ERR_TERM2 0x92EA /* Trio64 only */ 265 #define ECR_MAJ_AXIS_PIX_CNT 0x96E8 266 #define ECR_MAJ_AXIS_PIX_CNT2 0x96EA /* Trio64 only */ 267 #define ECR_GP_STAT 0x9AE8 /* GP = Graphics Processor */ 268 #define ECR_DRAW_CMD 0x9AE8 269 #define ECR_DRAW_CMD2 0x9AEA /* Trio64 only */ 270 #define ECR_SHORT_STROKE 0x9EE8 271 #define ECR_BKGD_COLOR 0xA2E8 /* BKGD = Background */ 272 #define ECR_FRGD_COLOR 0xA6E8 /* FRGD = Foreground */ 273 #define ECR_BITPLANE_WRITE_MASK 0xAAE8 274 #define ECR_BITPLANE_READ_MASK 0xAEE8 275 #define ECR_COLOR_COMPARE 0xB2E8 276 #define ECR_BKGD_MIX 0xB6E8 277 #define ECR_FRGD_MIX 0xBAE8 278 #define ECR_READ_REG_DATA 0xBEE8 279 #define ECR_ID_MIN_AXIS_PIX_CNT 0x00 280 #define ECR_ID_SCISSORS_TOP 0x01 281 #define ECR_ID_SCISSORS_LEFT 0x02 282 #define ECR_ID_SCISSORS_BUTTOM 0x03 283 #define ECR_ID_SCISSORS_RIGHT 0x04 284 #define ECR_ID_PIX_CNTL 0x0A 285 #define ECR_ID_MULT_CNTL_MISC_2 0x0D 286 #define ECR_ID_MULT_CNTL_MISC 0x0E 287 #define ECR_ID_READ_SEL 0x0F 288 #define ECR_PIX_TRANS 0xE2E8 289 #define ECR_PIX_TRANS_EXT 0xE2EA 290 #define ECR_PATTERN_Y 0xEAE8 /* Trio64 only */ 291 #define ECR_PATTERN_X 0xEAEA /* Trio64 only */ 292 293 294 /* Pass-through */ 295 #define PASS_ADDRESS 0x40001 296 #define PASS_ADDRESS_W 0x40001 297 298 /* Video DAC */ 299 #define VDAC_ADDRESS 0x03c8 300 #define VDAC_ADDRESS_W 0x03c8 301 #define VDAC_ADDRESS_R 0x03c7 302 #define VDAC_STATE 0x03c7 303 #define VDAC_DATA 0x03c9 304 #define VDAC_MASK 0x03c6 305 306 307 #define WGfx(ba, idx, val) \ 308 do { vgaw(ba, GCT_ADDRESS, idx); vgaw(ba, GCT_ADDRESS_W , val); } while (0) 309 310 #define WSeq(ba, idx, val) \ 311 do { vgaw(ba, SEQ_ADDRESS, idx); vgaw(ba, SEQ_ADDRESS_W , val); } while (0) 312 313 #define WCrt(ba, idx, val) \ 314 do { vgaw(ba, CRT_ADDRESS, idx); vgaw(ba, CRT_ADDRESS_W , val); } while (0) 315 316 #define WAttr(ba, idx, val) \ 317 do { \ 318 unsigned char tmp;\ 319 tmp = vgar(ba, ACT_ADDRESS_RESET);\ 320 vgaw(ba, ACT_ADDRESS_W, idx);\ 321 vgaw(ba, ACT_ADDRESS_W, val);\ 322 } while (0) 323 324 325 #define SetTextPlane(ba, m) \ 326 do { \ 327 WGfx(ba, GCT_ID_READ_MAP_SELECT, m & 3 );\ 328 WSeq(ba, SEQ_ID_MAP_MASK, (1 << (m & 3)));\ 329 } while (0) 330 331 /* Special wakeup/passthrough registers on graphics boards 332 * 333 * The methods have diverged a bit for each board, so 334 * WPass(P) has been converted into a set of specific 335 * inline functions. 336 */ 337 338 static inline unsigned char 339 RAttr(ba, idx) 340 volatile void *ba; 341 short idx; 342 { 343 344 vgaw(ba, ACT_ADDRESS_W, idx); 345 delay(0); 346 return vgar(ba, ACT_ADDRESS_R); 347 } 348 349 static inline unsigned char 350 RSeq(ba, idx) 351 volatile void *ba; 352 short idx; 353 { 354 vgaw(ba, SEQ_ADDRESS, idx); 355 return vgar(ba, SEQ_ADDRESS_R); 356 } 357 358 static inline unsigned char 359 RCrt(ba, idx) 360 volatile void *ba; 361 short idx; 362 { 363 vgaw(ba, CRT_ADDRESS, idx); 364 return vgar(ba, CRT_ADDRESS_R); 365 } 366 367 static inline unsigned char 368 RGfx(ba, idx) 369 volatile void *ba; 370 short idx; 371 { 372 vgaw(ba, GCT_ADDRESS, idx); 373 return vgar(ba, GCT_ADDRESS_R); 374 } 375 376 377 static inline void 378 cv_write_port(bits, BoardAddr) 379 unsigned short bits; 380 volatile unsigned char *BoardAddr; 381 { 382 volatile char *addr; 383 static unsigned char CVPortBits=0; /* mirror port bits here */ 384 385 addr = BoardAddr + 0x40001; 386 if (bits & 0x8000) 387 CVPortBits |= bits&0xFF; /* Set bits */ 388 else { 389 bits = bits & 0xFF; 390 bits = (~bits) & 0xFF ; 391 CVPortBits &= bits; /* Clear bits */ 392 } 393 394 *addr = CVPortBits; 395 } 396 397 #define set_port_bits(b, ba) cv_write_port((unsigned short )b | 0x8000,ba) 398 #define clear_port_bits(b, ba) cv_write_port((unsigned short )b & 0xff,ba) 399 400 401 /* 402 * Monitor Switch 403 * 0 = CyberVision Signal 404 * 1 = Amiga Signal, 405 * ba = boardaddr 406 */ 407 408 static inline void 409 cvscreen(toggle, ba) 410 char toggle; 411 volatile unsigned char *ba; 412 { 413 414 if (toggle) 415 cv_write_port (0x10, ba); 416 else 417 cv_write_port (0x8010, ba); 418 } 419 420 /* 0 = on, 1= off */ 421 /* ba= registerbase */ 422 static inline void 423 gfx_on_off(toggle, ba) 424 char toggle; 425 volatile unsigned char *ba; 426 { 427 unsigned char r; 428 429 toggle &= 0x1; 430 toggle = toggle << 5; 431 432 r = RSeq(ba, 0x1); 433 r &= 0xDF; /* Bit 5 auf 0!!! */ 434 WSeq(ba, 1, r | toggle); 435 } 436 437 int cv_mode __P((register struct grf_softc *gp, int cmd, void *arg, int a2, int a3)); 438 int cv_load_mon __P((struct grf_softc *gp, struct grfcvtext_mode *gv)); 439 int grfcv_cnprobe __P((void)); 440 #if 0 441 void grfcv_iteinit __P((struct grf_softc *gp)); 442 #endif 443 444 static unsigned char clocks[]={ 445 0x13, 0x61, 0x6b, 0x6d, 0x51, 0x69, 0x54, 0x69, 446 0x4f, 0x68, 0x6b, 0x6b, 0x18, 0x61, 0x7b, 0x6c, 447 0x51, 0x67, 0x24, 0x62, 0x56, 0x67, 0x77, 0x6a, 448 0x1d, 0x61, 0x53, 0x66, 0x6b, 0x68, 0x79, 0x69, 449 0x7c, 0x69, 0x7f, 0x69, 0x22, 0x61, 0x54, 0x65, 450 0x56, 0x65, 0x58, 0x65, 0x67, 0x66, 0x41, 0x63, 451 0x27, 0x61, 0x13, 0x41, 0x37, 0x62, 0x6b, 0x4d, 452 0x23, 0x43, 0x51, 0x49, 0x79, 0x66, 0x54, 0x49, 453 0x7d, 0x66, 0x34, 0x56, 0x4f, 0x63, 0x1f, 0x42, 454 0x6b, 0x4b, 0x7e, 0x4d, 0x18, 0x41, 0x2a, 0x43, 455 0x7b, 0x4c, 0x74, 0x4b, 0x51, 0x47, 0x65, 0x49, 456 0x24, 0x42, 0x68, 0x49, 0x56, 0x47, 0x75, 0x4a, 457 0x77, 0x4a, 0x31, 0x43, 0x1d, 0x41, 0x71, 0x49, 458 0x53, 0x46, 0x29, 0x42, 0x6b, 0x48, 0x1f, 0x41, 459 0x79, 0x49, 0x6f, 0x48, 0x7c, 0x49, 0x38, 0x43, 460 0x7f, 0x49, 0x5d, 0x46, 0x22, 0x41, 0x53, 0x45, 461 0x54, 0x45, 0x55, 0x45, 0x56, 0x45, 0x57, 0x45, 462 0x58, 0x45, 0x25, 0x41, 0x67, 0x46, 0x5b, 0x45, 463 0x41, 0x43, 0x78, 0x47, 0x27, 0x41, 0x51, 0x44, 464 0x13, 0x21, 0x7d, 0x47, 0x37, 0x42, 0x71, 0x46, 465 0x6b, 0x2d, 0x14, 0x21, 0x23, 0x23, 0x7d, 0x2f, 466 0x51, 0x29, 0x61, 0x2b, 0x79, 0x46, 0x1d, 0x22, 467 0x54, 0x29, 0x45, 0x27, 0x7d, 0x46, 0x7f, 0x46, 468 0x4f, 0x43, 0x2f, 0x41, 0x1f, 0x22, 0x6a, 0x2b, 469 0x6b, 0x2b, 0x5b, 0x29, 0x7e, 0x2d, 0x65, 0x44, 470 0x18, 0x21, 0x5e, 0x29, 0x2a, 0x23, 0x45, 0x26, 471 0x7b, 0x2c, 0x19, 0x21, 0x74, 0x2b, 0x75, 0x2b, 472 0x51, 0x27, 0x3f, 0x25, 0x65, 0x29, 0x40, 0x25, 473 0x24, 0x22, 0x41, 0x25, 0x68, 0x29, 0x42, 0x25, 474 0x56, 0x27, 0x7e, 0x2b, 0x75, 0x2a, 0x1c, 0x21, 475 0x77, 0x2a, 0x4f, 0x26, 0x31, 0x23, 0x6f, 0x29, 476 0x1d, 0x21, 0x32, 0x23, 0x71, 0x29, 0x72, 0x29, 477 0x53, 0x26, 0x69, 0x28, 0x29, 0x22, 0x75, 0x29, 478 0x6b, 0x28, 0x1f, 0x21, 0x1f, 0x21, 0x6d, 0x28, 479 0x79, 0x29, 0x2b, 0x22, 0x6f, 0x28, 0x59, 0x26, 480 0x7c, 0x29, 0x7d, 0x29, 0x38, 0x23, 0x21, 0x21, 481 0x7f, 0x29, 0x39, 0x23, 0x5d, 0x26, 0x75, 0x28, 482 0x22, 0x21, 0x77, 0x28, 0x53, 0x25, 0x6c, 0x27, 483 0x54, 0x25, 0x61, 0x26, 0x55, 0x25, 0x30, 0x22, 484 0x56, 0x25, 0x63, 0x26, 0x57, 0x25, 0x71, 0x27, 485 0x58, 0x25, 0x7f, 0x28, 0x25, 0x21, 0x74, 0x27, 486 0x67, 0x26, 0x40, 0x23, 0x5b, 0x25, 0x26, 0x21, 487 0x41, 0x23, 0x34, 0x22, 0x78, 0x27, 0x6b, 0x26, 488 0x27, 0x21, 0x35, 0x22, 0x51, 0x24, 0x7b, 0x27, 489 0x13, 0x1, 0x13, 0x1, 0x7d, 0x27, 0x4c, 0x9, 490 0x37, 0x22, 0x5b, 0xb, 0x71, 0x26, 0x5c, 0xb, 491 0x6b, 0xd, 0x47, 0x23, 0x14, 0x1, 0x4f, 0x9, 492 0x23, 0x3, 0x75, 0x26, 0x7d, 0xf, 0x1c, 0x2, 493 0x51, 0x9, 0x59, 0x24, 0x61, 0xb, 0x69, 0x25, 494 0x79, 0x26, 0x34, 0x5, 0x1d, 0x2, 0x6b, 0x25, 495 0x54, 0x9, 0x35, 0x5, 0x45, 0x7, 0x6d, 0x25, 496 0x7d, 0x26, 0x16, 0x1, 0x7f, 0x26, 0x77, 0xd, 497 0x4f, 0x23, 0x78, 0xd, 0x2f, 0x21, 0x27, 0x3, 498 0x1f, 0x2, 0x59, 0x9, 0x6a, 0xb, 0x73, 0x25, 499 0x6b, 0xb, 0x63, 0x24, 0x5b, 0x9, 0x20, 0x2, 500 0x7e, 0xd, 0x4b, 0x7, 0x65, 0x24, 0x43, 0x22, 501 0x18, 0x1, 0x6f, 0xb, 0x5e, 0x9, 0x70, 0xb, 502 0x2a, 0x3, 0x33, 0x4, 0x45, 0x6, 0x60, 0x9, 503 0x7b, 0xc, 0x19, 0x1, 0x19, 0x1, 0x7d, 0xc, 504 0x74, 0xb, 0x50, 0x7, 0x75, 0xb, 0x63, 0x9, 505 0x51, 0x7, 0x23, 0x2, 0x3f, 0x5, 0x1a, 0x1, 506 0x65, 0x9, 0x2d, 0x3, 0x40, 0x5, 0x0, 0x0, 507 }; 508 509 #endif /* _GRF_RHREG_H */ 510 511
Indexes created Fri Sep 26 08:10:20 GMT 2025